U.S. patent application number 12/260064 was filed with the patent office on 2009-03-26 for integrated half-bridge power circuit.
This patent application is currently assigned to NXP, B.V.. Invention is credited to Raymond J. Grover, Adrianus Willem Ludikhuize, Jacob Antonius Van der Pol.
Application Number | 20090079272 12/260064 |
Document ID | / |
Family ID | 32507891 |
Filed Date | 2009-03-26 |
United States Patent
Application |
20090079272 |
Kind Code |
A1 |
Ludikhuize; Adrianus Willem ;
et al. |
March 26, 2009 |
Integrated Half-Bridge Power Circuit
Abstract
A down converter includes an integrated circuit, which includes
a control FET (CF) and a synchronous rectifier FET (SF). The
control FET is a lateral double-diffused (LDMOS) FET, and the
conductivity-type of the LDMOS FET and the conductivity-type of the
substrate are of the same type.
Inventors: |
Ludikhuize; Adrianus Willem;
(Eindhoven, NL) ; Van der Pol; Jacob Antonius;
(Nijmegen, NL) ; Grover; Raymond J.; (Didsbury,
GB) |
Correspondence
Address: |
NXP, B.V.;NXP INTELLECTUAL PROPERTY DEPARTMENT
M/S41-SJ, 1109 MCKAY DRIVE
SAN JOSE
CA
95131
US
|
Assignee: |
NXP, B.V.
|
Family ID: |
32507891 |
Appl. No.: |
12/260064 |
Filed: |
October 28, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10537575 |
Jun 6, 2005 |
7459750 |
|
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PCT/IB2003/005806 |
Aug 12, 2003 |
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12260064 |
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Current U.S.
Class: |
307/112 ;
257/337; 257/E27.059 |
Current CPC
Class: |
Y02B 70/10 20130101;
H01L 27/088 20130101; H02M 3/1588 20130101; H01L 27/0629 20130101;
H01L 27/0922 20130101 |
Class at
Publication: |
307/112 ;
257/337; 257/E27.059 |
International
Class: |
H02B 1/24 20060101
H02B001/24; H01L 27/085 20060101 H01L027/085 |
Claims
1-12. (canceled)
13. A method of switching an electrical load, the method
comprising: providing a power-converter that includes an integrated
circuit having a high-side switch, a low-side switch and a
substrate, wherein the high-side switch is a Lateral
Double-Diffused Metal Oxide Semiconductor Field Effect Transistor
(LDMOS FET), and the conductivity-type of the LDMOS FET and the
conductivity of the substrate are of the same type.
14. A method as recited in claim 13, wherein the low-side switch is
a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS)
FET.
15. A method as recited in claim 13, wherein the low-side switch is
a vertical trench Double Diffused Metal Oxide Semiconductor (DMOS)
FET.
16. A method as recited in claim 13, wherein low-side switch is
another Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS)
FET.
17. A method as recited in claim 14, wherein the power converter
further comprises a plurality of conductive plugs, which provide an
ohmic connection of a few milli-Ohms to an output on a surface of a
substrate.
18. A method as recited in claim 15, wherein the power converter
further comprises a plurality of conductive plugs, which provide
an, ohmic connection of a few milli-Ohms to an output on a surface
of a substrate.
19. A method as recited in claim 16, wherein the power converter
further comprises a plurality of conductive plugs, which provide an
ohmic connection of a few milli-Ohms to an output on a surface of a
substrate.
20. A method as recited in claim 13, wherein the high side switch
is a Control FET (CF), and the lowside switch is a Synchronous
Rectifier FET (SF).
21. An integrated circuit comprising: a substrate having a first
conductivity type; a first transistor including a source region
that is disposed in a first well in the substrate, the first well
having a second conductivity type a second transistor including a
source region that is disposed in a second well in the substrate, a
drain region, and a body region that is disposed in the second
well, the second well having the first conductivity type, wherein
the source region of the first transistor is connected to the drain
region of the second transistor.
22. The integrated circuit of claim 21, further comprising a source
contact that connects the source region of the first transistor to
the drain region of the second transistor, and a conductive plug of
the first conductivity type in the substrate, wherein the
conductive plug is connected to the source contact and the
conductive plug separates the first well from the second well.
23. The integrated circuit of claim 22, wherein the first and
second transistors are both lateral double-diffused metal oxide
semiconductor type transistors.
24. The integrated circuit of claim 21, further comprising a source
contact and a conductive plug of the first conductivity type in the
substrate, wherein the drain region of the second transistor is
formed by a portion of the substrate, the source contact is
connected to the source region of the first transistor and to the
conductive plug, and the conductive plug is connected to the drain
region of the second transistor.
25. The integrated circuit of claim 24, wherein the conductive plug
separates the first well from the second well.
26. The integrated circuit of claim 21, wherein the second
transistor further includes a trench gate that is disposed in the
second well.
27. The integrated circuit of claim 21, wherein the first
transistor is a lateral double-diffused metal oxide semiconductor
type transistor.
28. The integrated circuit of claim 24, wherein the second
transistor is a vertical double-diffused metal oxide semiconductor
type transistor.
29. The integrated circuit of claim 21, further comprising one or
more field effect transistors that are configured to control gate
switching of the first and second transistors.
30. The integrated circuit of claim 21, wherein the first
transistor is a control transistor of a down convertor and the
second transistor is a synchronous rectifier of the down
convertor.
31. The integrated circuit of claim 21, further comprising an
inductor and a capacitor, wherein a source contact of the first
transistor and a drain contact of the second transistor are
connected to a first side of the inductor, and the capacitor is
connected to a second side of the transistor.
32. The integrated circuit of claim 21, wherein the first
transistor further includes a drain region and a body region that
are each disposed in the first well.
Description
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The present invention relates generally to integrated power
conversion circuits using a half bridge, and particularly, to
integrated power-transistors for a down-converter power supply
having improved switching characteristics.
SUMMARY OF THE INVENTION
[0002] Power-converters are often used in power supplies, power
amplifiers and motor drives. Down converters, including Buck
converters are often used to convert an input voltage to a lower
voltage for supplying power to a load, such as a microprocessor.
These microprocessors have applicability in personal computers (PC)
as well as other electronic devices. In PC applications, the input
voltage to the converter is on the order of 12 V, and the required
output is on the order of approximately 1.4 V, or a factor of about
ten in step-down. Moreover, the required output currents of these
converters are increasing to above 50 A, further adding to the
design considerations of these circuits, and their devices.
[0003] Down-converter circuits often include a control transistor
and a synchronous rectifier. These devices are often
metal-oxide-semiconductor (MOS) transistors, which are
silicon-based field effect transistors (FET). The use of a control
FET (CF) and a synchronous rectifier FET (SF) has certain
advantages. However, in known circuits these devices are discrete
elements or are disposed in modules. Such circuits have certain
drawbacks. For example, as the demand for faster switching
frequencies increases, parasitic effects in such devices can have a
deleterious impact on the ability of the CF and SF to meet these
demands.
[0004] The losses associated with the on-and-off switching of down
converters are beneficially minimized as much as possible. This has
certain benefits, such as improving the battery life within the PC
and reduction of the heat-dissipation. Conversion loss in MOSFET's
is determined partly by resistance and partly by the figure of
merit of the device, which is proportional to the on resistance,
R.sub.on, and the gate-to-drain charge, Q.sub.gd.
[0005] In accordance with an exemplary embodiment of the present
invention, a down converter comprises an integrated circuit having
a control FET (CF) and a synchronous rectifier FET (SF), wherein
the control FET is a lateral double-diffused (LDMOS) FET, and the
conductivity-type of the LDMOS FET and the conductivity-type of the
substrate are the same.
[0006] As will become clearer as the present description continues,
the on-resistance and the gate-to-drain charge are improved via
exemplary embodiments described herein. Other benefits of the
embodiments are reduced parasitics, an option for integration of
interface circuitry (for better control of the power-device
switching) and a reduced production cost.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The invention is best understood from the following detailed
description when read with the accompanying drawing figures. It is
emphasized that the various features are not necessarily drawn to
scale. In fact, the dimensions may be arbitrarily increased or
decreased for clarity of discussion.
[0008] FIG. 1 is a schematic diagram of a down converter in
accordance with an exemplary embodiment of the present
invention.
[0009] FIG. 2a is a cross-sectional view of the integrated CF and
SF used in a down converter in accordance with an exemplary
embodiment of the present invention.
[0010] FIG. 2b is a cross-sectional view showing a plurality of
conductive plugs inside the cells (source/drain fingers) of a
CF-switch of a down-converter in accordance with an exemplary
embodiment of the present invention.
[0011] FIG. 3 is a cross-sectional view of the integrated CF and SF
used in a down converter in accordance with an exemplary embodiment
of the present invention.
[0012] FIG. 4 is a cross-sectional view of the integrated CF and SF
used in a down converter in accordance with an exemplary embodiment
of the present invention.
[0013] FIG. 5 is a cross-sectional view of the integrated CF and SF
used in a down converter in accordance with an exemplary embodiment
of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0014] In the following detailed description, for purposes of
explanation and not limitation, exemplary embodiments disclosing
specific details are set forth in order to provide a thorough
understanding of the present invention. However, it will be
apparent to one having ordinary skill in the art having had the
benefit of the present disclosure, that the present invention may
be practiced in other embodiments that depart from the specific
details disclosed herein. Moreover, descriptions of well-known
devices, methods and materials may be omitted so as to not obscure
the description of the present invention.
[0015] FIG. 1 shows a down converter circuit 100 in accordance with
an exemplary embodiment of the present invention. The circuit 100
is illustratively a Buck-converter circuit with a CF 101 and an SF
102. The input voltage, which is illustratively on the order of
approximately 12V, is from a voltage source or power supply (not
shown), and is applied over input terminals 103 and 104. The output
terminals 105 and 106 are connected to an inductor 107, and ground,
respectively. The load is a large storage capacitor 108 and a
resistor 109. The resistor 109 represents one of a variety of
electronic devices connected to the down-converter 100. For
example, the resistor 109 may be a microprocessor. It is noted,
however, that the use of the down converter circuit 100 of the
exemplary embodiment is not limited to a microprocessor-based
applications. For example, the converter-circuit may be used in
switch-mode (audio) amplifiers. Still other applications of the
converter circuit 100 will become apparent to one skilled in the
art having had the benefit of the present disclosure.
[0016] Generally, the requirements on down converters such as
circuit 100 are to provide an increasingly lower output voltage at
the load, while providing an increasing current to the load. These
requirements are coupled with a requirement for very low-ohmic
switches. Furthermore, a reduction of the physical sizes and values
of the inductor 107 and of the capacitor 108 (typically on the
order of several mF) is desired in compact high-speed
down-converter applications (e.g., on the order of approximately
300 kHz to approximately 2 MHz, with transients on the order of
nano-seconds), and requires faster on/off switching-time of current
to the load. Notwithstanding the need for efficient and rapid
supply of the power to the load, the down converter circuit 100
usefully has reduced electronic parasitics.
[0017] As is known, in efficient high-speed power devices and
circuits, the greatest sources of parasitic effects are parasitic
resistance and inductance, which deteriorates the efficiency and
switching speed of a device. Therefore, it is useful to reduce all
parasitics (resistive and inductive) in the total switching path
(e.g., the transistor, the transmission lines, the packaging, etc.)
As will become clearer as the present description proceeds, these
parasitics are reduced via integrated circuits of exemplary
embodiments described herein.
[0018] The exemplary embodiments include integration of the CF 101
and the SF 102 in a semiconductor device structure (chip) that
reduces the undesirable electronic parasitics by various methods
and structures. Moreover, these embodiments foster the fabrication
of the CF 101 and SF 102 in an integrated package or directly on
the circuit board of the load (e.g., PC-board in a microprocessor
application) using a minimum number of processing steps, so the
overall cost of the device is comparatively reduced through a
reduction in processing complexity. Finally, in addition to
reducing the parasitic resistance and inductance through transistor
choice and design, the exemplary embodiments reduce the spacing
between the transistors to realize a reduction in the
parasitics.
[0019] FIG. 2a shows an integrated circuit (IC) 200 in accordance
with an exemplary embodiment of the present invention. It is noted
that the various materials and doping polarities are intended to be
illustrative of the exemplary embodiments. Clearly, other
materials, elements and doping polarities may be used to realize
the exemplary embodiments. Moreover, it is noted that known
materials and semiconductor processing techniques may be used to
realize the IC 200. As such, in the interest of brevity and clarity
of the description of the exemplary embodiments, these known
materials and techniques are generally omitted.
[0020] The IC 200 is illustratively a half-bridge circuit and
includes devices fabricated on a common n.sup.+ substrate 201,
which is illustratively n-doped silicon. A vertical double-diffused
MOS (VDMOS) transistor 202 includes a gate 219 having a gate
contact 205, a drain contact 223, an n.sup.+ source 216 and a
p-body 218 shorted to the source 216 via source contact 203. The
VDMOS is formed in an n-doped epitaxial (epi) well 206. The drain
of the VDMOS structure is comprised of a heavily doped (n.sup.+)
drain 204 and the n-epi well 206. Hereinafter the VDMOS drain will
be referred to as drain 204.
[0021] In the present exemplary embodiment, the VDMOS transistor
202 is configured to function as the SF rectifier 102 of the down
converter circuit 100 as will become clearer as the present
description continues. Beneficially, the VDMOS FET 202 is a
trench-gate structure, which generally provides a lower on-state
resistance (for example, on the order of 10 mOhm*mm.sup.2 for a
device with an operating voltage of approximately 25 V) compared to
other FET devices.
[0022] An LDMOS transistor 207 is formed in a buried p-well 221,
and includes a gate 211; an n.sup.+ source 214 shorted to a p-body
217; and an n-drain 215, which is formed in an n-type well 220. The
gate contacts 205 and 211 are each connected to a control section
(not shown) that drives the gates 219 and 211 for switching the
FET's 202 and 207 on and off. In the exemplary embodiment, the
LDMOS FET functions as the CF of the down-converter circuit
100.
[0023] The IC 200 may also include an NMOS FET 226 and a PMOS FET
227, which may be used in various applications of the IC. The FET's
may be used in conjunction with interface circuitry (not shown) for
better control of the switching, and a reduced inductance in the
gate-drive circuit. These and other devices may also be
incorporated on the IC in keeping with the exemplary
embodiments.
[0024] Illustratively, gate 219 is driven between ground and
approximately 5V to approximately 12 V. Gate 211 is driven between
the gate voltage and source voltage of the LDMOS FET 207. The
source contact 208 connects the source 214 to the output 208 and
the drain 204, which cycles between input-voltage (approximately
12V) and a flyback-voltage (typically about -0.2V). Hence, the gate
211 is driven by a control block supplied by an external capacitor,
which is illustratively charged by a bootstrap circuit and/or a
charge-pump circuit (not shown).
[0025] As mentioned above, it is useful to provide circuit 100
including the power transistors (FET'S) with a reduced parasitic
inductance and on-resistance compared to known devices.
Illustratively, by virtue of the IC 200, the parasitic inductance
of the circuit 100 including the half-bridge IC 200 of an exemplary
embodiment is on the order of approximately 1.0 nH, while the
on-resistance is on the order of approximately 5 mOhms to
approximately 10 mOhms. The reduced parasitic inductance results in
an improved switching speed (on/off time) for the load (e.g.,
capacitor 108 and resistor 109), while the reduced on-resistance
results in a reduction of the conductive losses of the IC.
[0026] The semiconductor device structure and design of the IC 200
realizes benefits in reduced parasitics in part because of the
reduced parasitics of the devices that comprise the IC 200. For
purposes of illustration, the VDMOS FET 202 provides a relatively
low on-state resistance, illustratively on the order 10
mOhm*mm.sup.2 for a 25V device and a reasonable Q.sub.gd. The LDMOS
FET 207 also provides a reasonable low on-resistance
(illustratively 25 mOhm*mm.sup.2 for a 25V device), and a low
Q.sub.gd.cndot.; the product (Ron*Qgd) is illustratively on the
order of approximately 12 mOhm*nC for LDMOS FET 207. Of course this
is merely illustrative, and other similar improved values may be
realized via the exemplary embodiments depending on the
application.
[0027] In the exemplary embodiment shown in FIG. 2a, the drain
contact 209 is connected to the voltage input of the down-converter
circuit 100 (e.g., 12V as mentioned above), while the source
contact 208 is connected to the drain contact 223 of the VDMOS FET,
which is also the drain of the SF 102 in the present exemplary
embodiment. The source contact 208 is illustratively connected via
a deep connection such as a conductive n+ plug 210 (or heavily
doped sinker) in the substrate 201. Alternatively, an n+ plug 210
may be disposed in an etched trench or dip; or a metal short (or
via) may be disposed in an etched trench to achieve this end. In
any event, this provides a low-Ohmic connection with a small
lateral dimension. The conductive plug 210 or similar device then
is applied on multiple locations inside a cell of LDMOS devices,
(e.g., as shown in FIG. 2b) thus connecting source-contact 208 with
low resistance to heavily doped drain 204, using contact 222 with a
relatively thin first metal only, which allows fine patterns inside
the cell. This is advantageous for allowing a thick (second)
power-metal for 203 and 209 on the top-side of the IC with coarse
patterns and a thick power-metal (drain contact 223) for the output
at the bottom-side (i.e., beneath the substrate).
[0028] As can be appreciated, the source contact 208 of the LDMOS
FET 202 and the drain contact 223 of the VDMOS FET 207 have now a
low-ohmic connection on the chip (IC) and are connected to an
inductor of a down converter, such as inductor 107 of FIG. 1.
Beneficially, this fosters a reduction in parasitics compared with
other structures. Finally, other connections are made in a
relatively straightforward manner, so the IC 200 is connected to
the other elements of the down converter circuit 100.
[0029] The IC 200 is fabricated illustratively as follows, using
well-known semiconductor processing techniques. An n+ silicon layer
forms the substrate 201, with n-epitaxy approximately 3-4 um in
thickness forming the n-well 206. This epi-layer is about 2-3 um in
thickness at end of processing. This step is followed first by a
P-well implantation and diffusion to form the p-well 221 and
p-wells 224 and 225 of the NMOS and PMOS FET's 226 and 227,
respectively. An N-well implantation is carried out to form the
n-wells 220 of the LDMOS drift-region and the PMOS FET n-well 228.
This is followed by a dopant diffusion. A deep n+ plug 210 may then
be implanted if desired, followed by a diffusion. Thereafter a
trench is etched for the VDMOS FET 202.
[0030] Alternatively, the deep N-type plug 210 could be fabricated
using the trench with additional n+ implant in its bottom for a
surface contact to the n+ wafer to form the drain contact 204. Next
an optional field-oxide step is carried out via local oxidation of
silicon (LOCOS). This field-oxide (not shown) also may be grown, or
deposited and etched. Thereafter, a gate-oxide formation (e.g., by
oxide growth) step is carried out to form the gate oxides of the
VDMOS FET 202 and LDMOS FET 207. These gate oxides have a thickness
of approximately 15 to approximately 40 nm, depending on the
required gate-source voltage (Vgs), which is illustratively
approximately 5V to approximately 12V.
[0031] Thereafter, a poly-silicon deposition and n+ doping is
carried out, which is followed by patterning of the poly. After the
poly-deposition sequence is complete, a shallow p-type DMOS
body-implantation is effected to form the body 218 (e.g., with
Latid-Boron, with Arsenic link). Next, a (oxide) spacer (not shown)
is formed by standard processing techniques. This processing
sequence results a short-channel and a good link to the source,
which fosters a low-R.sub.on for the LDMOS FET 207. Next, a shallow
n+ region, and a shallow p+ region are implanted and activated,
followed by field-oxide (FOX) deposition, contact-windows (not
shown), first metal, oxide or nitride-deposition, vias (not shown),
thick second metal (not shown) with a seed-layer and galvanic
copper 10-15 um, covered by protection and opened to bond-pads (not
shown).
[0032] In operation, if the LDMOS FET 207 (CF) is on, it charges
the n+ substrate to the input voltage (e.g., 12V), thereby
providing a current in the load-inductance 107. If CF is closed,
the load-inductance 107 pulls the n+ substrate from 12V towards
approximately -0.1V or to approximately -0.7V, depending on the
turn-on timing of the VDMOS FET 202. The current in a
down-converter normally flows through the load-inductance 107 from
the source 214 and to the load. Hence, the potential on n+
substrate will not be above +12V; the potential on 209 may rise
above this value, depending on the inductance. Finally, it is noted
that in embodiments described herein, the inductance may be reduced
further using surface solder-bumps and flip-chip packaging.
[0033] FIG. 3 shows an IC 300 in accordance with another exemplary
embodiment of the present invention. This IC 300 shares common
features and materials with the IC 200 previously described. As
such, differences will be highlighted, and commonalties not
discussed. The IC 300 illustratively includes an n-type substrate
301 with two LDMOS FET's 302 and 303, respectively. The LDMOS FET
302 is usefully the SF 102 of FIG. 1, while the LDMOS FET 303 is
the CF 101. The LDMOS FET 303 is substantially identical to that
described in FIG. 2a. One difference lies in its source connection,
which is via metallization connected to the drain contact 304 of
the LDMOS FET 302. This corresponds, of course, to the output 105
of FIG. 1.
[0034] The LDMOS FET 302, which functions as the SF 102, has a
source 306 and body 307 connected to ground via a source contact
308. The gate 309 is connected to a control function (not shown)
much like the control function of the gate 211 described above. The
drain 215 is placed in an n-well 220 and connected to output 304
via 305. The device is placed in an n-epi well 206. Advantageously,
the IC 300 has a low on resistance, with each LDMOS transistor
having an on-resistance (R.sub.on) per unit area on the order of
approximately 10 m.OMEGA.*mm.sup.2 for a 20V. Moreover, all power
connections to the IC are now on a common side of the chip,
eliminating the need for the formation of backside contacts or the
deep conductive plug(s) or similar device. This illustrative
embodiment is also beneficial because the substrate does not need
to be thinned during processing to reduce parasitic resistance, or
to have a very low resistivity via super-doping. This embodiment
however puts higher demands to the metallization of both
LDMOS-devices, and may require an additional (third) metal-layer
and via-pattern.
[0035] FIG. 4 shows another exemplary embodiment of the present
invention. This embodiment shares common features and structures
with that of FIGS. 2a, 2b and 3, and may be used in a circuit such
as is shown in FIG. 1. The IC 400 of FIG. 4 is essentially IC 300
with n+ plugs 401 (diffused, pre-etched or trench) and the n+
substrate 201 with output 105 of the circuit of FIG. 1 at the
bottom-side via metallization 223. Plugs 401 are useful to relieve
the demand on the metallization of both LDMOS FETs and allow for a
two-layer metal-system, which is advantageous during
fabrication.
[0036] FIG. 5 is another exemplary embodiment of the present
invention. Again, the IC 500 shares common features and structures
with the exemplary embodiments of FIGS. 2-4. To with, IC 500 is
essentially IC 400 except a from p-epitaxial layer 501 is disposed
on the n+ substrate 201; or may be an n-epi layer on the n+
substrate 202 with a blanket P-well implantation and diffusion.
Here device 309 is placed in a p-well 501. The plugs 401 also act
for well-isolation in this embodiment. This saves at least one
mask-step.
[0037] The invention being thus described, it would be obvious that
the same may be varied in many ways by one of ordinary skill in the
art having had the benefit of the present disclosure. Such
variations are not regarded as a departure from the spirit and
scope of the invention, and such modifications as would be obvious
to one skilled in the art are intended to be included within the
scope of the following claims and their legal equivalents.
* * * * *