U.S. patent application number 11/845560 was filed with the patent office on 2009-03-05 for thermally enhanced thin semiconductor package.
Invention is credited to Ruben P. Madrid.
Application Number | 20090057852 11/845560 |
Document ID | / |
Family ID | 40387695 |
Filed Date | 2009-03-05 |
United States Patent
Application |
20090057852 |
Kind Code |
A1 |
Madrid; Ruben P. |
March 5, 2009 |
THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE
Abstract
A semiconductor die package is disclosed. The semiconductor die
package includes a semiconductor die comprising an input at a first
top semiconductor die surface and an output at a second bottom
semiconductor die surface. A leadframe having a first leadframe
surface and a second leadframe surface opposite the first leadframe
surface is in the semiconductor die package and is coupled to the
first top semiconductor die surface. A clip having a first clip
surface and a second clip surface is coupled to the second bottom
semiconductor die surface. A molding material having exterior
molding material surfaces covers at least a portion of the
leadframe, the clip, and the semiconductor die. The first leadframe
surface and the first clip surface are exposed by the molding
material, and the first leadframe surface, the first clip surface,
and the exterior molding material surfaces of the molding material
form exterior surfaces of the semiconductor die package.
Inventors: |
Madrid; Ruben P.; (Cebu,
PH) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER, EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Family ID: |
40387695 |
Appl. No.: |
11/845560 |
Filed: |
August 27, 2007 |
Current U.S.
Class: |
257/670 ;
257/E21.502; 257/E23.04; 438/123 |
Current CPC
Class: |
H01L 2224/0603 20130101;
H01L 2224/73253 20130101; H01L 2924/01078 20130101; H01L 2224/16245
20130101; H01L 2924/0665 20130101; H01L 2924/01013 20130101; H01L
24/81 20130101; H01L 2224/3754 20130101; H01L 2924/01005 20130101;
H01L 2924/01082 20130101; H01L 2924/10253 20130101; H01L 2924/01019
20130101; H01L 2924/18301 20130101; H01L 2924/01079 20130101; H01L
2224/13111 20130101; H01L 2224/371 20130101; H01L 23/49524
20130101; H01L 24/83 20130101; H01L 2224/81193 20130101; H01L
2224/37124 20130101; H01L 2224/84801 20130101; H01L 24/33 20130101;
H01L 24/40 20130101; H01L 2224/37147 20130101; H01L 2224/8121
20130101; H01L 2224/81815 20130101; H01L 2224/1134 20130101; H01L
2224/32245 20130101; H01L 23/49562 20130101; H01L 2224/13147
20130101; H01L 24/37 20130101; H01L 2224/2919 20130101; H01L
2924/1305 20130101; H01L 2924/13091 20130101; H01L 2924/1306
20130101; H01L 2924/181 20130101; H01L 2924/01029 20130101; H01L
23/4334 20130101; H01L 2223/54433 20130101; H01L 2924/01033
20130101; H01L 24/84 20130101; H01L 2224/83801 20130101; H01L
2924/01006 20130101; H01L 2223/54473 20130101; H01L 2924/01047
20130101; H01L 2924/014 20130101; H01L 23/544 20130101; H01L
2224/2919 20130101; H01L 2924/0665 20130101; H01L 2924/00 20130101;
H01L 2924/0665 20130101; H01L 2924/00 20130101; H01L 2924/10253
20130101; H01L 2924/00 20130101; H01L 2924/1306 20130101; H01L
2924/00 20130101; H01L 2924/1305 20130101; H01L 2924/00 20130101;
H01L 2924/181 20130101; H01L 2924/00012 20130101; H01L 2224/84801
20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/670 ;
438/123; 257/E21.502; 257/E23.04 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 21/56 20060101 H01L021/56 |
Claims
1. A semiconductor die package comprising: a semiconductor die
comprising an input at a first top semiconductor die surface and an
output at a second bottom semiconductor die surface; a leadframe
having a first leadframe surface and a second leadframe surface
opposite the first leadframe surface, wherein the second leadframe
surface is coupled to the first top semiconductor die surface; a
clip having a first clip surface and a second clip surface, wherein
the second clip surface is coupled to the second bottom
semiconductor die surface; and a molding material having exterior
molding material surfaces and covering at least a portion of the
leadframe, the clip, and the semiconductor die, wherein the first
leadframe surface and the first clip surface are exposed by the
molding material, and wherein the first leadframe surface, the
first clip surface, and the exterior molding material surfaces of
the molding material form exterior surfaces of the semiconductor
die package.
2. The semiconductor die package of claim 1 wherein the
semiconductor die comprises a vertical device.
3. The semiconductor die package of claim 1 wherein the first
leadframe surface defines a protruding leadframe portion of the
leadframe.
4. The semiconductor die package of claim 3 wherein the first clip
surface defines a protruding clip portion of the clip.
5. The semiconductor die package of claim 3 wherein exterior
surfaces of the molding material are substantially coplanar with
the first clip surface and the first leadframe surface, and wherein
the molding material covers edges of the protruding leadframe
portion and the protruding clip portion.
6. The semiconductor die package of claim 1 wherein the
semiconductor die is coupled to the leadframe using solder.
7. The semiconductor die package of claim 1 wherein the solder
comprises a high temperature solder material and a low temperature
solder material.
8. The semiconductor die package of claim 1 wherein the
semiconductor die comprises a trenched gate.
9. The semiconductor die package of claim 1 wherein the leadframe
comprises copper or a copper alloy.
10. A system comprising the semiconductor die package of claim
1.
11. A method for forming a semiconductor die package, the method
comprising: obtaining a semiconductor die comprising an input at a
first top semiconductor die surface and an output at a second
bottom semiconductor die surface; attaching a leadframe having a
first leadframe surface and a second leadframe surface opposite the
first leadframe surface to the semiconductor die, wherein the
second leadframe surface is coupled to the first top semiconductor
die surface; attaching a clip having a first clip surface and a
second clip surface, wherein the second clip surface is coupled to
the second bottom semiconductor die surface; and molding a molding
material around at least a portion of the leadframe, the clip, and
the semiconductor die, wherein after molding, the first leadframe
surface and the first clip surface are exposed by the molding
material, and wherein the first leadframe surface, the first clip
surface, and the exterior molding material surfaces of the molding
material form exterior surfaces of the semiconductor die
package.
12. The method of claim 11 wherein attaching the leadframe to the
semiconductor die comprises using solder to attach the leadframe to
the semiconductor die.
13. The method of claim 11 wherein attaching the clip to the
semiconductor die comprises using solder to attach the clip to the
semiconductor die.
14. The method of claim 11 further comprising, prior to attaching
the leadframe to the semiconductor die, partially etching the
leadframe to form a protruding portion comprising the first
leadframe surface.
15. The method of claim 14 further comprising, prior to attaching
the clip to the semiconductor die, partially etching the clip to
form a protruding portion comprising the first clip surface.
16. The method of claim 14 wherein molding comprises using a
molding tool with molding dies that contact surfaces of the clip
and the leadframe.
17. The method of claim 14 wherein the semiconductor die comprises
a vertical MOSFET.
18. The method of claim 14 wherein the leadframe comprises
copper.
19. The method of claim 14 wherein attaching the leadframe to the
semiconductor die occurs after attaching the clip to the
semiconductor die.
20. The method of claim 14 wherein the semiconductor die package is
in an array of semiconductor die packages when the semiconductor
die package is formed.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] Not Applicable
BACKGROUND
[0002] Semiconductor die packages are known in the semiconductor
industry, but could be improved. For example, electronic devices
such as wireless phones and the like are becoming smaller and
smaller. It is desirable to make thinner semiconductor die packages
so that they can be incorporated into such electronic devices. It
would also be desirable to improve upon the heat dissipation
properties of conventional semiconductor die packages.
[0003] Another technical challenge that exists is in the formation
of such semiconductor die packages. A clip and a leadframe may
sandwich a semiconductor die in an exemplary semiconductor die
package. If the clip and the leadframe are not properly aligned
with each other and the semiconductor die, then the manufactured
semiconductor die package could be defective and rework may be
needed.
[0004] Embodiments of the invention address these and other
problems, individually and collectively.
BRIEF SUMMARY
[0005] Embodiments of the invention are directed to semiconductor
die packages, methods for making semiconductor die packages, and
assemblies and systems using such semiconductor die packages.
[0006] One embodiment of the invention is directed to a
semiconductor die package. The semiconductor die package includes a
semiconductor die comprising an input at a first top semiconductor
die surface and an output at a second bottom semiconductor die
surface. A leadframe having a first leadframe surface and a second
leadframe surface opposite the first leadframe surface is in the
semiconductor die package and is coupled to the first top
semiconductor die surface. A clip having a first clip surface and a
second clip surface is coupled to the second bottom semiconductor
die surface. A molding material having exterior molding material
surfaces covers at least a portion of the leadframe, the clip, and
the semiconductor die. The first leadframe surface and the first
clip surface are exposed by the molding material, and the first
leadframe surface, the first clip surface, and the exterior molding
material surfaces of the molding material form exterior surfaces of
the semiconductor die package.
[0007] Another embodiment of the invention is directed to a method
for forming a semiconductor die package. The method comprises
obtaining a semiconductor die comprising an input at a first top
semiconductor die surface and an output at a second bottom
semiconductor die surface, and attaching a leadframe having a first
leadframe surface and a second leadframe surface opposite the first
leadframe surface to the semiconductor die. The second leadframe
surface is coupled to the first top semiconductor die surface. A
clip is attached to the second bottom semiconductor die surface.
The clip has a first clip surface and a second clip surface. A
molding material is molded around at least a portion of the
leadframe, the clip, and the semiconductor die. After molding, the
first leadframe surface and the first clip surface are exposed by
the molding material. The first leadframe surface, the first clip
surface, and the exterior molding material surfaces of the molding
material form exterior surfaces of the semiconductor die
package.
[0008] These and other embodiments of the invention are described
in further detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 shows a top perspective view of a semiconductor die
package according to an embodiment of the invention.
[0010] FIG. 2 shows a bottom perspective view of the semiconductor
die package shown in FIG. 1.
[0011] FIG. 3 shows a top perspective view of a semiconductor die
package according to an embodiment of the invention with the
outline of the molding material shown.
[0012] FIG. 4 shows a bottom perspective view of a semiconductor
die package according to an embodiment of the invention with the
outline of the molding material shown.
[0013] FIG. 5 shows a top perspective view of a semiconductor die
package according to an embodiment of the invention with a portion
of the molding material being removed.
[0014] FIG. 6 shows a bottom perspective view of a semiconductor
die package according to an embodiment of the invention with a
portion of the molding material being removed.
[0015] FIG. 7 shows a side cross-sectional view of a semiconductor
die package according to an embodiment of the invention.
[0016] FIG. 8 shows a front cross-sectional view of a semiconductor
die package according to an embodiment of the invention.
[0017] FIG. 9 shows an exploded view of a semiconductor die package
according to an embodiment of the invention.
[0018] FIG. 10 shows a top view of a semiconductor die package
according to an embodiment of the invention.
[0019] FIG. 11 shows a top perspective view of a leadframe
structure attached to a frame.
[0020] FIG. 12 shows a bottom perspective view of a thermal drain
clip.
[0021] FIG. 13 shows a bottom perspective view of an internal frame
die attach pad area.
[0022] FIG. 14 shows a bottom perspective view of an assembled
frame with an attached thermal drain clip.
[0023] FIG. 15 is a top perspective view of an assembled frame with
an attached thermal drain clip.
[0024] FIG. 16 is a top perspective view of an assembled frame with
an attached thermal drain clip, after molding.
[0025] FIG. 17 is a bottom perspective view of an assembled frame
with an attached thermal drain clip, after molding.
[0026] FIG. 18 is a side, cross-sectional view of an embodiment of
the invention after assembly and molding.
[0027] FIGS. 19(a) and 19(c) show die bonding and layouts.
[0028] FIGS. 20(a)-20(k) show portions of a semiconductor die
package as it is being formed.
[0029] FIG. 21 shows a semiconductor die comprising a vertical
MOSFET with a trenched gate.
[0030] In the Figures, like numerals designate like elements, and
the descriptions of like elements may not be repeated in some
instances.
DETAILED DESCRIPTION
[0031] One embodiment of the invention is directed to a
semiconductor die package. The semiconductor die package includes a
semiconductor die comprising an input (e.g., a source region) at a
first top semiconductor die surface and an output (e.g., a drain
region) at a second bottom semiconductor die surface. A leadframe
having a first leadframe surface and a second leadframe surface
opposite the first leadframe surface is in the semiconductor die
package and is coupled to the first top semiconductor die surface.
A clip (e.g., a drain clip) having a first clip surface and a
second clip surface is coupled to the second bottom semiconductor
die surface. A molding material having exterior molding material
surfaces covers at least a portion of the leadframe, the clip, and
the semiconductor die. The first leadframe surface and the first
clip surface are exposed by the molding material, and the first
leadframe surface, the first clip surface, and the exterior molding
material surfaces of the molding material may form exterior
surfaces of the semiconductor die package.
[0032] FIG. 1 shows a top perspective view of a semiconductor die
package 10 according to an embodiment of the invention. The
semiconductor die package 10 comprises a leadframe 214 comprising a
source lead structure 214(a) and a gate lead structure 214(b). The
source lead structure 214(a) comprises a source pad 14, an exposed
source surface 14(a) (which may be an example of at least part of a
first leadframe surface), and source leads 12. The leadframe 214
may also comprise a gate lead structure comprising a gate lead 11.
An exposed thermal clip 15 is also shown, and will be described in
further detail below with respect to FIG. 2. A molding material 13
may be formed on at least a portion of the leadframe 214, the clip
215, and a semiconductor die (not shown) that lies between the
leadframe 214 and the clip 15. The molding material 13 may be
formed using any suitable material including an epoxy based molding
material. If desired, a heatsink (not shown) could be placed on top
of the surface 14(a) to improve heat dissipation properties.
[0033] As shown in FIG. 1, a top exterior surface of the molding
material 13 of the semiconductor die package 10 is substantially
coplanar with and exposes the exposed source pad surface 14(a).
Extensions to the source leads 12 (as well as the gate lead 11) are
also exposed by the molding material 13 in this example. Thus, the
topmost surface of the package may be formed at least in part by
the exposed source surface 14(a) and the top exterior surface of
the molding material 13. This particular configuration results in a
very thin semiconductor die package, with good heat dissipation
properties. Heat can dissipate through the gate lead 11, the source
lead 12, and the exposed thermal clip 15.
[0034] FIG. 2 shows a bottom view of the semiconductor die package
10 shown in FIG. 1. As shown, a bottom clip surface 15(a) (which
may be an example of a first clip surface) of the thermal clip 15
may be exposed by the molding material 13. The bottom clip surface
15(a) may be substantially coplanar with the bottom surface of the
molding material 13. The ends of the leads 11, 12 may also be
substantially coplanar with the bottom clip surface 15(a) so that
the semiconductor die package 10 can be mounted to a printed
circuit board or the like.
[0035] In the embodiment shown in FIG. 2, the leads 11, 12 may
extend out of the molding material 13 from one end of the
semiconductor die package 10, while a portion of the clip 15 may
extend out of the molding material 13 from the opposite end of the
semiconductor die package 10. Thus, the package 10 shown in FIG. 2
is a leaded package. In other embodiments of the invention,
however, "leadless" packages could be produced. A leadless package
may still include leads, but they may not extend past the lateral
surfaces of the molding material 13 at all or to any appreciable
degree.
[0036] FIG. 3 is a top perspective view of the semiconductor die
package shown in FIG. 1 with the outline of the molding material
being shown by dotted lines. FIG. 4 shows a bottom perspective view
of the semiconductor die package shown in FIG. 1 with the outline
of the molding material being shown by dotted lines. FIGS. 3 and 4
more clearly show a leadframe comprising a gate lead structure 11
and a source lead structure 12. The gate lead structure 11 and the
source lead structure 12 are electrically isolated from each
other.
[0037] A semiconductor (e.g., silicon) die 32 is sandwiched between
the leadframe and a thermal drain clip 15. The thermal clip 15 and
the leadframe may be electrically coupled to an output region in
the semiconductor die 32 in the semiconductor die package 10.
[0038] The leadframe 214 and the thermal drain clip 15 may be
formed of any suitable electrically conductive material including
copper, aluminum, noble metals and alloys thereof. The leadframe
and the thermal drain clip 15 may also be plated with solderable
layers (e.g., underbump metallurgy layers).
[0039] The semiconductor dies used in the semiconductor packages
according to preferred embodiments of the invention include
vertical power transistors. Vertical power transistors include
VDMOS transistors. A VDMOS transistor is a MOSFET that has two or
more semiconductor regions formed by diffusion. It has a source
region, a drain region, and a gate. The device is vertical in that
the source region and the drain region are at opposite surfaces of
the semiconductor die. The gate may be a trenched gate structure or
a planar gate structure, and is formed at the same surface as the
source region. Trenched gate structures are preferred, since
trenched gate structures are narrower and occupy less space than
planar gate structures. During operation, the current flow from the
source region to the drain region in a VDMOS device is
substantially perpendicular to the die surfaces. An example of a
semiconductor die 800 comprising a vertical MOSFET with a trenched
gate is shown in FIG. 21. Other devices that may be present in a
semiconductor die may include diodes, BJT (bipolar junction
transistors) and other types of electrical devices.
[0040] Referring again to FIG. 3, part of the leadframe 214 may be
etched to allow the molding material 13 to lock to the leadframe.
As shown in FIG. 3, the gate lead structure 11 has a gate pad 31
and a partially etched region 31(a) for locking. The source lead
structure 214(a) has an exposed source pad 14 with an exposed
source pad surface 14(a). The source pad surface 14(a) is also
defined by a partially etched region 34 for mold locking. The
source pad surface 14(a) may be part of a protruding region that
protrudes from the other portions of the source pad 14.
[0041] As shown in FIG. 4, the drain clip 15 may also be partially
etched, and may have a partially etched region 311 to allow the
molding material 13 to lock to the drain clip 15. The drain pad
surface 15(a) may be part of a protruding region that protrudes
from the other portion of the source pad.
[0042] Any suitable etching process may be used to etch the
leadframe and/or the clip 15, and etching may occur to any suitable
depth. Suitable etching processes may include wet or dry etching
processes. In some embodiments, the leadframe may be etched about
one half way through the thickness of the leadframe. The etched
leadframe maybe characterized as being half-etched under such
circumstances.
[0043] FIG. 5 shows a top perspective view of the semiconductor die
package 10 with a portion of the molding material 13 being removed.
As shown, the molding material 13 may cover ledges forming the
partially etched regions 31(a), 34 of the leadframe 214, without
covering the source pad surface 14(a). The top exterior surface of
the molding material 13 may be substantially coplanar with the
source pad surface 14(a). As shown in FIG. 1, the molding material
13 may cover the top surface 31(b) of the gate pad 31. The top
surface 31(b) of the gate pad 31 may be exposed, however, in other
embodiments of the invention.
[0044] FIG. 6 shows a bottom perspective view of the semiconductor
die package with a portion of the molding material 13 being
removed. FIG. 6 more clearly shows the partially etched region 311
of the clip 15. The molding material 13 may cover the surfaces of
the partially etched region 311, but does not cover the drain
surface 15(a). The drain surface 15(a) can be substantially
coplanar with the bottom exterior surface of the molding material
13. As shown, the clip 15 may also have lateral grooves 127 improve
the locking of the molding material 13 to the clip 15.
[0045] FIG. 7 is a cross-sectional view of the semiconductor die
package. FIG. 7 more clearly shows solder bumps 76 coupling a first
surface 32(a) of the semiconductor die 32 to the source pad 14.
Solder paste 99 may contact the solder bumps 76 and the source pad
14. The semiconductor die 32 may also comprise a second surface
32(b) that is coupled to the drain clip 15. Solder can also be used
to couple a second surface 15(b) of the drain clip 15 to the second
surface 32(b) of the semiconductor die 32. The molding material 13
does not cover the top first surface 14(a) of the source pad 14 and
the bottom surface of the clip 15, and further fills in the
partially etched region 311 to allow the molding material 13 to
lock to the drain clip 15. As shown in FIG. 7, the bottom surface
15(a) of the clip 15 is also substantially coplanar with the bottom
surface of the molding material 13. In this example, source leads
12 extend from one side of the semiconductor die package, while the
drain clip 15 extends from the opposite side of the semiconductor
die package.
[0046] The solder bumps 76 and the solder paste 99 may have
different melting temperatures in some embodiments of the
invention, and any suitable solder material may be used including
Pb based solder and lead free solder materials. Other types of
conductive adhesives such as conductive epoxies may also be used to
electrical and mechanically couple parts in the package 10
together.
[0047] FIG. 8 shows a front cross-sectional view of the
semiconductor die package 10 in FIG. 7. FIG. 8 additionally shows a
partially etched region 34 of the source pad 14, and the molding
material 13 filling in the partially etched region 34 to provide
for molding locking.
[0048] FIG. 9 shows an exploded view of the previously described
leadframe 214, molding material 13, semiconductor die 32, and the
clip 15.
[0049] FIG. 10 shows a top view of the semiconductor die package
10.
[0050] A method for forming the above described semiconductor die
package can now be described. In one embodiment, the method may
comprise obtaining a semiconductor die comprising an input at a
first top semiconductor die surface and an output at a second
bottom semiconductor die surface, and attaching a leadframe having
a first leadframe surface and a second leadframe surface opposite
the first leadframe surface to the semiconductor die. The second
leadframe surface is coupled to the first top semiconductor die
surface. A clip having a first clip surface and a second clip
surface is attached to the semiconductor die before or after the
semiconductor die is attached to the second leadframe surface. In
any event, the second clip surface is coupled to the second bottom
semiconductor die surface, and a molding material is molded around
at least a portion of the leadframe, the clip, and the
semiconductor die, wherein after molding, the first leadframe
surface and the first clip surface are exposed by the molding
material, and wherein the first leadframe surface, the first clip
surface, and the exterior molding material surfaces of the molding
material form exterior surfaces of the semiconductor die
package.
[0051] A leadframe can be obtained from any suitable precursor
structure, which may be formed by any suitable process including
stamping, etching, or any suitable combination of such processes.
FIG. 11 shows a top perspective view of a leadframe precursor
structure 111 according to an embodiment of the invention. It
includes a lifted anvil 113 at a first end of the leadframe
precursor structure 111 attached to a frame 112. The frame 112 may
define a frame window 1111 for molding. The upper surface of the
anvil 113 may lie in a different plane and may be downset with
respect to the upper surface of the frame 112. A horizontal slot
1112 is parallel to the orientation of the anvil 113 and two
vertical locator slots 1113 on opposite ends of the horizontal slot
1112. The vertical slots 1113 will be used for thermal drain clip
hook positioning.
[0052] The leadframe precursor structure 1111 also includes a
source lead structure including a source pad 14 and integral source
leads 12, and a gate lead structure including a gate pad 31 and an
integral gate lead 11, attached to the frame 112 via tie bars 118
at a second end opposite the first end. As in prior FIGS.,
partially etched regions 34 and 31(a) are shown in the source pad
14 and the gate pad 31, respectively.
[0053] FIG. 12 shows a perspective view of the drain clip 15. It
includes a drain clip surface 15(a), and slotted regions 127 for
mold locking, as well as a relief slot 126 for cutting in a
singulation process. It also includes a thermal clip locator hook
125 extending from a thermal clip pad 124. The drain clip 15 can be
formed by any suitable process including etching and stamping.
[0054] FIG. 13 shows the leadframe precursor structure 111 in FIG.
11, flipped over. FIG. 13 shows a support area 1216 for the clip 15
on the anvil 113. Solder paste 1215 is on the support area 1216.
Solder paste 99 is also deposited on the internal surfaces of the
gate pad and the source pad. A flat frame surface 1213 is also
present in the leadframe precursor structure 111.
[0055] FIG. 14 shows a perspective bottom view of an assembled
frame with an attached thermal drain clip. FIG. 15 shows a top
perspective view of the assembled frame with an attached drain
clip. FIG. 15 also shows a thermal die attach clip pad 159. FIG. 18
shows a cross-sectional view of the assembly shown in FIGS. 16-17.
FIG. 18 additionally shows a conductive adhesive (e.g., solder) 186
coupling the die 32 to the drain clip 15, and a setting point 1710
between the clip 15 and the anvil 113.
[0056] As shown in FIG. 14, the clip 15 can be placed on the source
and gate pads so that the hook 125 fits into the horizontal slot
1112. Opposite edges defining the vertical slots 1113 restrict the
lateral movement of the hook 125, thereby stabilizing the lateral
and vertical positioning of the clip 15, relative to the source and
gate pads 14, 31 (See FIG. 15). As shown in prior Figures, a
semiconductor die 32 is sandwiched between the source and gate pads
14, 31, and the drain clip 15. The semiconductor die 32 may have
been bumped with solder using conventional solder deposition
processes.
[0057] As shown in FIGS. 16 and 17, after attaching a semiconductor
die 32 to the precursor 111 and the clip 15, a molding material 113
can be formed so that it covers at least a portion of the
semiconductor die 32, the frame 214 in the precursor 111, and the
clip 15. As shown in FIG. 16, the top surfaces of the source pad
14, gate lead 11, and source leads 12, are exposed by the molding
material 13, and may be substantially coplanar with the top
exterior surface of the molding material 13. As shown in FIG. 17,
the bottom surface of the drain clip 15 is substantially coplanar
with the bottom surface of the molding material 13. The molding
material 13 lies within a frame window 179 formed by the leadframe
precursor 111.
[0058] Molding may occur using any suitable molding tool or molding
process. In an exemplary embodiment, the molding tool may have two
molding dies, where surfaces of the molding dies contact surfaces
of the leadframe and the clip so that they are not covered with
molding material during the molding process. Any suitable molding
temperatures and pressures may be used in embodiments of the
invention.
[0059] After molding, referring to FIGS. 16-17, the leads 11, 12 as
well as the portion of clip 15 with the slot 124 may be cut with a
saw or the like. The leads 11, 12, may then be bent (if they are
not already bent) to form the semiconductor die package.
[0060] Although one semiconductor die package is shown, the
semiconductor die package may be formed in an array.
[0061] FIGS. 19(a)-19(b) show top plan views of assemblies like
those shown in FIGS. 16-18, which two different die sizes. FIG.
19(a) shows a die size of 2.66 mm.times.3.66 mm. FIG. 19(b) shows a
die size of 4 mm.times.4 mm. Accordingly, as shown in FIGS.
19(a)-19(b), embodiments of the invention may incorporate any
suitable die size, or type of die.
[0062] FIGS. 20(a)-20(k) show portions of a semiconductor die
package as it is being formed. Many of the steps in FIGS.
20(a)-20(k) have been described above, and the descriptions are
applicable here.
[0063] FIGS. 20(a)-20(k) show the following: FIG. 20(a) shows a
thermal drain clip 15; FIG. 20(b) shows a die 32 being attached to
the thermal drain clip 15 using a soft solder and die attach
process (using reflow); FIGS. 20(c)-20(d) show a structure formed
after singulation and subsequent placement (by flipping) of the
clip 15 and die 32 combination onto a leadframe precursor 111; FIG.
20(e) shows a structure formed after a reflow process is performed,
wherein the die 32, the clip 15, and the precursor 111 are joined
together; FIG. 20(f) shows a structure formed after a film assisted
molding process is performed, whereby a molding material 13 is
formed around selected parts of the package; FIG. 20(g) shows a
structure formed after a water jet deflash process is performed;
FIG. 20(h) shows a structure formed after a laser marking process
is performed, whereby the die package can be laser marked for
identification purposes; FIG. 20(i) shows a structure formed after
a singulation process is performed, whereby the package can be
separated from other packages in an array; FIG. 20(j) shows a
structure formed after a unit test step is performed; and FIG.
20(k) shows a structure formed just prior to a pack and ship
step.
[0064] Embodiments of the invention have a number of advantages.
Embodiments of the invention may have some, none or all of the
following advantages. First, by exposing portions of the leadframe
and clip through the molding material, the packages are quite thin
and can be used in thin devices such as wireless phones, PDAs, etc.
Second, since larger surfaces of the clip and the leadframe are
exposed, heat can easily dissipate from a semiconductor die within
a semiconductor die package according to an embodiment of the
invention. Third, bigger die sizes can be mounted using the same
standard footprint. Fourth, as noted above, a clip can be properly
aligned with a die and a leadframe using a hook, thereby reducing
potential alignment errors during manufacturing. Fifth, no deflash
process and plating processes are needed if a pre-plated frame is
used. Sixth, embodiments of the invention are flexible and can use
both copper stud bumping and electroless NiAu bumps as well. Such
bumps may be present on the previously described dies. Seventh,
embodiments of the invention are robust and can be used in
applications such as automotive applications. Eighth, there is no
need to use a film assisted mold process since both sides of the
package can be in metal-to-metal contact with the surfaces of a
mold cavity.
[0065] As used herein "top" and "bottom" surfaces are used in the
context of relativity with respect to a circuit board upon which
the semiconductor die packages according to embodiments of the
invention are mounted. Such positional terms may or may not refer
to absolute positions of such packages.
[0066] The semiconductor die packages described above can be used
in electrical assemblies including circuit boards with the packages
mounted thereon. They may also be used in systems such as phones,
computers, etc.
[0067] Any recitation of "a", "an", and "the" is intended to mean
one or more unless specifically indicated to the contrary.
[0068] The terms and expressions which have been employed herein
are used as terms of description and not of limitation, and there
is no intention in the use of such terms and expressions of
excluding equivalents of the features shown and described, it being
recognized that various modifications are possible within the scope
of the invention claimed.
[0069] Moreover, one or more features of one or more embodiments of
the invention may be combined with one or more features of other
embodiments of the invention without departing from the scope of
the invention.
[0070] All patents, patent applications, publications, and
descriptions mentioned above are herein incorporated by reference
in their entirety for all purposes. None is admitted to be prior
art.
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