U.S. patent application number 12/247193 was filed with the patent office on 2009-02-05 for wafer-level assembly of heat spreaders for dual ihs packages.
This patent application is currently assigned to Intel Corporation. Invention is credited to Rajashree Baskaran, Chuan Hu, Daoqiang Lu.
Application Number | 20090034206 12/247193 |
Document ID | / |
Family ID | 38877178 |
Filed Date | 2009-02-05 |
United States Patent
Application |
20090034206 |
Kind Code |
A1 |
Lu; Daoqiang ; et
al. |
February 5, 2009 |
WAFER-LEVEL ASSEMBLY OF HEAT SPREADERS FOR DUAL IHS PACKAGES
Abstract
An embodiment of the present invention is a technique to
fabricate a package. A heat spreader (HS) array on a HS support
substrate is formed. The HS array has a plurality of heat
spreaders. A diced wafer supported by a wafer support substrate
(WSS) is formed. The diced wafer has a plurality of thin dice. The
thin dice in the diced wafer are bonded to the heat spreaders in
the HS array to form HS-bonded thin dice between the HS support
substrate and the WSS.
Inventors: |
Lu; Daoqiang; (Chandler,
CA) ; Baskaran; Rajashree; (Phoeniz, AZ) ; Hu;
Chuan; (Chandler, AZ) |
Correspondence
Address: |
INTEL/BSTZ;BLAKELY SOKOLOFF TAYLOR & ZAFMAN LLP
1279 OAKMEAD PARKWAY
SUNNYVALE
CA
94085-4040
US
|
Assignee: |
Intel Corporation
Santa Clara
CA
|
Family ID: |
38877178 |
Appl. No.: |
12/247193 |
Filed: |
October 7, 2008 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11479740 |
Jun 30, 2006 |
|
|
|
12247193 |
|
|
|
|
Current U.S.
Class: |
361/718 |
Current CPC
Class: |
H01L 24/27 20130101;
H01L 2224/73253 20130101; H01L 2224/29111 20130101; H01L 2924/16152
20130101; H01L 2224/16225 20130101; H01L 2224/32225 20130101; H01L
2224/73204 20130101; H01L 2924/14 20130101; H01L 2224/0401
20130101; H01L 2924/16152 20130101; H01L 2924/01079 20130101; H01L
2924/15311 20130101; H01L 2224/274 20130101; H01L 2924/351
20130101; H01L 23/3675 20130101; H01L 2221/68359 20130101; H01L
2924/01029 20130101; H01L 21/6835 20130101; H01L 2924/351 20130101;
H01L 2224/29111 20130101; H01L 2924/14 20130101; H01L 2924/10253
20130101; H01L 2924/09701 20130101; H01L 2224/04026 20130101; H01L
21/4882 20130101; H01L 2224/73204 20130101; H01L 2924/10253
20130101; H01L 2924/00 20130101; H01L 2924/15311 20130101; H01L
2924/00 20130101; H01L 2224/32225 20130101; H01L 2224/16225
20130101; H01L 2224/73204 20130101; H01L 2224/73253 20130101; H01L
2224/16225 20130101; H01L 2924/01029 20130101; H01L 2924/00
20130101; H01L 2221/68309 20130101; H01L 23/42 20130101; H01L
2224/16 20130101; H01L 2924/00 20130101; H01L 2224/32225 20130101;
H01L 2924/00 20130101 |
Class at
Publication: |
361/718 |
International
Class: |
H05K 7/20 20060101
H05K007/20 |
Claims
1-8. (canceled)
9. A package comprising: a substrate; a die assembly attached to
the substrate, the die assembly comprising: a thin die having a
thickness, a first thermal interface material (TIM) deposited on
the thin die, and a first heat spreader (HS) attached to the thin
die through the first TIM; a second TIM attached to the first HS;
and a second heat spreader attached to the substrate and the second
TIM, the second heat spreader enclosing the die assembly.
10. The package of claim 9 further comprising: an underfill
dispensed between the die assembly and the substrate.
11. The package of claim 9 wherein the thickness is less than 50
.mu.m.
12. The package of claim 9 wherein the first TIM has a remelting
point higher than 250.degree. C.
13. The package of claim 9 wherein the first TIM has thickness less
than the second TIM.
14. The package of claim 9 wherein the first TIM has thickness of
approximately 5 .mu.m.
15. The package of claim 9 wherein the first heat spreader is
approximately equal to the thin die in size.
16. A system comprising: a front end processing unit to receive and
transmit a radio frequency (RF) signal, the RF signal being
converted to digital data; a digital processor coupled to the front
end processing unit to process the digital data; and a memory
device coupled to the digital processor, the memory device being
packaged in a package, the package comprising: a substrate, a die
assembly attached to the substrate, the die assembly comprising: a
thin die having a thickness, a first thermal interface material
(TIM) deposited on the thin die, and a first heat spreader (HS)
attached to the first TIM, a second TIM attached to the first HS,
and a second heat spreader attached to the substrate and the second
TIM, the second heat spreader enclosing the die assembly.
17. The system of claim 16 further comprising: an underfill
dispensed between the die assembly and the substrate.
18. The system of claim 16 wherein the thickness is less than 50
.mu.m.
19. The system of claim 16 wherein the first TIM has a remelting
point higher than 250.degree. C.
20. The system of claim 16 wherein the first TIM has thickness less
than the second TIM.
21. The system of claim 16 wherein the first TIM has thickness of
approximately 5 .mu.m.
22. The system of claim 16 wherein the first heat spreader is
approximately equal to the thin die in size.
Description
BACKGROUND
[0001] 1. Field of the Invention
[0002] Embodiments of the invention relate to the field of
semiconductor, and more specifically, to semiconductor
packaging.
[0003] 2. Description of Related Art
[0004] Advances in packaging technologies for semiconductor devices
have provided many opportunities for development of efficient
thermal management. One thermal management scheme is the use of
heat spreaders on semiconductor dice.
[0005] Existing techniques for attaching heat spreaders on
ultra-thin dice have a number of disadvantages. One technique uses
high accuracy pick-and-place equipment. This technique is
time-consuming, leading to delay and high cost in the manufacturing
cycle. In addition, when adhesive is used to form the heat spreader
array, releasing the heat spreaders to ultra-thin die bonding is
quite challenging.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Embodiments of invention may best be understood by referring
to the following description and accompanying drawings that are
used to illustrate embodiments of the invention. In the
drawings:
[0007] FIG. 1A is a diagram illustrating a manufacturing system in
which one embodiment of the invention can be practiced.
[0008] FIG. 1B is a diagram illustrating a system according to one
embodiment of the invention.
[0009] FIG. 2A is a diagram illustrating a carrier template
according to one embodiment of the invention.
[0010] FIG. 2B is a diagram illustrating placing heat spreaders
into cavities of the carrier template according to one embodiment
of the invention.
[0011] FIG. 2C is a diagram illustrating forming a heat spreader
(HS) array on a HS support substrate according to one embodiment of
the invention.
[0012] FIG. 2D is a diagram illustrating a diced wafer supported by
a wafer support substrate (WSS) according to one embodiment of the
invention.
[0013] FIG. 2E is a diagram illustrating bonding the thin dice in
the diced wafer to the heat spreaders in the HS array according to
one embodiment of the invention.
[0014] FIG. 2F is a diagram illustrating an HS-bonded diced wafer
supported by a WSS according to one embodiment of the
invention.
[0015] FIG. 2G is a diagram illustrating applying a dicing tape to
the HS-bonded diced wafer supported by a WSS according to one
embodiment of the invention.
[0016] FIG. 2H is a diagram illustrating releasing the WSS from the
HS-bonded diced wafer according to one embodiment of the
invention.
[0017] FIG. 2I is a diagram illustrating picking an individual die
assembly according to one embodiment of the invention.
[0018] FIG. 3 is a diagram illustrating a package according to one
embodiment of the invention.
[0019] FIG. 4 is a flowchart illustrating a process to assemble
wafer-level heat spreaders for dual HS packages according to one
embodiment of the invention.
[0020] FIG. 5 is a flowchart illustrating a process to form a HS
array on HS support substrate according to one embodiment of the
invention.
[0021] FIG. 6 is a flowchart illustrating a process to form diced
wafer supported by a WSS according to one embodiment of the
invention.
[0022] FIG. 7 is a flowchart illustrating a process to bond thin
dice to heat spreaders according to one embodiment of the
invention.
[0023] FIG. 8 is a flowchart illustrating a process to assemble a
HS-bonded thin die into a package according to one embodiment of
the invention.
DESCRIPTION
[0024] An embodiment of the present invention is a technique to
fabricate a package. A heat spreader (HS) array on a HS support
substrate is formed. The HS array has a plurality of heat
spreaders. A diced wafer supported by a wafer support substrate
(WSS) is formed. The diced wafer has a plurality of thin dice. The
thin dice in the diced wafer are bonded to the heat spreaders in
the HS array to form HS-bonded thin dice between the HS support
substrate and the WSS.
[0025] In the following description, numerous specific details are
set forth. However, it is understood that embodiments of the
invention may be practiced without these specific details. In other
instances, well-known circuits, structures, and techniques have not
been shown to avoid obscuring the understanding of this
description.
[0026] One embodiment of the invention may be described as a
process which is usually depicted as a flowchart, a flow diagram, a
structure diagram, or a block diagram. Although a flowchart may
describe the operations as a sequential process, many of the
operations can be performed in parallel or concurrently. In
addition, the order of the operations may be re-arranged. A process
is terminated when its operations are completed. A process may
correspond to a method, a program, a procedure, a method of
manufacturing or fabrication, etc.
[0027] An embodiment of the present invention is a technique to
fabricate a package having two heat spreaders. The technique
includes wafer-level bonding an array of heat spreaders to a diced
thinned wafer. A carrier template having an array of cavities is
fabricated with high precision. The dimensions and positions of the
cavities are carefully matched with the dimensions and positions of
the dice on the silicon wafer to which the heat spreaders are
bonded. The heat spreaders (HS) which have a thin layer of a solder
layer on one side are placed in the cavities of the carrier
template (i.e., the side with the solder of the HS faces the
carrier template). The thin solder layer acts as a first thermal
interface material (TIM) when the dice are assembled into packages.
A heat spreader support substrate covered by a thin layer of
silicone such as polydimethyl siloxane (PDMS) is then placed on the
heat spreaders under a pressure. Due to the van der Waals forces
between the PDMS and the heat spreaders, all the heat spreaders in
the carrier template adhere to the thin PDMS layer. The HS array is
transferred to the PDMS-coated support substrate. A diced wafer is
formed by mounting a wafer onto a wafer support substrate (WSS),
thinning the wafer, depositing a backside metallurgy (BSM) layer
and/or a thin solder layer on backside of the wafer, and dicing the
thinned wafer into thin dice without releasing dies from the WSS.
Then, the HS array is aligned and bonded to the thin dice on the
diced wafer by reflowing the solder layer on the HS array and/or Si
dice under pressure. The HS support substrate is then released from
the HS array-bonded wafer. The HS array-bonded wafer is then
mounted on a dicing tape and the WSS is released. The individual
HS-bonded dice are then assembled into packages. Each package has a
second TIM and a second heat spreader with a larger size for
further heat spreading.
[0028] The technique provides efficient placement of HS array
because the carrier template may be manufactured in advance with
high precision. Therefore, time-consuming high accuracy
pick-and-place operation for HS array is eliminated. In addition,
the technique eliminates the use of any adhesive for attaching the
heat spreaders on the support substrate and associated support
substrate releasing processing operations. Furthermore, the
compliant PDMS layer on the HS support substrate may better
compensate the non-co-planarity and HS thickness variations,
leading to better bond-line control between the heat spreaders and
the silicon dice.
[0029] FIG. 1A is a diagram illustrating a manufacturing system 5
in which one embodiment of the invention can be practiced. The
system 5 includes a wafer fabrication phase 10, wafer preparation
phase 15, a wafer dicing phase 20, a carrier template fabrication
phase 25, a heat spreader (HS) support substrate fabrication phase
30, a HS array formation phase 35, a wafer-level bonding phase 40,
a support substrate releasing phase 45, a die attachment phase 50,
an encapsulation and HIS attachment phase 55, and a stress testing
phase 60. The system 5 represents a manufacturing flow of a
semiconductor packaging process.
[0030] The wafer fabrication phase 10 fabricates the wafer
containing a number of dice. The individual dice may be any
microelectronic devices such as microprocessors, memory devices,
interface circuits, high power optical devices etc. The wafer
fabrication phase 10 includes typical processes for semiconductor
fabrication such as preparation of the wafer surface, growth of
silicon dioxide (SiO.sub.2), patterning and subsequent implantation
or diffusion of dopants to obtain the desired electrical
properties, growth or deposition of a gate dielectric, and growth
or deposition of insulating materials, depositing layers of metal
and insulating material and etching it into the desired patterns.
Typically the metal layers consist of aluminium or copper. The
various metal layers are interconnected by etching holes, called
"vias," in the insulating material.
[0031] The wafer preparation phase 15 prepares a wafer containing
dice for packaging and testing. During this phase, the wafers are
sorted after the patterning process. An inspection may be carried
out to check for wafer defects. Then, the wafer may be mounted on a
wafer support substrate (WSS) that adheres to the front side (or
bump side) of the wafer. The WSS provides mechanical support for
handling during subsequent phases. The wafer is then thinned to a
desired thickness to provide ultra-thin wafer. Additional
processing may be performed to prepare the wafer for subsequent
phases, such as deposition of backside metallization (BSM) or
solder layer on the wafer.
[0032] The wafer dicing phase 20 dices, cuts, or saws the wafer
into individual dice from the backside of the wafer. The dicing
depth may be well controlled such that only the thin wafer is diced
and the WSS may not be diced. High precision saw blade/laser and
image recognition unit may be used. De-ionized water may be
dispensed on the wafer to wash away any residual particles or
contaminants during the dicing. Then, the wafer is dried by being
spun at high spinning speed.
[0033] The carrier template fabrication phase 25 fabricates one or
more carrier templates to carry the heat spreaders to be bonded
with the dice on the wafer. The fabrication may be performed on
facilities outside the semiconductor fabrication facilities such as
by other vendors. The carrier template fabrication phase 25
receives information or data files regarding the dimensions and
positions of the dice on the wafer. This information is used to
fabricate the carrier templates with high precision.
[0034] The HS support substrate fabrication phase 30 fabricates the
HS support substrate to support the array of heat spreaders. The HS
support substrate may be used to hold the heat spreaders for
precision bonding with the dice.
[0035] The HS array formation phase 35 forms the HS array supported
by the HS support substrate. The heat spreaders may be fabricated
by HS manufacturers and used in this phase. The HS array contains
the heat spreaders that are positioned to correspond to the
positions of the dice on the wafer.
[0036] The wafer-level bonding phase 40 bonds the HS array to the
dice on the wafer. The bonding essentially attaches the heat
spreaders to the corresponding dice at the wafer level.
[0037] The support substrate releasing phase 45 releases the HS
support substrate and the wafer support substrate from the
assembly. The resulting assembly includes array of dice attached to
first heat spreaders.
[0038] The die attachment phase 50 attaches the die to a package
substrate. The substrate material depends on the packaging type. It
may be ceramic, organic, or inorganic such as silicon. The die may
be attached to a package substrate through flip chip
technology.
[0039] The encapsulation and IHS attachment phase 55 underfills the
gap between the die and the substrate and attaches an IHS.
Underfill material may be dispensed between the die and the
substrate. Integrated heat spreader (IHS) may be attached to the
die and substrate assembly. The fully assembled package 65 is ready
to be tested.
[0040] The stress testing phase 60 performs one or more tests such
as Highly Accelerated Stress Test (HAST) or biased-HAST on the
device package under stress conditions. A test chamber may be
designed to conduct a stress test. It may have monitoring circuits,
measurement circuits, and other data processing equipment. The
package 65 is placed in the test chamber subject to the stress
test. It may be powered or non-powered. Various stress tests may be
performed on the wafer or on the packaged devices 65 at various
points of the manufacturing process flow. The tests may follow
standards such as Joint Electron Device Engineering Council (JEDEC)
standards or military standards. Examples of these tests may
include electrostatic discharge (ESD), or human body model (HBM),
high temperature operational life (HTOL), thermal shock,
temperature cycle, high temperature storage, vibration and
mechanical loading, shear testing, and accelerated moisture
resistance.
[0041] FIG. 1B is a diagram illustrating a system 100 according to
one embodiment of the invention. The system 100 represents a mobile
communication module. It includes a system on package (SOP) 110, an
intermediate frequency processing unit 160, and a base-band
processing unit 170.
[0042] The SOP 110 represents the front end processing unit for the
mobile communication module. It is a transceiver incorporating
on-package integrated lumped passive components as well as radio
frequency (RF) components. It includes an antenna 115, a duplexer
120, a filter 125, a system-on-chip (SOC) 150, a power amplifier
(PA) 180, and a filter 185.
[0043] The antenna 115 receives and transmits RF signals. The RF
signals may be converted to digital data for processing in
subsequent stages. It is designed in compact micro-strip and
strip-line for L and C-band wireless applications. The duplexer 120
acts as a switch to couple to the antenna 115 to the receiver and
the transmitter to the antenna 115. The filters 125 and 185 are
C-band LTCC-strip-line filter or multilayer organic lumped-element
filter at 5.2 GHz and narrowband performance of 200 MHz suitable
for the Institute of Electrical and Electronic Engineers (IEEE)
802.11 wireless local area network (WLAN). The SOC 150 includes a
low noise amplifier (LNA) 130, a down converter 135, a local
voltage controlled oscillator (VCO) 140, an up converter 171, and a
driver amplifier 175. The LNA 130 amplifies the received signal.
The down converter 135 is a mixer to convert the RF signal to the
IF band to be processed by the IF processing unit 160. The up
converter 171 is a mixer to convert the IF signal to the proper RF
signal for transmission. The VCO 140 generates modulation signal at
appropriate frequencies for down conversion and up conversion. The
driver amplifier 175 drives the PA 180. The PA 180 amplifies the
transmit signal for transmission.
[0044] The IF processing unit 160 includes analog components to
process IF signals for receiving and transmission. It may include a
band-pass filter and a low pass filter at suitable frequency bands.
The filter may provide base-band signal to the base-band processing
unit 170. The base-band processing unit 170 may include an
analog-to-digital converter (ADC) 172, a digital-to-analog
converter (DAC) 174, a digital signal processor (DSP) 176, and
memory device 178. The ADC 172 and the DAC 174 are used to convert
analog signals to digital data and digital data to analog signal,
respectively. The DSP 176 is a programmable processor that may
execute a program to process the digital data. The memory device
178 may be flash memories or random access memories. It may be
packaged using Flip-Chip Ball Grid Array (FCBGA) packaging
technology, a molded packaging, or any other suitable packaging
technologies. The memory device 178 may be manufactured according
to the manufacturing flow 5 shown in FIG. 1A. It may be the device
package 65. It may include an ultra-thin die in the package. The
base-band processing unit 170 may also include memory and
peripheral components. The DSP 176 may, therefore, be coupled to
the front end processing unit via the IF processing unit 160 and/or
the base-band processing unit 170 to process the digital data.
[0045] The SOP 110 may be a multi-layer three-dimensional (3D)
architecture for a monolithic microwave integrated circuit (MMIC)
with embedded passives (EP) technology. It may be implemented using
Low Temperature Co-fired Ceramics (LTCC) and organic-based
technologies. The 3D architecture may include multiple layers
include a layer 117 to implement the antenna 115, layers 122, 124,
and 186 for the filters 125 and 185, and layer 188 for the SOC 150
and the passive components using EP technology. Typically, the
packaging technology involves embedded passives with multiple
layers.
[0046] FIG. 2A is a diagram illustrating a carrier template 210
according to one embodiment of the invention. The carrier template
210 may be manufactured in advance and separately from the
packaging process. The carrier template 210 may be made from
materials such as silicon. It has a number of cavities 215 with
tight dimensional tolerances. The cavities 215 may be formed or
fabricated using wet etching or any other etching processes.
[0047] The dimensions and positions of the cavities 215 are
carefully matched with the dimensions and positions of the heat
spreaders that are bonded to the corresponding dice on a wafer. The
dimensions and positions of the dice on the wafer are typically
known in advance and may be available in computer readable forms
which may be used to precisely control the formation of the
cavities 215. The fabrication of the carrier template 210 and the
cavities 215 may be performed independently and separately from the
packaging process.
[0048] FIG. 2B is a diagram illustrating placing heat spreaders
into cavities of the carrier template according to one embodiment
of the invention.
[0049] The carrier template 210 is placed in a shaker 212. The
shaker 212 may be a mechanical shaker that shakes or vibrates at a
predetermined rate. It typically has enclosure to keep items or
articles being shaken from being thrown out during shaking. A
number of heat spreaders are placed inside the shaker 212 on the
carrier template 210. The heat spreaders (HS) are designed to have
dimensions fit within the cavities 215, which in turn fit the
dimensions of the dice on the wafer. They may be made by any
material having a high thermal conductivity such as copper or SiC.
Through gravity and shaking forces, the heat spreaders self
assemble and fall into the cavities 215 to become HS 220. Heat
spreaders that do not fall into the cavities 215 are excess HS 225
and may be removed from the shaker 212. There are many other
methods of achieving the same impact as `shaking` using other
agitating methods such as acoustic agitation or electrostatic
agitation that results in the HSs self assembling in the required
cavities.
[0050] Alternatively, the heat spreaders may be placed into the
cavities 215 by a pick-and-place equipment. Since the carrier
template 210 is made of rigid material and is not a fragile object,
the pick-and-place equipment may place the heat spreaders in the
cavities 215 without high precision or accuracy. Through gravity,
the heat spreaders may settle into the cavities 215 when they are
slightly misplaced.
[0051] FIG. 2C is a diagram illustrating forming a heat spreader
(HS) array on a HS support substrate according to one embodiment of
the invention. The heat spreaders 220 in the cavities 215 are now
transferred to a HS support substrate 230. The HS support substrate
230 may be any suitable material, such as glass. It is coated or
covered by a thin layer of silicone 232. The silicone 232 may be
any polymer that has good adhesive property. One such polymer is
the poly-dimethyl siloxane (PDMS), a rubber material.
[0052] The HS support substrate 230 with the PDMS layer 232 is
placed, or pressed, on the HS 220 in the cavities 215 of the
carrier template 210. The PDMS layer 232 picks up all the HS 220
due to the van der Waals force. The HS 220 stay at the same
positions on the HS support substrate 230 as they are in the
cavities 215. Therefore, the HS 220 form an array of heat spreaders
that are located at positions to correspond or match with positions
of dice on a wafer. The carrier template 210 may be discarded or
re-used to hold a next array of heat spreaders. The HS support
substrate 230, the layer of silicone 232 and the HS array 220 form
the HS array 235 with HS support substrate.
[0053] FIG. 2D is a diagram illustrating a diced wafer 255
supported by a wafer support substrate (WSS) according to one
embodiment of the invention. The WSS-supported diced wafer 255
includes a WSS 245 and a number of singulated thinned dice
260.sub.1, to 260.sub.N.
[0054] First, the WSS 245 is mounted onto a wafer. The mounting may
be performed using an adhesive to attach the WSS 245 to the wafer.
The wafer is then thinned to a desired thickness. For ultra-thin
wafer, the thickness may be less than 75 .mu.m, or may be
approximately 50 .mu.m. Then, a backside metallurgy (BSM) layer 250
is deposited on the backside of the wafer. This BSM layer 250 may
have a thickness of about 3 to 10 .mu.m. It serves to provide the
basis for attachment during bonding. It may consist of a stack of
metal layers such as titanium (Ti), nickel (Ni) and gold (Au).
Besides these metal layers, it may also include a solder layer such
as tin-copper. The solder layer serve as the thermal interface
material (TIM) and it may have a process temperature range from
180.degree. C. to 280.degree. C. The solder material is carefully
designed such that, after bonding, the TIM layer has a high
remelting temperature (e.g., higher than 250.degree. C.) and thus
it does not melt again during die to substrate assembly processes.
Then, the thinned wafer and the BSM layer 250 are diced, sawed, or
singulated into individual dice.
[0055] FIG. 2E is a diagram illustrating bonding the thin dice in
the diced wafer 255 to the heat spreaders in the HS array 235
according to one embodiment of the invention.
[0056] The HS array 235 is then positioned so that the HS 220 face
toward to backside of the thinned wafer, or the thin dice
260.sub.j's (j=1, . . . , N). The thin dice 260.sub.j's in the
diced wafer 255 are then aligned to the HS 220 in the HS array with
HS support substrate 235. Since the HS 220 are positioned according
to the positions of the cavities, they are matched with the thin
dice 260.sub.j's.
[0057] The thin dice 260.sub.j's in the diced wafer 255 are then
bonded or attached to the HS 220 in the HS array with HS support
substrate 235. The bonding may be performed by reflowing the solder
layer on the HS array and/or the solder of the BSM layer 250 on the
wafer under pressure from at least one of the WSS 245 or the HS
support substrate 230. The pressure may be applied to both the WSS
245 and the HS support substrate 230, or one of them. The reflow
causes the HS 220 to be bonded or attached to the corresponding
thin dice 260.sub.j's.
[0058] FIG. 2F is a diagram illustrating an HS-bonded diced wafer
supported by a WSS according to one embodiment of the
invention.
[0059] The adhesion strength between the HS 220 to the thin dice
260j 's is typically greater than the van der Waals force that
keeps the HS 220 to the layer of silicone 232 on the HS support
substrate 230. Therefore, the HS support substrate 230 and the
coated layer of silicone 232 may be easily removed from the bonded
assembly. The removal may be performed by vacuum sucking. There are
other ways to release the HS 220 from the support substrate 230.
Chemical solvent/laser/heat may also be utilized to facilitate the
debonding.
[0060] FIG. 2G is a diagram illustrating applying a dicing tape to
the HS-bonded diced wafer supported by a WSS according to one
embodiment of the invention.
[0061] A dicing tape 270 is then attached or mounted onto the HS
220 of the thin dice assembly. The dicing tape 270 essentially
holds the individual die assemblies together.
[0062] FIG. 2H is a diagram illustrating releasing the WSS from the
HS-bonded diced wafer according to one embodiment of the
invention.
[0063] The WSS 245 is then released from the thin die assembly with
the dicing tape 270. The release of the WSS 245 may be carried out
by a number of methods including mechanical and thermal removal,
laser or ultraviolet (UV) light. The laser may be used to irradiate
the WSS 245. The irradiation may weaken the adhesion of adhesive
that is used to attach the WSS 245 to the wafer 240.
[0064] FIG. 2I is a diagram illustrating picking an individual die
assembly according to one embodiment of the invention.
[0065] After the WSS 245 is removed, a pick-and-place equipment or
tool may be used to pick up the individual die assemblies and
assemble them into packages. A die assembly 280 now has a die, a
first TIM, and a matching heat spreader.
[0066] FIG. 3 is a diagram illustrating a package 300 according to
one embodiment of the invention. The package 300 includes a
substrate 310, a die assembly 280, an underfill 320, a second TIM
330, and an integral heat spreader (IHS) 340. The die assembly 280
includes the thin die 240, a first TIM 250, and the HS 220. The
package 300 may be a package 65 for the memory 178 or the DSP 176
shown in FIGS. 1A and 1B.
[0067] The substrate 310 is a package substrate that provides
support for the thin die 240. The substrate 310 may be made of an
organic or inorganic materials. The substrate 310 may be selected
for any suitable packaging technologies including Ball Grid Array
(BGA), Pin Grid Array (PGA), or Land Grid Array (LGA). A number of
solder balls 315 may be attached to the substrate 310. The solder
balls 315 allow attachment of the package device 65/178 to a
circuit board or to any other mounting component. The die 240 is
any semiconductor die. It may have a microelectronic device such as
a microprocessor, a memory, an interface chip, an integrated
circuit, etc. The die 240 is attached to the substrate 310 by a
number of solder bumps 242. The bumps 242 provide contact with the
contact pads on the substrate. The bumps 242 may be fabricated
using any standard manufacturing or fabrication techniques such as
the controlled collapse chip connect (C4) technique.
[0068] The underfill 320 is dispensed between die 240 and the
substrate 310 to strengthen the attachment of die 240 to the
substrate 310 to help prevent the thermal stresses from breaking
the connections between die 240 and the substrate 310. The stresses
may be caused by the difference between the coefficients of thermal
expansion of die 240 and the substrate 310. The underfill 320 may
contain filler particles suspended in an organic resin. The size of
the filler particles are typically selected according to a gap
between the die 240 and the substrate 310, e.g., the filler
particles have a diameter about one third the size of the gap.
Generally, the composition and concentration of filler particles
are selected to control the coefficient of thermal expansion of the
underfill 320.
[0069] The IHS or second HS 340 may house or cover the die assembly
280 on the substrate 310. It may include a flat surface and
supporting walls on both or four sides of the die assembly 280.
During operation, the die 240 may generate heat. The heat may be
transferred to the IHS 340 through the first TIM 250 and a second
TIM 330. The second TIM 330 may have a thickness of approximately
10 to 50 .mu.m. The TIM 330 may be located, or interposed, between
the bottom surface of the IHS 250 and the top surface of the HS 220
to encapsulate the cover assembly 260. It may be attached to a heat
generating device, such as the die 240, to transfer the heat to a
heat spreader or a heat sink or any another heat dissipating
device. The TIM 330 may be made of a solder, a thermally conductive
adhesive, a thermal grease, phase change material, etc.
[0070] The package 300 thus has two heat spreaders: the first HS
240 and the second HS 340. The two heat spreaders may be of the
same or different materials. The package 300 also has two TIMs: the
first TIM 250 and the second TIM 330. The package 300 therefore has
a good heat transfer because the first HS 240 which has a much
higher thermal conductivity than silicon is brought closer to the
hot spots due to the thin silicon die and thin first TIM 250.
[0071] FIG. 4 is a flowchart illustrating a process 400 to assemble
wafer-level heat spreaders for dual HS packages according to one
embodiment of the invention.
[0072] Upon START, the process 400 forms a heat spreader (HS) array
on a HS support substrate (Block 410). The HS array has a plurality
of heat spreaders that have dimensions matched to the individual
dice on the wafer. Next, the process 400 forms a diced wafer
supported by a wafer support substrate (WSS) (Block 420). The diced
wafer has a plurality of thin dice. Then, the process 400 bonds the
thin dice in the diced wafer to the heat spreaders in the HS array
to form HS-bonded thin dice between the HS support substrate and
the WSS (Block 430).
[0073] Next, the process 400 releases the HS support substrate from
the HS array (Block 440). Then, the process 400 mounts the bonded
diced wafer onto a dicing tape (Block 450). Next, the process 400
releases the WSS from the diced wafer (Block 460). This may be
performed by decomposing adhesive between the WSS and the wafer by
laser. Then, the process 400 assembles an HS-bonded thin die into a
package (Block 470). The process 400 is then terminated.
[0074] FIG. 5 is a flowchart illustrating the process 410 shown in
FIG. 4 to form a HS array on HS support substrate according to one
embodiment of the invention.
[0075] Upon START, the process 410 fabricates a carrier template
having a plurality of cavities (Block 510). The dimensions and
positions of the cavities are matched to the dimensions and
positions of the thin dice on the wafer. Next, the process 410
places the plurality of heat spreaders in the cavities (Block 520).
This may be performed using self-assembly such as using the shaker
shown in FIG. 2B. Then, the process 410 places, or presses, the HS
support substrate coated with a layer of silicone such as PDMS on
the plurality of heat spreaders (Block 530). Under the pressing
force, the heat spreaders adhere to the layer of silicone through
the van der Waals force. Next, the process 410 picks up the
plurality of heat spreaders from the carrier template (Block 540).
The process 410 is then terminated.
[0076] FIG. 6 is a flowchart illustrating the process 420 shown in
FIG. 4 to form diced wafer supported by a WSS according to one
embodiment of the invention.
[0077] Upon START, the process 420 mounts a wafer on a wafer
support substrate (WSS) (Block 610). Next, the process 420 thins
the wafer to a desired thickness (Block 620). Any thinning
technique may be employed. For ultra-thin wafer, the desired
thickness may be less than 50 .mu.m. Then, the process 420 deposits
a backside metallurgy (BSM) layer on backside of the thinned wafer
(Block 630). The BSM layer may be made of any suitable material,
such as a solder. Next, the process 420 dices, saws, or singulates
the thinned wafer into the plurality of thin dice (Block 640). The
process 420 is then terminated.
[0078] FIG. 7 is a flowchart illustrating the process 430 shown in
FIG. 4 to bond thin dice to heat spreaders according to one
embodiment of the invention.
[0079] Upon START, the process 430 aligns the diced wafer to the HS
array to match the thin dice with the heat spreaders (Block 710).
Next, the process 430 reflows the solder layer under pressure on at
least one of the WSS and the HS support substrate (Block 720). The
reflow causes bonding or attachment of the array of heat spreaders
to the diced and thinned dice. The process 430 is then
terminated.
[0080] FIG. 8 is a flowchart illustrating the process 470 shown in
FIG. 4 to assemble a HS-bonded thin die into a package according to
one embodiment of the invention.
[0081] Upon START, the process 470 picks the HS-bonded thin die
from the dicing tape (Block 810). Next, the process 470 places, or
attaches, the HS-bonded thin die on a substrate (Block 820). Then,
the process 470 dispenses an underfill between the HS-bonded thin
die and the substrate (Block 830) and then cure the underfill.
[0082] Next, the process 470 applies a thermal interface material
(TIM) on the HS (Block 840). Then, the process 470 attaches an
integral heat spreader to the TIM and the substrate (Block 850).
The process 470 is then terminated.
[0083] An embodiment of the invention is described to provide
superior thermal and mechanical performance. Throughout the
process, the HS support substrate and the WSS provide mechanical
support for the HS array or the thin dice. After they serve their
function, they may be released from the assembly. The bonding of
the thin dice to the HS array is performed at the wafer level. The
resulting package essentially includes two integrated HSs. One is
directly on top of the die and the other is the normal IHS attached
to the first HS.
[0084] While the invention has been described in terms of several
embodiments, those of ordinary skill in the art will recognize that
the invention is not limited to the embodiments described, but can
be practiced with modification and alteration within the spirit and
scope of the appended claims. The description is thus to be
regarded as illustrative instead of limiting.
* * * * *