U.S. patent application number 12/162065 was filed with the patent office on 2009-01-22 for semiconductor chip with solder bump suppressing growth of inter-metallic compound and method of fabricating the same.
This patent application is currently assigned to NEPES CORPORATION. Invention is credited to Joon Young Choi, In Soo Kang.
Application Number | 20090020871 12/162065 |
Document ID | / |
Family ID | 36914089 |
Filed Date | 2009-01-22 |
United States Patent
Application |
20090020871 |
Kind Code |
A1 |
Kang; In Soo ; et
al. |
January 22, 2009 |
SEMICONDUCTOR CHIP WITH SOLDER BUMP SUPPRESSING GROWTH OF
INTER-METALLIC COMPOUND AND METHOD OF FABRICATING THE SAME
Abstract
A semiconductor chip having a solder bump and a method of
fabricating the same are provided. Conventionally, an
inter-metallic compound (IMC) unexpectedly grows at an interface of
the solder bump by means of heat generated during operation of the
semiconductor chip, thereby weakening mechanical property of the
semiconductor chip. To solve this drawback, the semiconductor chip
includes at least one metal adhesion layer formed on an electrode
pad of the semiconductor chip, an interlayer isolation layer formed
on the metal adhesion layer, at least one penetration layer formed
on the interlayer isolation layer and penetrating into the solder
bump, and the solder bump formed on the penetration layer. Thereby,
materials of the penetration layer penetrate into the solder bump
to change the solder bump into a multi-component solder bump, so
that the growth of the IMC is suppressed, and the reliability of
the semiconductor chip can be improved.
Inventors: |
Kang; In Soo; (Chungbuk,
KR) ; Choi; Joon Young; (Incheon, KR) |
Correspondence
Address: |
MARGER JOHNSON & MCCOLLOM, P.C.
210 SW MORRISON STREET, SUITE 400
PORTLAND
OR
97204
US
|
Assignee: |
NEPES CORPORATION
Chungbuk
KR
|
Family ID: |
36914089 |
Appl. No.: |
12/162065 |
Filed: |
February 8, 2006 |
PCT Filed: |
February 8, 2006 |
PCT NO: |
PCT/US06/04522 |
371 Date: |
July 24, 2008 |
Current U.S.
Class: |
257/737 ;
257/E21.508; 257/E23.068; 438/613 |
Current CPC
Class: |
H01L 2924/01322
20130101; H01L 2924/01049 20130101; H01L 2224/0347 20130101; H01L
2924/01051 20130101; H01L 2924/01024 20130101; H01L 2924/014
20130101; H03H 7/18 20130101; H01L 2924/01078 20130101; H01L
2924/01047 20130101; H01L 2924/01022 20130101; H03H 7/0161
20130101; H01L 2924/0103 20130101; H01L 2924/01082 20130101; H01L
2924/0002 20130101; H01L 2924/01079 20130101; H01P 5/18 20130101;
H01L 2224/03912 20130101; H02J 3/28 20130101; H01L 2224/0361
20130101; H01L 2924/01013 20130101; H01L 2224/03914 20130101; H01L
2924/01029 20130101; H01L 2924/01046 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/737 ;
438/613; 257/E23.068; 257/E21.508 |
International
Class: |
H01L 21/60 20060101
H01L021/60; H01L 23/498 20060101 H01L023/498 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 18, 2005 |
US |
11062179 |
Mar 1, 2005 |
US |
11069682 |
Claims
1. A semiconductor chip having a solder bump, comprising: at least
one metal adhesion layer formed on an electrode pad of the
semiconductor chip; an interlayer isolation layer formed on the
metal adhesion layer; at least one penetration layer formed on the
interlayer isolation layer and penetrating into the solder bump;
and the solder bump formed on the penetration layer.
2. The semiconductor chip according to claim 1, wherein among the
metal adhesion layers, a first metal adhesion layer is formed of at
least one of titan (Ti), Ti alloy, aluminum (Al), Al alloy, nickel
(Ni), Ni alloy, copper (Cu), Cu alloy, chromium (Cr), Cr alloy,
gold (Au), and Au alloy,
3. The semiconductor chip according to claim 1, wherein among the
metal adhesion layers, a second metal adhesion layer is formed as
needed, and is formed of at least one of Ni, Ni alloy, Cu, Cu
alloy, palladium (Pd), and Pd alloy.
4. The semiconductor chip according to claim 1, wherein the
interlayer isolation layer is formed of one of Ni, Ni alloy, Pd,
and Pd alloy.
5. The semiconductor chip according to claim 1, wherein the
penetration layer is formed of at least one of Cu, Cu alloy,
antimony (Sb), Sb alloy, indium (In), In alloy, tin (Sn), Sn alloy,
bismuth (Bi), Bi alloy, platinum (Pt), Pt alloy, gold (Au) and Au
alloy.
6. The semiconductor chip according to claim 1, wherein the
penetration layer forms 0.1 to 10% by weight of the solder bump by
controlling the thickness or the volume ratio of the penetration
layer.
7. The semiconductor chip according to claim 1, wherein the solder
bump is formed of one of Au, a lead (Pb)-free solder selected from
one of Sn, Sn/Ag, Sn/Cu, Sn/Zn, Sn/Zn/Bi, Sn/Ag/Cu, and Sn/Ag/Bi,
and a Pb solder selected from one of high Pb solder and eutectic Pb
solder.
8. A method of fabricating a semiconductor chip having a solder
bump, the method comprising the steps of: forming at least one
metal adhesion layer on an electrode pad of the semiconductor chip;
forming an interlayer isolation layer on the metal adhesion layer;
forming at least one penetration layer on the interlayer isolation
layer so as to penetrate into the solder bump when the solder bump
is formed; and forming the solder bump on the penetration
layer.
9. The method according to claim 8, further comprising the step of,
after the metal adhesion layer is formed, forming photoresist
patterns on opposite ends of a top surface of the metal adhesion
layer, wherein the interlayer isolation layer is formed on the
metal adhesion layer between the photoresist patterns.
10. The method according to claim 8, wherein the step of forming
the interlayer isolation layer is performed by a sputtering or
plating process.
11. The method according to claim 8, wherein the step of forming
the penetration layer is performed by a sputtering or plating
process.
12. The method according to claim 8, further comprising the step of
reflowing the solder bump.
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor chip with a
solder bump and a method of fabricating the same, and more
particularly, to a semiconductor chip having a solder bump
suppressing growth of an inter-metallic compound and a method of
fabricating the same.
BACKGROUND ART
[0002] In general, a semiconductor package is fabricated by
employing a wire bonding technique to electrically connect
electrode terminals of a printed circuit board with pads of a
semiconductor chip by means of conductive wires. However, since the
technique increases a size of the semiconductor package as compared
to that of the semiconductor chip and it takes much time to
complete a wire bonding process, it is limited to downsizing and
mass-production of semiconductor chips.
[0003] Particularly, due to high integration, high performance, and
high speed of the semiconductor chip, various efforts to downsize
and mass-produce the semiconductor package are tried. This recent
trial results in a proposal for the semiconductor package in which
the electrode terminals of a printed circuit board are directly and
electrically connected with the electrode pads of a semiconductor
chip through metal bumps such as solder bumps formed on the
electrode pads of the semiconductor chip.
[0004] This conventional semiconductor package fabricated through
solder bumps will be described below with reference to FIG. 1.
[0005] FIG. 1 is a sectional view illustrating a conventional
semiconductor chip having a solder bump.
[0006] Specifically, FIG. 1 illustrates that a solder bump 30 is
just formed on a conventional semiconductor chip 10 before
packaging work on the semiconductor chip using solder is
completed.
[0007] As shown in FIG. 1, the semiconductor chip 10 has an
electrode pad 11 formed thereon. Also, the semiconductor chip 10
has a dielectric layer 21 formed thereon to allow a top surface of
the electrode pad 11 to be exposed. One or more under bump metal
(UBM) layers, usually, three UBM layers 22, 23 and 24 are formed on
the electrode pad 11, the top surface of which is exposed by the
dielectric layer 21. Here, the three UBM layers include an adhesion
layer 22, a diffusion barrier layer 23, and a wettable layer 24.
The solder bump 30 is finally formed on the uppermost layer 24 of
the UBM layers 22, 23 and 24. Here, when being formed, the solder
bump 30 reacts with the UBM layers 22, 23 and 24, so that an
inter-metallic compound (IMC) is created at an interface between
the solder bump 30 and the UBM layers 22, 23 and 24. The creation
of IMC brings about a wetting phenomenon between the solder bump 30
and the UBM layers 22, 23 and 24, and thereby practical mechanical
connection is completed.
[0008] However, when the semiconductor package connected by the
solder bump 30 is actually used, heat can be generated from the
solder bump. This heat causes the IMC having brittle mechanical
property to unexpectedly grow at the interface between the solder
bump 30 and the UBM layers 22, 23 and 24, and thus the IMC may be
thicker than expected. This phenomenon may produce a result of
weakening the mechanical property of the semiconductor package, and
exert a great influence on reliability of the semiconductor
package.
[0009] Meanwhile, there may be other interfacial phenomena
influencing the reliability of the semiconductor package. Among
them, one is a phenomenon in which the solder bump 30 is melted
into the UBM layers 22, 23 and 24. As a result, the UBM layers 22,
23 and 24 are lost, and thus the solder bump 30 comes into direct
contact with a metal pad 11 in the semiconductor chip 10, so that a
failure takes place between the solder bump 30 and the metal pad 11
of the semiconductor chip 10 which has bad wettability.
DISCLOSURE OF THE INVENTION
[0010] Therefore, the present invention has been made in view of
the above-mentioned problems, and it is an objective of the present
invention to provide a semiconductor chip having a solder bump, in
which an interlayer isolation layer, and a penetration layer whose
materials can penetrate into the solder bump are formed between at
least one under bump metal (UBM) layer and the solder bump, thereby
allowing a composition of the solder bump to be changed, and thus
suppressing growth of an inter-metallic compound (IMC) at an
interface of the solder bump.
[0011] According to an aspect of the present invention, there is
provided a semiconductor chip having a solder bump. The
semiconductor chip includes at least one metal adhesion layer
formed on an electrode pad of the semiconductor chip, an interlayer
isolation layer formed on the metal adhesion layer, at least one
penetration layer formed on the interlayer isolation layer and
penetrating into the solder bump, and the solder bump formed on the
penetration layer.
[0012] With this construction, the metal adhesion layer is
separated from the solder bump through the interlayer isolation
layer, and a composition of the solder bump is changed through the
penetration layer, so that the growth of the IMC is suppressed.
[0013] At this time, among the metal adhesion layers, a first metal
adhesion layer may be formed of at least one of titan (Ti), Ti
alloy, aluminum (Al), Al alloy, nickel (Ni), Ni alloy, copper (Cu),
Cu alloy, chromium (Cr), Cr alloy, gold (Au), and Au alloy,
[0014] Further, among the metal adhesion layers, a second metal
adhesion layer may be formed as needed, and may be formed of at
least one of Ni, Ni alloy, Cu, Cu alloy, palladium (Pd), and Pd
alloy. Thereby, the first metal adhesion layer is more firmly
bonded with the interlayer isolation layer.
[0015] Also, the interlayer isolation layer may be formed of one of
Ni, Ni alloy, Pd, and Pd alloy.
[0016] The penetration layer may be formed of at least one of Cu,
Cu alloy, antimony (Sb), Sb alloy, indium (In), In alloy, tin (Sn),
Sn alloy, bismuth (Bi), Bi alloy, platinum (Pt), Pt alloy, gold
(Au) and Au alloy.
[0017] Further, the solder bump may be formed of one of Au,
eutectic Pb solder (Sn/37Pb), high Pb solder (Sn/95Pb), and a lead
(Pb)-free solder selected from one of Sn/Ag, Sn/Cu, Sn/Zn,
Sn/Zn/Bi, Sn/Ag/Cu, and Sn/Ag/Bi.
[0018] According to an aspect of the present invention, there is
provided a method of fabricating a semiconductor chip having a
solder bump. The method comprises the steps of forming at least one
metal adhesion layer on an electrode pad of the semiconductor chip,
forming an interlayer isolation layer on the metal adhesion layer,
forming at least one penetration layer on the interlayer isolation
layer so as to penetrate into the solder bump when the solder bump
is formed, and forming the solder bump on the penetration
layer.
[0019] Here, the method may further comprise the step of, after the
metal adhesion layer is formed, forming photoresist patterns on
opposite ends of a top surface of the metal adhesion layer. The
interlayer isolation layer may be formed on the metal adhesion
layer between the photoresist patterns. The step of forming the
interlayer isolation layer may be performed by a sputtering or
plating process. The step of forming the penetration layer may be
performed by a sputtering or plating process.
[0020] Further, the method may further comprise the step of
reflowing the solder bump. Thereby, the penetration layer
penetrates into the solder bump through the reflow process, so that
the growth of the IMC is suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The foregoing and other objects, features and advantages of
the present invention will become more apparent from the following
detailed description when taken in conjunction with the
accompanying drawings in which:
[0022] FIG. 1 is a sectional view illustrating a conventional
semiconductor chip having a solder bump;
[0023] FIG. 2 is a sectional view illustrating a semiconductor chip
having a solder bump suppressing growth of an inter-metallic
compound (IMC) in accordance with the present invention;
[0024] FIG. 3 is a flow chart illustrating a process of forming a
solder bump on a semiconductor chip so as to suppress growth of an
IMC in accordance with the present invention; and
[0025] FIGS. 4 through 12 are sectional views illustrating the
process of FIG. 3.
BEST MODE FOR CARRYING OUT THE INVENTION
[0026] Reference will now be made in detail to the exemplary
embodiments of the present invention.
[0027] FIG. 2 is a sectional view illustrating a semiconductor chip
having a solder bump suppressing growth of an inter-metallic
compound (IMC) in accordance with the present invention. As shown
in FIG. 2, the semiconductor chip 100 according to the present
invention has at least one electrode pad 110 formed thereon, and
the semiconductor chip 100 has a dielectric layer 210 partially
formed thereon to allow a top surface of the electrode pad 110 to
be exposed. One or more metal adhesion layers 220 and 230 are
formed on the electrode pad 110, the top surface of which is
exposed by the partially-formed dielectric layer 210. An interlayer
isolation layer 240 is formed on the metal adhesion layer 230. At
least one penetration layer 250 is formed on the interlayer
isolation layer 240 so as to penetrate into the solder bump when
the solder bump is formed. Finally, the solder bump 300 is formed
on the penetration layer 250.
[0028] More specifically, the electrode pad 110 may be composed of
metal, and is formed on the semiconductor chip 100. The electrode
pad 110 electrically connects the semiconductor chip 100 with an
external circuit board. The dielectric layer 210 is formed on the
semiconductor chip 100 so as to allow the top surface of the
electrode pad 110 to be exposed.
[0029] Among the metal adhesion layers 220 and 230, the first metal
adhesion layer 220 may be composed of at least one of titan (Ti),
Ti alloy, aluminum (Al), Al alloy, nickel (Ni), Ni alloy, copper
(Cu), Cu alloy, chromium (Cr), Cr alloy, gold (Au), and Au alloy,
and is formed on both the partially-formed dielectric layer 210 and
the electrode pad 110 whose top surface is exposed by the
dielectric layer 210. The UBM layers 220 and 230 may be preferably
formed at a thickness of 200 to 20000 .ANG..
[0030] The second metal adhesion layer 230 may be formed on the
first metal adhesion layer 220. At this time, the second metal
adhesion layer 230 may be composed of a material, which is suitable
to bond the first metal adhesion layer 220 and the interlayer
isolation layer 240, and preferably at least one of Ni, Ni alloy,
Cu, Cu alloy, palladium (Pd), and Pd alloy.
[0031] The interlayer isolation layer 240 may be composed of a
material, which is suitable to bond the metal adhesion layers 220
and 230 and the penetration layer 250, and preferably at least one
of Ni, Ni alloy, Pd, and Pd alloy. The interlayer isolation layer
240 is formed on the second metal adhesion layer 230, and thus
structurally separates the metal adhesion layers 220 and 230 from
the penetration layer 250 and the solder bump 300.
[0032] The penetration layer 250 may be composed of at least one of
Cu, Cu alloy, antimony (Sb), Sb alloy, indium (In), In alloy, tin
(Sn), Sn alloy, bismuth (Bi), Bi alloy, platinum (Pt), Pt alloy,
gold (Au) and Au alloy, and is formed on the interlayer isolation
layer 240. The penetration layer 250 may have variable thickness
depending on a size of the solder bump 300, and may form 0.1 to 10%
by weight in the solder bump 300. Among the materials forming the
penetration layer 250, Cu can give a great change to a shape and
growth of the IMC when the solder bump 300 is formed of Sn-rich
lead (Pb)-free solder. More specifically, a small quantity of Cu is
added to the solder bump 300 of SnAg, a property of the solder bump
300 can be improved. However, when Cu is supersaturated in the
solder bump 300, a melting point of the solder bump 300 may
increase. To this end, the penetration layer 250 is formed between
the solder bump 300 and the interlayer isolation layer 240.
Thereby, when the solder bump 300 is formed through a reflow
process, the penetration layer 250 is allowed to penetrate into the
solder bump 300.
[0033] The solder bump 300 may be composed of one of Au, Pb-free
solder, and Pb solder. Here, the Pb-free solder may be preferably
composed of at least one of Sn/Ag, Sn/Cu, Sn/Zn, Sn/Zn/Bi,
Sn/Ag/Cu, and Sn/Ag/Bi. The Pb solder may be selected from either
one of high Pb solder and eutectic Pb solder.
[0034] FIG. 3 is a flow chart illustrating a process of forming a
solder bump on a semiconductor chip so as to suppress growth of an
IMC in accordance with the present invention, and FIGS. 4 through
12 are sectional views illustrating the process of FIG. 3.
[0035] The process of forming a solder bump on a semiconductor chip
will be described below with reference to FIG. 3, and FIGS. 4
through 12.
[0036] First, as in FIG. 4, a electrode pad 110 is formed on a
semiconductor chip 100 (S101), and then a dielectric layer 210 is
formed across the semiconductor chip 100 so as to allow the top
surface of the electrode pad 110 to be exposed on the semiconductor
chip 100 (S102).
[0037] Subsequently, as in FIGS. 5 and 6, one or more metal
adhesion layers 220 and 230 are formed on the partially-formed
dielectric layer 210 and the electrode pad 110 whose top surface is
exposed by means of a sputtering or plating process (S103). The
metal adhesion layers 220 and 230 may have a structure composed of
a first metal adhesion layer 220 alone, or the first metal adhesion
layer 220/second metal adhesion layer 230.
[0038] Next, as illustrated in FIG. 7, photoresist patterns 301 are
formed on the second metal adhesion layer 230 in order to form an
interlayer isolation layer 240, a penetration layer 250, and a
solder bump 300 (S104).
[0039] Then, the interlayer isolation layer 240 is formed on the
second metal adhesion layer 230 by a plating or sputtering process
using the photoresist patterns 301 (S105). At this time, the
interlayer isolation layer 240 may be composed of a metal such as
nickel (Ni), as described above.
[0040] As illustrated in FIG. 8, at least one penetration layer 250
is formed on the interlayer isolation layer 240 by a plating or
sputtering process using the photoresist patterns 301 (S106). At
this time, the penetration layer 250 may be composed of metal such
as copper (Cu) as described above. The thickness or the volume
ratio of the penetration layer 250 can be adjusted to control a
quantity of the component of the penetration layer 250 penetrating
into the solder bump 300 during reflowing so that the penetration
layer 250 may form 0.1 to 10% by weight of the solder bump 300. In
case of using Pt, Pt alloy, Au, or Au alloy as the penetration
layer, the wettability with the solder bump can be enhanced and any
oxidation of under bump metal (such as the metal adhesion layer or
the isolation layer) can be prevented. These materials undergo
diffusion into the solder bump during reflow process, and thereby
prevent the IMC growth.
[0041] As illustrated in FIG. 9, the solder bump 300 is formed
using the photoresist patterns 301 (S107). At this time, the solder
bump 300 may be formed by an electroplating process, an electroless
plating process, an evaporation process, a ball attach process, a
screen printing process, a solder jet process and the like. As
described above, the solder bump 300 may be formed of one of Au, Pb
solder, and Pb-free solder.
[0042] Next, the photoresist patterns 301 are removed as
illustrated in FIG. 10, the metal adhesion layers 220 and 230 are
etched as illustrated in FIG. 11, and the solder bump 300 is
reflowed as illustrated in FIG. 12 (S108). At this time, the metal
adhesion layers 220 and 230 are etched by wet etching using
chemicals, or dry etching using a physical method. Meanwhile, on
reflowing, the penetration layer 250 is melted into the solder bump
300 and thus is lost. For this reason, a composition of the solder
bump 300 is changed. Therefore, the growth of the IMC which is a
problem of the conventional technology can be suppressed.
[0043] As can be seen from the foregoing, according to the present
invention, the interlayer isolation layer and the penetration layer
are formed in that order, and then the solder bump is formed on the
penetration layer. Thereby, the material composing the penetration
layer penetrates into the solder bump, and thus the solder bump is
changed into a multi-component solder bump. Thus, the growth of the
IMC is suppressed, and the reliability of the semiconductor chip
can be improved.
[0044] While this invention has been described in connection with
what is presently considered to be the most practical and preferred
embodiment, it is to be understood that the invention is not
limited to the disclosed embodiment and the drawings, but, on the
contrary, it is intended to cover various modifications and
variations within the spirit and scope of the appended claims.
* * * * *