U.S. patent application number 11/776710 was filed with the patent office on 2009-01-15 for process for finfet spacer formation.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Kangguo Cheng, Xi Li, Richard S. Wise.
Application Number | 20090017584 11/776710 |
Document ID | / |
Family ID | 40223862 |
Filed Date | 2009-01-15 |
United States Patent
Application |
20090017584 |
Kind Code |
A1 |
Cheng; Kangguo ; et
al. |
January 15, 2009 |
PROCESS FOR FINFET SPACER FORMATION
Abstract
A process for finFET spacer formation generally includes
depositing, in order, a conformnal liner material, a conformal
spacer material, and a conformal capping material onto the finFET
structure; tilt implanting dopant ions into portions of the capping
layer about the gate structure; selectively removing undoped
capping material about the source and drain regions; selectively
removing exposed portions of the spacer material; selectively
removing exposed portions of the capping material; anisotropically
removing a portion of the spacer material so as to expose a top
surface of the gate material and isolate the spacer material to
sidewalls of the gate structure; and removing the oxide liner from
the fin to form the spacer on the finFET structure.
Inventors: |
Cheng; Kangguo; (Beacon,
NY) ; Li; Xi; (Somers, NY) ; Wise; Richard
S.; (Newburgh, NY) |
Correspondence
Address: |
CANTOR COLBURN LLP - IBM FISHKILL
20 Church Street, 22nd Floor
Hartford
CT
06103
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
40223862 |
Appl. No.: |
11/776710 |
Filed: |
July 12, 2007 |
Current U.S.
Class: |
438/157 ;
257/E21.43 |
Current CPC
Class: |
H01L 29/785 20130101;
H01L 29/66795 20130101 |
Class at
Publication: |
438/157 ;
257/E21.43 |
International
Class: |
H01L 29/786 20060101
H01L029/786 |
Claims
1. A process for forming a spacer on a finFET structure,
comprising: providing a finFET structure free of a spacer
materials, the finFET structure comprising at least one vertical
fin body formed of a single crystal semiconductor material with
vertically-projecting sidewalls, source and drain regions at
opposite ends of the fin body, and a gate structure intersecting a
channel region of the fin body and electrically isolated from the
fin body; depositing, in order, a conformal liner material, a
conformal spacer material, and a conformal capping material onto
the finFET structure; tilt implanting dopant ions into portions of
the capping layer about the gate structure: selectively removing
undoped capping material about the source and drain regions;
selectively removing exposed portions of the spacer material;
selectively removing exposed portions of the capping material;
anisotropically removing a portion of the spacer material so as to
expose a top surface of the gate material and isolate the spacer
material to sidewalls of the gate structure; and removing the liner
from the fin to form the spacer on the finFET structure.
2. The elements of claim 1 wherein the capping layer is
polysilicon.
3. The elements of claim 1, wherein the spacer layer is a
nitride.
4. The elements of claim 1, wherein anisotropically removing the
portion of the spacer material comprises a RIE process.
5. The elements of claim 1 wherein the liner material is an
oxide.
6. The elements of claim 1, wherein the dopant ions are generated
from B, BF.sub.2 and combinations thereof.
Description
BACKGROUND OF THE INVENTION
[0001] 1. FIELD OF THE INVENTION
[0002] This invention generally relates to finFET spacer
formation.
[0003] 2. DESCRIPTION OF BACKGROUND
[0004] The term FinFET generally refers to a nonplanar, double-gate
transistor. Integrated circuits that include FinFETs may be
fabricated on a bulk silicon substrate or, more commonly, on a
silicon-on.insulator (SOI) wafer that includes an active SOI layer
of a single crystal semiconductor, such as silicon, a semiconductor
substrate, and a buried insulator layer, e.g., a buried oxide layer
that separates and electrically isolates the semiconductor
substrate from the SOI layer. Each FinFET generally includes a
narrow vertical fin body of single crystal semiconductor material
with vertically-projecting sidewalls. A gate contact or electrode
intersects a channel region of the fin body and is isolated
electrically from the fin body by a thin gate dielectric layer. At
opposite ends of the fin body are heavily-doped source/drain
regions.
[0005] Conventional methods of forming the fin body utilize
subtractive techniques in which a uniform thick layer of single
crystal silicon in patterned by masking and etching with process
likereactive ion etching (RIE). The width of the fin body is
related to the line width of a resist mask or a hard mask. The
nominal line width is specified either by photolithographic
techniques or by sidewall image transfer from an overlying spacer
but may be influenced by other factors. Forming the spacer around
the gate is essential for finFET fabrication. However, given the
three dimensional structure of the finFET, current processes for
forming the finFET are difficult to employ because the spacer is
undesirably formed about the source and the drain regions.
[0006] Accordingly, there is a need for fabrication processes for
spacer formation in finFET structures.
SUMMARY OF THE INVENTION
[0007] The shortcomings of the prior art are overcome and
additional advantges are provided through the provision of a
process for forming the spacer in the finFET structure. The process
includes providing a finFET structure free of a spacer material,
the finFET structure comprising at least one vertical fin body
formed of a single crystal semiconductor material with
vertically-projecting sidewalls, source and drain regions at
opposite end of the fin body; and a gate structure intersecting a
channel region of the fin body and electrically isolated from the
fin body; depositing, in order, a conformal liner material, a
conformal spacer material, and a conformal capping material onto
the finFET structure; tilt implanting dopant ions into portions of
the capping layer about the gate structure; selectively removing
undoped capping material about the source and drain regions;
selectively removing exposed portions of the spacer material;
selectively removing exposed portions of the capping material;
anisotropically removing a portion of the spacer material so as to
expose a top surface of the gate material and isolate the spacer
material to sidewalls of the gate structure; and removing the liner
from the fin to form the spacer on the finFET structure.
[0008] Additional features antd advantages are realized through the
techniques of the present invention. Other embodiments and aspects
of the invention are described in detail herein and are considered
a part of the claimed invention. For a better understanding of the
invention with advantages and features, refer to the description
and to the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The subject matter, which is regarded as the invention, is
particularly pointed out and distinctly claimed in the claims at
the conclusion of the specification. The foregoing and other
objects, features, and advantages of the invention are apparent
from the following detailed description taken in conjunction with
the accompanying drawings in which:
[0010] FIG. 1 illustrates a top down view of a finFET
structure;
[0011] FIG. 2 illustrates a cross sectional view of a finFET
structure taken along lines 2-2 of FIG. 1;
[0012] FIG. 3 illustrates a top down view of the finFET structure
of FIG. 1 after deposition of a liner layer, a spacer layer, and a
capping layer;
[0013] FIG. 4 illustrated a cross sectional view of the finFET
structure taken along lines 4-4 of FIG. 3;
[0014] FIG. 5 illustrates a top down view of the finFET structure
after tilted ion implantation of dopants in to the capping layer
disposed about the gate;
[0015] FIG. 6 illustrates a cross sectional view of the finFET
structure taken along lines 6-6 of FIG. 5;
[0016] FIG. 7 illustrates a top down view of the finFET structure
after selective removal of undoped capping layer about the source
and drain regions;
[0017] FIG. 8 illustrates a cross sectional view of the finFET
structure taken along lines 8-8 of FIG. 7;
[0018] FIG. 9 illustrates a top down view of the finFET structure
after removal of the exposed spacer layer;
[0019] FIG. 10 illustrates a cross sectional view of the finFET
structure taken along lines 10-10 of FIG. 9;
[0020] FIG. 11 illustrated a top down view of the finFET structure
after removal of the capping layer;
[0021] FIG. 12 illustrates a cross sectional view of the finFET
structure taken along lines along lines 12-12 of FIG. 11;
[0022] FIG. 13 illustrates a top down view of the finFET structure
after removal of the spacer layer to expose the gate sructure;
[0023] FIG. 14 illustrates a cross sectional view of the finFET
structure taken along lines 14-14 of FIG. 13;
[0024] FIG. 15 illustrates a top down view of the finFET structure
after removal of the liner layer;
[0025] FIG. 16 illustrates a cross sectional view of the finFET
structure taken along lines 16-16 of FIG. 15;
DETAILED DESCRIPTION OF THE INVENTION
[0026] The detailed description explains the preferred embodiments
of the invention, together with advantages and features, by way of
example with reference to the drawings.
[0027] Disclosed herein are processes for forming the spacer of a
finFET structure. It should be noted, however, the process decribed
herein for forming the spacer are equally applicable to any
fin-based, multigate transistor architecture regardless of number
of gates. Moreover, the present invention may be practiced in
conjunction with a various integrated circuit techniques that are
conventionally used in the art, and only so much of the commonly
practiced process steps are included herein as much as necessary to
provide an understanding the present invention.
[0028] As shown in FIGS. 1 and 2, the illustrated finFET structure,
generally designated by reference numeral 100, is fabricated on a
silicon substrate 102 having a buried oxide layer 104 and includes
a silicon source island 106 and a drain island 108 connected by a
silicon fin 110. The source, drain, and fin are covered by a
dielectric layer 112 (hard mask), and a gate 114 is formed that
extends across the fin 110. The fin is isolated from gate 114 by
gate oxide and the hard mask 112. The gate 114 may compromise an
oxide (i.e., SiO.sub.2) grown from either a dry oxygen ambient or
steam or a deposited layer of SiO.sub.2. Alternatively, the gate
dielectric 114 may be formed from any of the many candidates high
dielectric constant (high-k) materials, including but not limited
to Si.sub.3N.sub.4, silicon oxynitride (SiO.sub.xN.sub.y), a gate
dielectric stack of SiO.sub.2 and Si.sub.3N.sub.4, and metal oxides
like Ta.sub.2O.sub.5, as recognized by persons of ordinary skill in
the art. The fin 110 extends horizonatally on the substrate with
the gates in planes on either side of the fin.
[0029] The following discussion illustrates a method of fabricating
a spacer for the structure shown in FIGS. 1 and 2. In FIGS. 3 and
4, a liner layer 120, a spacer layer 122, and a capping layer 124
are conformly desposited onto the finFET structure 100. By way of
example, the liner layer can be an oxide material; the spacer layer
may be formed of nitride (e.g., Si.sub.3N.sub.4); and the capping
layer is polysilcon. The conformal depositon of the various layers
can be deposited by a conventional deposition process, such as
chemical vapor desposition (CVD) or plasma-assisted CVD. The
polysilicon layer can be deposited, for example, under the
condition fo 1 Torr and 620.degree. C, in the mixed gas of
SiH.sub.4, N.sub.2, and H.sub.2.
[0030] In FIGS. 5 and 6, tilted ion implantation of the capping
layer 126 about the gate structure 114 is illustrated. To that end,
a high concentration of a dopant is tilt implanted by implantation.
The dopant may be selected from Boron (B), borofluoride (BF.sub.2)
or a combination of these elements, and may be introduced at an
atomic concentration ranging from about 1E18 to 2E20 cm.sup.-3 to
about cm.sup.-3.
[0031] In FIGS. 7 and 8, the undoped capping layer 126 is
selectively removed from about the source and drain regions 106,
108, therby exposing the underlying spacer layer 124 in those area.
The undoped portions of the capping layer 126 can be removed using
a selective etch process.
[0032] In FIGS. 9 and 10, the exposed portions of the spacer layer
124 about the source and drain regions 106, 108 is selectively
removed with an anistrophic etch process such as by RIE, thereby
exposing portions of the liner layer 122, i.e., exposing portions
of the liner layer 122 about the source and drain regions 106,
108.
[0033] In FIGS. 11 and 12, the capping layer 122 is then removed
from the gate structure to expose the spacer layer 124 on the gate
structure 114.
[0034] In FIGS. 13 and 14, a portion of the spacer layer 124 is
removed by RIE so as to expose the gate polysilicon structure 114
while maintaining the spacer layer 124 on sidewalls of gate
structure 114.
[0035] In FIGS. 15 and 16, the remaining liner material is removed
so as to form the spacer using oxide selective plasma etches or wet
etches (e.g. hot phosphoric acid).
[0036] In summary, the process generally includes conformally
depositing on a finFET structure a liner layer, spacer layer and
polysilicon layer; implanting ions into the polysilicon surrounding
the gate; selectively removing undoped poly about the source and
drain regions; removing the exposed spacer film, removing the doped
polysilcon film; and removing a portion of the spacer layer such
that the gate material is exposed.
[0037] The flow diagrams depicted herein are just examples. There
may be many variations to these diagrams or the steps (or
operations) described therein without departing from the spirit of
the invention. For instance, the steps may be performed in a
differing order, or steps may be added, deleted or modified. All of
these variations are considered a part of the claimed
invention.
[0038] While the preferred embodiments to the invention has been
described, it will be understood that those skilled in the art,
both now and in the future, may make various improvement and
enhancements which fall within the scope of the claims which
follow. These claims should be construed to maintain the proper
protection for the invention first described.
* * * * *