U.S. patent application number 12/010806 was filed with the patent office on 2008-11-06 for field effect transistor having germanium nanorod and method of manufacturing the same.
Invention is credited to Se-young Cho, Joong S. Jeon, Suk-pil Kim, Ho Lee, Jung-hyun Lee, Nae-in Lee, Chang-wook Moon, Yeon-sik Park, Hwa-sung Rhee.
Application Number | 20080272366 12/010806 |
Document ID | / |
Family ID | 39938939 |
Filed Date | 2008-11-06 |
United States Patent
Application |
20080272366 |
Kind Code |
A1 |
Moon; Chang-wook ; et
al. |
November 6, 2008 |
Field effect transistor having germanium nanorod and method of
manufacturing the same
Abstract
A field effect transistor having at least one Ge nanorod and a
method of manufacturing the field effect transistor are provided.
The field effect transistor may include a gate oxide layer formed
on a silicon substrate, at least one nanorod embedded in the gate
oxide layer having both ends thereof exposed, a source electrode
and a drain electrode connected to opposite sides of the at least
one Ge nanorod, and a gate electrode formed on the gate oxide layer
between the source electrode and the drain electrode.
Inventors: |
Moon; Chang-wook; (Seoul,
KR) ; Jeon; Joong S.; (Seongnam-si, KR) ; Lee;
Jung-hyun; (Yongin-si, KR) ; Lee; Nae-in;
(Seoul, KR) ; Park; Yeon-sik; (Suwon-si, KR)
; Rhee; Hwa-sung; (Seongnam-si, KR) ; Lee; Ho;
(Cheonan-si, KR) ; Cho; Se-young; (Seoul, KR)
; Kim; Suk-pil; (Yongln-si, KR) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON
VA
20195
US
|
Family ID: |
39938939 |
Appl. No.: |
12/010806 |
Filed: |
January 30, 2008 |
Current U.S.
Class: |
257/24 ;
257/E21.403; 257/E21.411; 257/E29.051; 257/E29.069; 257/E29.271;
257/E29.297; 438/285 |
Current CPC
Class: |
H01L 29/7839 20130101;
H01L 2221/1094 20130101; H01L 29/0673 20130101; H01L 29/78696
20130101; H01L 21/02356 20130101; H01L 21/02365 20130101; H01L
29/0669 20130101; B82Y 10/00 20130101; H01L 51/426 20130101; H01L
29/66439 20130101; H01L 29/0665 20130101; H01L 29/66742 20130101;
H01L 29/1033 20130101; H01L 29/78684 20130101; B82Y 15/00 20130101;
H01L 21/02601 20130101 |
Class at
Publication: |
257/24 ; 438/285;
257/E29.069; 257/E21.403 |
International
Class: |
H01L 29/12 20060101
H01L029/12; H01L 21/336 20060101 H01L021/336 |
Foreign Application Data
Date |
Code |
Application Number |
May 3, 2007 |
KR |
10-2007-0043025 |
Claims
1. A field effect transistor, comprising: a gate oxide layer on a
silicon substrate: at least one Ge nanorod embedded in the gate
oxide layer having both ends thereof exposed; a source electrode
and a drain electrode connected to opposite sides of the Ge
nanorod; and a gate electrode on the gate oxide layer between the
source electrode and the drain electrode.
2. The field effect transistor of claim 1, wherein the at least one
Ge nanorod comprises 2 to 5 nanorods separated from each other.
3. The field effect transistor of claim 1, wherein the at least one
Ge nanorod has a diameter of about 1 to about 20 nm.
4. The field effect transistor of claim 1, wherein the at least one
Ge nanorod in a channel region has a circular or an oval
cross-section.
5. The field effect transistor of claim 1, wherein the source
electrode and the drain electrode form a Schottky barrier junction
with the at least one Ge nanorod.
6. The field effect transistor of claim 5, wherein the source
electrode and the drain electrode are formed of a metal selected
from the group consisting of Pt, Ni, Co, V, Yb, and Er.
7. The field effect transistor of claim 1, wherein the gate oxide
layer is a dielectric layer having a dielectric constant higher
than that of silicon oxide.
8. The field effect transistor of claim 7, wherein the gate oxide
layer is formed of one selected from the group consisting of
Si.sub.3N.sub.4, Ta.sub.2O.sub.5, HfO.sub.2, Zr.sub.2O.sub.5,
Al.sub.2O.sub.3, HfO.sub.xN.sub.y, HfSiO, and HfSiON.
9. The field effect transistor of claim 8, wherein the gate
electrode comprises: a first metal layer formed of one selected
from Ta, TaN, and TiN; and a second metal layer formed of
polysilicon on the first metal layer.
10. A method of manufacturing a field effect transistor, the method
comprising: forming an insulating layer and a first silicon layer
on a silicon substrate; sequentially forming a SiGe layer and a
second silicon layer on the first silicon layer; forming silicon
oxide layers by oxidizing the first and second silicon layers and
Si of the SiGe layer on the silicon substrate, and forming at least
one Ge nanorod from the SiGe layer; forming a source electrode and
a drain electrode contacting opposite ends of the at least one Ge
nanorod; forming a gate oxide layer that surrounds the at least one
Ge nanorod in a region for forming a channel region between the
source electrode and the drain electrode; and forming a gate
electrode on the gate oxide layer.
11. The method of claim 10, wherein the sequentially forming of the
SiGe layer and the second silicon layer is repeated 2 to 5 times on
the first silicon layer.
12. The method of claim 10, wherein the insulating layer is formed
of a material having an etching rate different from that of the
silicon oxide layers.
13. The method of claim 10, wherein forming the source electrode
and the drain electrode comprises: forming a first photoresist in
the region for forming the channel region; exposing both ends of
the at least one Ge nanorod by removing the silicon oxide layers in
regions for forming the source electrode and the drain electrode;
and depositing a metal having a work function greater than that of
Ge in the regions for forming the source electrode and the drain
electrode.
14. The method of claim 10, wherein forming the gate oxide layer
comprises: exposing the at least one Ge nanorod by removing the
silicon oxide layers in the region for forming the channel region;
and forming the gate oxide layer that surrounds the at least one Ge
nanorod using a material having a dielectric constant higher than
that of silicon oxide.
15. The method of claim 14, further comprising: forming a
cross-section of the at least one Ge nanorod in the channel region
into a circle or an oval shape by annealing the silicon substrate
in a H.sub.2 or D.sub.2 atmosphere prior to forming the gate oxide
layer.
16. The method of claim 14, wherein the material is one selected
from the group consisting of Si.sub.3N.sub.4, Ta.sub.2O.sub.5,
HfO.sub.2, Zr.sub.2O.sub.5, Al.sub.2O.sub.3, HfO.sub.xN.sub.y,
HfSiO, and HfSiON.
17. The method of claim 16, wherein the forming of the gate
electrode comprises forming a first metal layer formed of one
selected from Ta, TaN, and TiN and forming a second metal layer
formed of polysilicon on the first metal layer.
18. The method of claim 10, wherein the SiGe layer has a
composition of Si.sub.1-xGe.sub.x, where 0.1<x<0.5.
19. The method of claim 10, wherein the source electrode and the
drain electrode are formed of a metal selected from the group
consisting of Pt, Ni, Co, V, Yb, and Er.
20. The method of claim 10, wherein the gate oxide layer is formed
of silicon oxide, and the forming of the gate electrode comprises
forming a polysilicon layer.
21. The method of claim 10, wherein the at least one Ge nanorod has
a diameter of about 1 to about 20 nm.
Description
PRIORITY STATEMENT
[0001] This application claims priority under 35 U.S.C. .sctn. 119
to Korean Patent Application No. 2007-0043025, filed on May 3,
2007, in the Korean Intellectual Property Office (KIPO), the entire
contents of which are herein incorporated by reference.
BACKGROUND
[0002] 1. Field
[0003] Example embodiments relate to a field effect transistor
having a germanium nanorod as a channel and a method of
manufacturing the same.
[0004] 2. Description of Related Art
[0005] A conventional field effect transistor includes a silicon
channel region between a source and a drain on a silicon substrate
as a moving path of carriers. In order to turn on the silicon
channel region, a predetermined gate voltage must be applied
between the source and the drain. As a result, the speed of the
device is determined according to the mobility of the main
carriers, for example, holes.
[0006] The speed of a device that employs a transistor depends on
the mobility of the main carriers in the silicon channel, and thus,
much research to increase the mobility of the main carriers have
been conducted. In order to increase the mobility of the main
carriers, germanium, which has a higher mobility than silicon, has
been used.
SUMMARY
[0007] Example embodiments provide a field effect transistor having
a germanium nanorod that may have improved mobility suitable for a
high speed operation transistor. Example embodiments also provide a
method of manufacturing a field effect transistor having a
germanium nanorod and a method of manufacturing the germanium
nanorod.
[0008] According to example embodiments, a field effect transistor
having Ge nanorods may comprise a gate oxide layer on a silicon
substrate, at least one nanorod embedded in the gate oxide layer
having both ends thereof exposed, a source electrode and a drain
electrode connected to opposite sides of the Ge nanorod, and a gate
electrode on the gate oxide layer between the source electrode and
the drain electrode.
[0009] The Ge nanorod may comprise 2 to 5 nanorods separated from
each other.
[0010] The Ge nanorod may have a diameter of about 1 to about 20
nm.
[0011] The Ge nanorod in the channel region may have a circular or
an oval cross-section.
[0012] The source electrode and the drain electrode may form a
Schottky barrier junction with the Ge nanorod, and may be formed of
a metal selected from the group consisting of Pt, Ni, Co, V, Yb,
and Er.
[0013] The gate oxide layer may be a dielectric layer having a
dielectric constant higher than that of silicon oxide or silicon
nitride, and may be formed of one selected from the group
consisting of Si.sub.3N.sub.4, Ta.sub.2O.sub.5, HfO.sub.2,
Zr.sub.2O.sub.5, Al.sub.2O.sub.3, HfO.sub.xN.sub.y, HfSiO, and
HfSiON.
[0014] The gate electrode may comprise a first metal layer formed
of one selected from Ta, TaN, and TiN, and a second metal layer
formed of polysilicon on the first metal layer.
[0015] According to example embodiments, a method of manufacturing
a field effect transistor may comprise forming an insulating layer
and a first silicon layer on a silicon substrate, sequentially
forming a SiGe layer and a second silicon layer on the first
silicon layer, forming silicon oxide layers by oxidizing the first
and second silicon layers and the Si of the SiGe layer on the
silicon substrate, and forming the Ge nanorod from the SiGe layer.
The method may further comprise forming a source electrode and a
drain electrode contacting opposite ends of the Ge nanorod, forming
a gate oxide layer that surrounds the Ge nanorod in a region for
forming a channel region between the source electrode and the drain
electrode, and forming a gate electrode on the gate oxide
layer.
[0016] The sequentially forming of the SiGe layer and the second
silicon layer on the first silicon layer may be repeated 2 to 5
times on the first silicon layer.
[0017] The insulating layer may be formed of a material having an
etching rate different from that of the silicon oxide layers.
[0018] The forming of the source electrode and the drain electrode
may comprise forming a first photoresist in the region for forming
the channel region, exposing both ends of the Ge nanorod by
removing the silicon oxide layers in the regions for forming the
source electrode and the drain electrode, and depositing a metal
having a work function greater than that of Ge in the regions for
forming the source electrode and the drain electrode.
[0019] The forming of the gate oxide layer may comprise exposing
the Ge nanorod by removing the silicon oxide layer in the region
for forming the channel region, and forming the gate oxide layer
that surrounds the Ge nanorod using a material having a higher
dielectric constant than that of silicon oxide.
[0020] The method may further comprise forming a cross-section of
the Ge nanorod in the channel region into a circle or an oval shape
by annealing the silicon substrate in a H.sub.2 or D.sub.2
atmosphere prior to forming the gate oxide layer.
[0021] The forming of the gate electrode on the gate oxide layer
may comprise forming a first metal layer formed of one selected
from Ta, TaN, and TiN and forming a second metal layer formed of
polysilicon on the first metal layer.
[0022] The SiGe layer may have a composition of Si.sub.1-xGe.sub.x,
where 0.1<x<0.5.
[0023] The gate oxide layer may be formed of silicon oxide, and the
forming of the gate electrode on the gate oxide layer may comprise
forming a polysilicon layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Example embodiments will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings. FIGS. 1-10 represent non-limiting, example
embodiments as described herein.
[0025] FIG. 1 is a cross-sectional view of a field effect
transistor having a Ge nanorod according to example embodiments;
and
[0026] FIGS. 2 through 10 are perspective views illustrating a
method of manufacturing a field effect transistor having a Ge
nanorod according to example embodiments.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0027] Reference will now be made in detail to example embodiments,
examples of which are illustrated in the accompanying drawings.
However, example embodiments are not limited to the embodiments
illustrated hereinafter, and the embodiments herein are rather
introduced to provide easy and complete understanding of the scope
and spirit of example embodiments. In the drawings, the thicknesses
of layers and regions are exaggerated for clarity.
[0028] It will be understood that when an element or layer is
referred to as being "on," "connected to" or "coupled to" another
element or layer, it may be directly on, connected or coupled to
the other element or layer or intervening elements or layers may be
present. In contrast, when an element is referred to as being
"directly on," "directly connected to" or "directly coupled to"
another element or layer, there are no intervening elements or
layers present. Like reference numerals refer to like elements
throughout. As used herein, the term "and/or" includes any and all
combinations of one or more of the associated listed items.
[0029] It will be understood that, although the terms first,
second, third etc. may be used herein to describe various elements,
components, regions, layers and/or sections, these elements,
components, regions, layers and/or sections should not be limited
by these terms. These terms are only used to distinguish one
element, component, region, layer or section from another region,
layer or section. Thus, a first element, component, region, layer
or section discussed below could be termed a second element,
component, region, layer or section without departing from the
teachings of example embodiments.
[0030] Spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper" and the like, may be used herein for ease
of description to describe one element or feature's relationship to
another element(s) or feature(s) as illustrated in the figures. It
will be understood that the spatially relative terms are intended
to encompass different orientations of the device in use or
operation in addition to the orientation depicted in the figures.
For example, if the device in the figures is turned over, elements
described as "below" or "beneath" other elements or features would
then be oriented "above" the other elements or features. Thus, the
exemplary term "below" may encompass both an orientation of above
and below. The device may be otherwise oriented (rotated 90 degrees
or at other orientations) and the spatially relative descriptors
used herein interpreted accordingly.
[0031] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
example embodiments. As used herein, the singular forms "a," "an"
and "the" are intended to include the plural forms as well, unless
the context clearly indicates otherwise. It will be further
understood that the terms "comprises" and/or "comprising," when
used in this specification, specify the presence of stated
features, integers, steps, operations, elements, and/or components,
but do not preclude the presence or addition of one or more other
features, integers, steps, operations, elements, components, and/or
groups thereof.
[0032] Example embodiments are described herein with reference to
cross-sectional illustrations that are schematic illustrations of
example embodiments (and intermediate structures). As such,
variations from the shapes of the illustrations as a result, for
example, of manufacturing techniques and/or tolerances, are to be
expected. Thus, example embodiments should not be construed as
limited to the particular shapes of regions illustrated herein but
are to include deviations in shapes that result, for example, from
manufacturing. For example, an implanted region illustrated as a
rectangle may, typically, have rounded or curved features and/or a
gradient of implant concentration at its edges rather than a binary
change from implanted to non-implanted region. Likewise, a buried
region formed by implantation may result in some implantation in
the region between the buried region and the surface through which
the implantation takes place. Thus, the regions illustrated in the
figures are schematic in nature and their shapes are not intended
to illustrate the actual shape of a region of a device and are not
intended to limit the scope of example embodiments.
[0033] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which example
embodiments belong. It will be further understood that terms, such
as those defined in commonly used dictionaries, should be
interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and will not be
interpreted in an idealized or overly formal sense unless expressly
so defined herein.
[0034] FIG. 1 is a cross-sectional view of a field effect
transistor 100 having a Ge nanorod according to example
embodiments.
[0035] Referring to FIG. 1, an insulating layer 120 may be formed
on a silicon substrate 110. A gate oxide layer 130, which may be a
dielectric layer having a higher dielectric constant, may be formed
on the silicon substrate 110. The gate oxide layer 130 may be
formed of SiO.sub.2 or a material having a dielectric constant
greater than SiO.sub.2 (e.g., Si.sub.3N.sub.4, Ta.sub.2O.sub.5,
HfO.sub.2, Zr.sub.2O.sub.5, Al.sub.2O.sub.3, HfO.sub.xN.sub.y,
HfSiO, or HfSiON). In this case, x and y in HfO.sub.xN.sub.y may be
integers.
[0036] The insulating layer 120 may be formed of a material having
an etching rate different from that of silicon oxide that may be
produced in the oxidation process, and may be formed of silicon
oxide by oxygen ion implantation or silicon nitride.
[0037] Two Ge nanorods 140 separated from each other may be
embedded horizontally in the gate oxide layer 130. The two Ge
nanorods 140 may have a circle or an oval cross-section with a
diameter of about 1 to about 20 nm. If the cross-section of the Ge
nanorods 140 is a circle, an electric field may uniformly enter the
Ge nanorods 140, and thus, leakage current may be reduced.
[0038] Although the field effect transistor 100 in FIG. 1 may
include two Ge nanorods 140, example embodiments are not limited
thereto, and 2 to 5 Ge nanorods may be formed parallel to each
other. If only one Ge nanorod 140 is formed in the field effect
transistor 100, a disconnection failure may occur. If more than 6
Ge nanorods 140 are formed in the field effect transistor 100, the
manufacturing process may become more complicated. The Ge nanorods
140 may be channels (e.g., paths of main carriers) in the field
effect transistor 100, for example, holes. The Ge nanorods 140 may
provide a carrier mobility in a channel region of the field effect
transistor 100 higher than that of a conventional field effect
transistor.
[0039] The gate oxide layer 130 formed of a dielectric having a
higher dielectric constant may reduce gate leakage current by
surrounding the Ge nanorods 140.
[0040] A source electrode 151 and a drain electrode 152, which may
be electrically connected to the Ge nanorods 140, may be formed on
opposite sides of the Ge nanorods 140. The source electrode 151 and
the drain electrode 152 may form a Schottky barrier junction with
the Ge nanorods 140. In this case, the source electrode 151 and the
drain electrode 152 may be formed of a metal having a work function
greater than Ge. Germanides may be formed on contact surfaces
between the Ge nanorods 140 and the source electrode 151, and
between the Ge nanorods 140 and the drain electrode 152. In order
to form a p-type electrode, Pt or Ni may be used, and, in order to
form an n-type electrode, Yb or Er may be used.
[0041] A gate electrode 160 may be formed on the gate oxide layer
130 between the source electrode 151 and the drain electrode 152.
The gate electrode 160 may include a first metal layer 161 formed
of Ta, TaN, or TiN and a second metal layer 162 formed of
polysilicon. If the gate oxide layer 130 is formed of SiO.sub.2,
the gate electrode 160 may include only the second metal layer 162.
Also, if the gate oxide layer 130 is formed of a material having a
dielectric constant higher than SiO.sub.2 (e.g., Si.sub.3N.sub.4,
Ta.sub.2O.sub.5, HfO.sub.2, Zr.sub.2O.sub.5, Al.sub.2O.sub.3,
HfO.sub.xN.sub.y, HfSiO, or HfSiON), the gate electrode 160 may
have a structure in which the first metal layer 161 and the second
metal layer 162 are stacked. X and y in HfO.sub.xN.sub.y may be
integers. The second metal layer 162 may reduce the depletion
region in the channel region, thereby facilitating the formation of
the channel.
[0042] In the field effect transistor 100 according to example
embodiments, because the gate oxide layer 130 formed of a higher
dielectric material may be disposed around the Ge nanorods 140,
channel opening may be easier when a gate voltage is applied to the
gate electrode 160, thereby reducing the driving voltage. Also,
because the Ge nanorods 140 having a higher mobility than silicon
may be used in the field effect transistor 100, the speed of a
device including the field effect transistor 100 according to
example embodiments may be increased.
[0043] A method of manufacturing the field effect transistor 100
having the Ge nanorods 140 and a method of manufacturing the Ge
nanorods 140 according to example embodiments will now be
described.
[0044] FIGS. 2 through 10 are perspective views illustrating a
method of manufacturing the field effect transistor 100 having the
Ge nanorods 140. The same reference numerals are used to indicate
elements that are substantially similar to the elements of FIG. 1,
and thus, a detailed description thereof will be omitted.
[0045] Referring to FIG. 2, an insulating layer 120 having an
etching rate different from silicon oxide, which may be formed in a
process of oxidizing silicon, may be formed on a silicon substrate
110. A first silicon layer 121 may be formed on the insulating
layer 120. The insulating layer 120 may be a silicon oxide layer of
a silicon on insulator (SOI) substrate formed by implanting oxygen
in the silicon substrate 110 or a silicon nitride layer.
[0046] SiGe layers 122 and 124 and second silicon layers 123 and
125 may then be alternately formed on the first silicon layer 121.
In FIG. 2, the SiGe layers and the second silicon layers may be
alternately deposited twice on the first silicon layer 121, for
example, and the SiGe layers and the second silicon layers may be
alternately deposited 2 to 5 times on the first silicon layer 121.
The SiGe layers 122 and 124 and the silicon layers 121, 123, and
125 may be formed using a chemical vapour deposition (CVD)
method.
[0047] The SiGe layers 122 and 124 may have a composition of
Si.sub.1-xGe.sub.x, where x may be about 0.1 to about 0.5, and may
be deposited to a thickness of about 1 to about 20 nm. The silicon
layers 121, 123, and 125 may also be formed to a thickness of about
1 to about 20 nm. The resultant product as illustrated in FIG. 2
may be obtained by patterning the silicon layers 121, 123, and 125
and the second silicon layers 123 and 125.
[0048] Referring to FIG. 3, the resultant product of FIG. 2 may be
annealed in a furnace at a temperature of about 800 to 900.degree.
C. for about 1 to 5 minutes under an oxygen atmosphere. The silicon
layers 121, 123, and 125 and the SiGe layers 122 and 124 may be
partly oxidized. As a result, silicon layers 121', 123', and 125'
formed by the oxidation may have a reduced width. In the SiGe
layers 122 and 124, Si may be separated from Ge and may be
oxidized. As a result, only Ge layers 122' and 124' having a rod
shape may remain. This result may indicate that the SiGe layers 122
and 124 may be oxidized faster than the silicon layers 121, 123,
and 125. Thus, the SiGe layers 122 and 124 may become Ge nanorods
122' and 124' (corresponding to the Ge nanorods 140 of FIG. 1) that
may function as channels. Reference numeral 126 indicates a
SiO.sub.2 region formed due to the oxidation of the silicon layers
121, 123, and 125 and the Si of the SiGe layers 122 and 124.
[0049] Referring to FIG. 4, after a first photoresist P1 is formed
in a region between the regions for forming the source and drain
electrodes on the silicon substrate 110, SiO.sub.2 that may not be
covered by the first photoresist P1 may be removed by wet
etching.
[0050] Referring to FIG. 5, the resultant product in FIG. 4 may be
annealed in a furnace at a temperature of about 800 to 900.degree.
C. for about 1 to 5 minutes under an oxygen atmosphere. The silicon
layers 121', 123', and 125' in the regions for forming the source
and drain electrodes may be oxidized, and may be removed in the
subsequent etching process. Both ends of the nanorods 122' and 124'
in the regions for forming the source and drain electrodes may be
exposed.
[0051] Referring to FIG. 6, a source electrode 151 and a drain
electrode 152 may be formed by depositing a metal in the regions
for forming the electrodes. At this point, the source electrode 151
and the drain electrode 152 may be formed of a metal having a work
function greater than Ge so as to form a Schottky barrier junction
therebetween. The Ge nanorods 122' and 124' and the source
electrode 151 and the drain electrode 152 may form a germanide on
the contact region therebetween. In order to form a p-type
electrode, Pt or Ni may be used, and in order to form an n-type
electrode, Yb or Er may be used.
[0052] Referring to FIG. 7, the first photoresist P1 (refer to FIG.
6) may be removed, and SiO.sub.2 126 (refer to FIG. 6) covering the
region for forming a channel may be etched by wet etching.
[0053] The silicon layers 121', 123', and 125' in the regions for
forming electrodes may then be oxidized into a first silicon oxide
(not shown) by annealing the silicon substrate 110. After a second
silicon oxide layer (not shown) is formed on the silicon substrate
110 to cover the first silicon to form the gate oxide layer 130
(refer to FIG. 1), the gate electrode 160 (refer to FIG. 1) may be
formed on the gate oxide layer. The gate electrode 160 may be
formed as a monolayer using polysilicon.
[0054] Alternatively, the gate oxide layer may be formed of a
material having a dielectric constant greater than that of the
silicon oxide layer. Referring to FIG. 8, the first silicon oxide
formed by oxidizing the silicon layers 121', 123', and 125' in the
regions for forming electrodes may be removed by etching.
[0055] Referring to FIG. 9, the silicon substrate 110 may be
annealed under an atmosphere of H.sub.2 or D.sub.2 at a partial
pressure of about 2% to about 5% of the total pressure. As a
result, cross-sections of the Ge nanorods 122' and 124' may have a
circle or an oval shape.
[0056] The gate oxide layer 130 may then be formed using a higher
dielectric material (e.g., one material selected from
Si.sub.3N.sub.4, Ta.sub.2O.sub.5, HfO.sub.2, Zr.sub.2O.sub.5,
Al.sub.2O.sub.3, HfO.sub.xN.sub.y, HfSiO, and HfSiON) in the region
for forming a channel. The gate oxide layer 130 may be formed to
surround the Ge nanorods 122' and 124'.
[0057] Referring to FIG. 10, a gate electrode 160 may be formed on
the gate oxide layer 130. The gate electrode 160 may include a
first metal layer 161 formed of one material selected from Ta, TaN,
and TiN and a second metal layer 162 formed of polysilicon on the
first metal layer 161.
[0058] A field effect transistor according to example embodiments
may include Ge nanorods having a mobility greater than silicon as a
channel, thereby increasing the driving speed and reducing the
driving voltage of a device including the field effect
transistor.
[0059] Also, a p-type transistor or an n-type transistor may be
formed according to the material used to form the electrodes.
Because in example embodiments, Ge nanorods may be used as a
channel, a higher speed and lower power consumption transistor may
be developed.
[0060] In a method of manufacturing a field effect transistor
according to example embodiments, the Ge nanorods, which may be a
channel region, may be readily formed using an oxidation process
and an etching process.
[0061] The foregoing is illustrative of example embodiments and is
not to be construed as limiting thereof. Although example
embodiments have been described, those skilled in the art will
readily appreciate that many modifications are possible in example
embodiments without materially departing from the novel teachings
and advantages of example embodiments. Accordingly, all such
modifications are intended to be included within the scope of the
claims. Therefore, it is to be understood that the foregoing is
illustrative of example embodiments and is not to be construed as
limited to the specific embodiments disclosed, and that
modifications to the disclosed embodiments, as well as other
embodiments, are intended to be included within the scope of the
appended claims. Example embodiments are defined by the following
claims, with equivalents of the claims to be included therein.
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