U.S. patent application number 11/687983 was filed with the patent office on 2008-10-02 for reversible sequential element and reversible sequential circuit thereof.
This patent application is currently assigned to NATIONAL TSING HUA UNIVERSITY. Invention is credited to Min Lun Chuang, Chun Yao Wang.
Application Number | 20080238479 11/687983 |
Document ID | / |
Family ID | 39764172 |
Filed Date | 2008-10-02 |
United States Patent
Application |
20080238479 |
Kind Code |
A1 |
Wang; Chun Yao ; et
al. |
October 2, 2008 |
REVERSIBLE SEQUENTIAL ELEMENT AND REVERSIBLE SEQUENTIAL CIRCUIT
THEREOF
Abstract
A reversible sequential element comprises a first logic gate and
a second logic gate. The first logic gate includes a first input
terminal, a second input terminal, a third input terminal, a first
output terminal coupled to the first input terminal, a second
output terminal and a third output terminal. The second logic gate
includes a first input line, a second input line, a first output
line and a second output line. When the first input terminal is set
to a first state, the second input terminal is coupled to the third
output terminal and the third input terminal is coupled to the
second output terminal; otherwise, the second input terminal is
coupled to the second output terminal and the third input terminal
is coupled to the third output terminal. The third output terminal,
second input line and second output line are coupled to each other.
The input signal carried on the first input line is set as 0 so
that the second output line and the first output line have the same
output.
Inventors: |
Wang; Chun Yao; (Hsinchu
City, TW) ; Chuang; Min Lun; (Hsinchu City,
TW) |
Correspondence
Address: |
WPAT, PC;INTELLECTUAL PROPERTY ATTORNEYS
2030 MAIN STREET, SUITE 1300
IRVINE
CA
92614
US
|
Assignee: |
NATIONAL TSING HUA
UNIVERSITY
Hsinchu
TW
|
Family ID: |
39764172 |
Appl. No.: |
11/687983 |
Filed: |
March 19, 2007 |
Current U.S.
Class: |
326/46 |
Current CPC
Class: |
H03K 3/0372
20130101 |
Class at
Publication: |
326/46 |
International
Class: |
H03K 19/173 20060101
H03K019/173 |
Claims
1. A reversible sequential element, comprising: a first logic gate
including a first input terminal, a second input terminal, a third
input terminal, a first output terminal coupled to the first input
terminal, a second output terminal and a third output terminal,
wherein the second input terminal is coupled to the third output
terminal and the third input terminal is coupled to the second
output terminal when the first input terminal is set to a first
state, and otherwise the second input terminal is coupled to the
second output terminal and the third input terminal is coupled to
the third output terminal; and a second logic gate including a
first input line, a second input line, a first output line and a
second output line coupled to the third output terminal and the
second input line, wherein an input signal carried on the first
input line is set as a constant level so that outputs of the second
output line and the first output line are identical.
2. The reversible sequential element of claim 1, wherein an output
signal carried on the first output line is fed back to the third
input terminal.
3. The reversible sequential element of claim 1, wherein the first
logic gate is a Fredkin gate.
4. The reversible sequential element of claim 1, wherein the second
logic gate is a 2-bit Toffoli gate.
5. The reversible sequential element of claim 1, wherein the second
input terminal and the third output terminal have the same
transition in binary levels, and the third input terminal and the
second output terminal have the same transition in binary levels
when the first input terminal is set to 1 as the first state.
6. The reversible sequential element of claim 1, wherein the second
input terminal and the second output terminal have the same
transition in binary levels and the third input terminal and the
third output terminal have the same transition in binary levels
when the first input terminal is set to 0 as a second state.
7. The reversible sequential element of claim 1, wherein the first
input terminal carries a clock signal, the second input terminal
carries a data input signal and the third input terminal carries a
data input signal.
8. The reversible sequential element of claim 1, wherein the
reversible sequential element acts as a reversible D latch.
9. A reversible sequential circuit, comprising two reversible
sequential elements, each of the reversible sequential elements
including: a first logic gate including a first input terminal, a
second input terminal, a third input terminal, a first output
terminal coupled to the first input terminal, a second output
terminal and a third output terminal, wherein the second input
terminal is coupled to the third output terminal and the third
input terminal is coupled to the second output terminal when the
first input terminal is set to a first state, and otherwise the
second input terminal is coupled to the second output terminal and
the third input terminal is coupled to the third output terminal;
and a second logic gate including a first input line, a second
input line, a first output line and a second output line coupled to
the third output terminal and the second input line, wherein an
input signal carried on the first input line is set as a constant
level so that outputs of the second output line and the first
output line are identical and an output signal carried on the first
output line is fed back to the third input terminal; wherein the
second output line of the first one of the reversible sequential
elements is connected to the second input terminal of the second
one of the reversible sequential elements and the first output
terminal of the first reversible sequential element is connected to
the first input terminal of the second reversible sequential
element through an inverter.
10. The reversible sequential circuit of claim 9, wherein the first
logic gate is a Fredkin gate.
11. The reversible sequential circuit of claim 9, wherein the
second logic gate is a 2-bit Toffoli gate.
12. The reversible sequential circuit of claim 9, wherein the
second input terminal and the third output terminal have the same
transition in binary levels, and the third input terminal and the
second output terminal have the same transition in binary levels
when the first input terminal is set to 1 as the first state.
13. The reversible sequential circuit of claim 9, wherein the
second input terminal and the second output terminal have the same
transition in binary levels, and the third input terminal and the
third output terminal have the same transition in binary levels
when the first input terminal is set to 0 as a second state.
14. The reversible sequential circuit of claim 9, wherein the first
input terminal carries a clock signal, the second input terminal
carries a data input signal and the third input terminal carries a
data input signal.
15. The reversible sequential circuit of claim 9, wherein the
reversible sequential element acts as a reversible D latch.
16. The reversible sequential circuit of claim 9, wherein the
reversible sequential circuit acts as a reversible D flip-flop.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a reversible sequential
element and a reversible sequential circuit, and more particularly
to a reversible sequential element configured by reversible gates
and a reversible sequential circuit configured by the reversible
sequential elements.
[0003] 2. Description of the Related Art
[0004] Reversible computing does not result in information loss
during the computation process. Thus, it naturally takes care of
heating generated due to information loss. Zero energy dissipation
would be possible only if the gates in a network are all
reversible. As a result, reversibility will become an essential
property in future circuit design. Reversible logic has been
applied to various future technologies, such as ultra-low-power
CMOS design, optical computing, quantum computing and
nanotechnology. These technologies increasingly employ reversible
logic gates to reduce power computation.
[0005] However, the conventional logic gates are almost
irreversible. Among the commonly used gates, only NOT gate is
reversible. AND gate and OR gate are irreversible because they
cannot satisfy the condition of one-to-one and onto mapping between
the inputs and outputs of a logic gate. One way to make the AND
function reversible is to add one input and two outputs, as shown
in FIG. 1(a). These additional input and outputs for reversibility
are called garbage bits. The AND function can be obtained in the
third output column xy.quadrature.z (.quadrature. representing an
XOR gate) of FIG. 1(a), when setting z=0. The truth table of AND
function is shown in bold.
[0006] This whole truth table is equivalent to the truth table of
3-bit Toffoli gate, and its symbol is shown in FIG. 1(b). The third
output column xy.quadrature.z means that the output is z when
x=y=1, and otherwise the output is z. This gate can be used to
realize a 2-input reversible AND function by setting z as a
constant 0, as mentioned.
[0007] Fredkin gate is a reversible gate as well and is also called
controlled SWAP gate. FIG. 2(a) is the symbol of Fredkin gate and
FIG. 2(b) is its truth table. Its behavior can be described as
follows: if the control bit x is set to 1, the outputs of y and z
are swapped, otherwise they remain unchanged.
[0008] A restriction on reversible logic synthesis has to be
followed: the fanout count of a signal net must equal one so that a
duplication is necessary if two copies of one signal are needed.
This restriction is due to the fact that fanout structure itself is
not reversible. For fanout, the number of input signals is one, but
there are two or more output signals. Therefore, for this
restriction, a 2-bit Toffoli gate is utilized to duplicate a
signal. The symbol of a 2-bit Toffoli gate and its truth table are
shown in FIGS. 3(a) and 3(b), respectively. The function of the
second output column is x.quadrature.y. If y is set as a constant
0, a copy of input variable x will be obtained in the second
output, which is shown in bold. Therefore, the fanout structure in
a conventional network can be implemented in this way.
[0009] There are two objectives in reversible circuit synthesis:
[0010] 1. Minimize the number of gates: the number of gates gives a
simple estimation of the implementation cost of a reversible
circuit. [0011] 2. Minimize the number of garbage outputs: we need
extra implementation cost (area and power) for those garbage
outputs in reversible circuits. Minimizing the number of garbage
outputs leads to minimizing the chip area and power consumption of
a reversible circuit.
[0012] However, the synthesis result of a traditional D latch is
not good when the conventional direct transformation method is used
to implement a reversible D latch. This is because the D latch is
built by many irreversible gates; using the direct transformation
method to construct a reversible D latch will require a large
number of gates and garbage outputs.
SUMMARY OF THE INVENTION
[0013] An objective of the present invention is to provide a
reversible sequential element built by a minimum number of gates
and a reversible sequential circuit built by the reversible
sequential elements. The implementation cost of each of the
reversible sequential element and reversible sequential circuit is
substantially reduced.
[0014] Another objective of the present invention is to provide a
reversible sequential element with a minimum garbage outputs and a
reversible sequential circuit built by the reversible sequential
elements. Accordingly, the chip area and power consumption of each
of the reversible sequential element and reversible sequential
circuit are also minimized.
[0015] In order to achieve the objective, the present invention
discloses a reversible sequential element comprising a first logic
gate and a second logic gate. The first logic gate includes a first
input terminal, a second input terminal, a third input terminal, a
first output terminal, a second output terminal and a third output
terminal. The second logic gate includes a first input line, a
second input line, a first output line and a second output line.
Apparently, the terminals are used to designate the inputs and
outputs of the first logic gate and the lines are used to designate
the inputs and outputs of the second logic gate. The first input
terminal for carrying an input signal is coupled to the first
output terminal. When the first input terminal is set to a first
state, the second input terminal is coupled to the third output
terminal and the third input terminal is coupled to the second
output terminal; otherwise, the second input terminal is coupled to
the second output terminal and the third input terminal is coupled
to the third output terminal. The third output terminal, second
input line and second output line are coupled to each other. The
input signal carried on the first input line is set as a constant
level so that the second output line and the first output line have
the same output. Furthermore, the first output line is fed back to
the third input terminal.
[0016] The present invention further discloses a reversible
sequential circuit comprising two aforesaid reversible sequential
elements that are respectively named as a first reversible
sequential element and a second reversible sequential element. The
second output line of the first reversible sequential element is
connected to the second input terminal of the second reversible
sequential element. The first output terminal of the first
reversible sequential element is connected to the first input
terminal of the second reversible sequential element through an
inverter.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The invention will be described according to the appended
drawings in which:
[0018] FIG. 1(a) is the truth table of a 3-bit Toffoli gate;
[0019] FIG. 1(b) is the symbol of a 3-bit Toffoli gate;
[0020] FIG. 2(a) is the symbol of a Fredkin gate;
[0021] FIG. 2(b) is the truth table of a Fredkin gate;
[0022] FIG. 3(a) is the symbol of a 2-bit Toffoli gate;
[0023] FIG. 3(b) is the truth table of a 2-bit Toffoli gate;
[0024] FIG. 4(a) is the augmented truth table of a D latch in
accordance with the present invention;
[0025] FIG. 4(b) is the configuration of a D latch in accordance
with the present invention;
[0026] FIG. 4(c) shows the functional verification on the D latch
in accordance with the present invention;
[0027] FIG. 5(a) is the truth table of a D flip-flop in accordance
with the present invention; and
[0028] FIG. 5(b) is the configuration of a D flip-flop in
accordance with the present invention.
PREFERRED EMBODIMENT OF THE PRESENT INVENTION
[0029] FIG. 4(a) is the augmented truth table of a D latch in
accordance with the present invention. Regarding the present
embodiment, a truth table extension method is used to construct the
novel design of the D latch. Unlike the direct transformation
method, those irreversible gates are not directly replaced with the
reversible ones within a sequential element. Alternatively, the
original irreversible truth table of a sequential D latch is
extended to an augmented reversible one. The first output clk' and
second output D' are two garbage outputs that make the original D
latch reversible, as shown in FIG. 4(a). The minimum number of
garbage outputs required for reversibility is .left
brkt-top.log(q).right brkt-bot., where q is the maximum number of
times an output pattern is repeated in the truth table. In this
embodiment, 0 and 1 are repeated four times in the output column
Q.sub.n+1 so that .left brkt-top.log(4).right brkt-bot. is equal to
2. Accordingly, the additional outputs clk' and D' make the table
reversible. Compared with the truth table in FIG. 2(b), the
augmented truth table is identical. This means we only need one
Fredkin gate to implement a reversible D latch. Apparently, the
values of the present truth table are assigned in different ways,
so the design may be different.
[0030] After synthesizing this augmented reversible function, the
fanout problem is incurred and should be resolved. The input Q in
the next state comes from the current output Q.sub.n+1. Thus, an
additional Q.sub.n+1 is needed for feedback. Accordingly, a 2-bit
Toffoli gate is used to duplicate the output variable Q.sub.n+1.
The complete implementation of the reversible D latch 40 is shown
in FIG. 4(b).
[0031] The reversible D latch 40 comprises a Fredkin gate 41 and a
2-bit Toffoli gate 42. The Fredkin gate 41 includes a first input
terminal clk 411 for carrying a clock signal, a second input
terminal D 412 for carrying a data input signal, a third input
terminal Q.sub.n 413 for carrying another data input signal, a
first output terminal clk' 414, a second output terminal D' 415 and
a third output terminal 416. The 2-bit Toffoli gate 42 includes a
first input line 421, a second input line 422, a first output line
Q.sub.n+1 423 and a second output line Q.sub.n+1 424. Apparently,
we use the terminals to designate the inputs and outputs of the
Fredkin gate 41 and use the lines to designate the inputs and
outputs of the 2-bit Toffoli gate 42. The first input terminal clk
411 is coupled to the first output terminal clk' 414. When the
first input terminal clk 411 is set to a first state such as 1, the
second input terminal D 412 is coupled to the third output terminal
416 and the third input terminal Q.sub.n 413 is coupled to the
second output terminal D' 415; otherwise, when the first input
terminal clk 411 is set to a second state such as 0, the second
input terminal D 412 is coupled to the second output terminal D'
415 and the third input terminal Q.sub.n 413 is coupled to the
third output terminal 416. The third output terminal 416, second
input line 422 and second output line Q.sub.n+1 424 are coupled to
each other. The input signal carried on the first input line 421 is
set as 0 so that the second output line Q.sub.n+1 424 and the first
output line Q.sub.n+1 423 have the same output Q.sub.n+1. In this
embodiment, the input signal carried on the first input line 421 is
set to 0 as a constant level. If an inverter or an equivalent
circuit is added to the first input line 421, the input signal
would be set to 1 as a constant level. Furthermore, the first
output line Q.sub.n+1 424 is fed back to the third input terminal
Q.sub.n 413.
[0032] Whether the design of the reversible D latch 40 exactly
implements the behavior of a D latch would be verified. The
leftmost part of the symbol in FIG. 4(c) shows the Boolean
functions obtained from the augmented truth table of D latch in
FIG. 4(a). To simplify the expression of Boolean equations, the
symbol "C" is used to represent input variable clk. The rightmost
part of the symbol in FIG. 4(c) shows the functions of implemented
reversible D latch. There two expressions are identical, and
therefore the functionality of the reversible D latch is
correct.
[0033] A flip-flop is an edge-triggered sequential element while a
latch is a level-sensitive sequential element. A traditional D
flip-flop consists of two D latches and one inverter. The first D
latch is called the master and the second one is called the slave.
Since a reversible D latch has been built, as shown in FIG. 4(b), a
reversible D flip-flop can be constructed directly by replacing the
D latch and inverter with its reversible versions. The behavior and
structure of a reversible D flip-flop 50 are shown in FIG. 5(a) and
FIG. 5(b). The D flip-flop design can be traced and compared with
its function in the truth table in FIG. 5(a). The behavior of
implemented D flip-flop is the same as that of the truth table.
[0034] The D flip-flop 50 comprises two reversible D latches 40.
The second output line Q.sub.n+1 424 of the left D latch 40 is
connected to the second input terminal D 412 of the right D latch
40. The first output terminal 414 of the left D latch 40 is
connected to the first input terminal 413 of the right D latch 40
through an inverter gate 51 replacing an inverter.
[0035] The aforementioned descriptions of the present invention are
intended to be illustrative only. Numerous alternative methods may
be devised by persons skilled in the art without departing from the
scope of the following claims.
* * * * *