U.S. patent application number 11/728890 was filed with the patent office on 2008-10-02 for forming a type i heterostructure in a group iv semiconductor.
Invention is credited to Chi On Chui, Jack T. Kavalieros, Prashant Majhi, Wilman Tsai.
Application Number | 20080237572 11/728890 |
Document ID | / |
Family ID | 39792645 |
Filed Date | 2008-10-02 |
United States Patent
Application |
20080237572 |
Kind Code |
A1 |
Chui; Chi On ; et
al. |
October 2, 2008 |
FORMING A TYPE I HETEROSTRUCTURE IN A GROUP IV SEMICONDUCTOR
Abstract
In one embodiment, the present invention includes a method for
forming a transistor that includes forming a first buffer layer of
silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate,
forming a barrier layer on the first buffer layer, the barrier
layer comprising silicon germanium (Si.sub.1-xGe.sub.x), and
forming a quantum well (QW) layer on the barrier layer including a
lower QW barrier layer formed of silicon germanium carbon
(Si.sub.1-yGe.sub.y(C)), a strained QW channel layer formed of
germanium on the lower QW layer, and an upper QW barrier layer on
the strained QW channel layer formed of Si.sub.1-zGe.sub.z(C).
Other embodiments are described and claimed.
Inventors: |
Chui; Chi On; (Los Angeles,
CA) ; Majhi; Prashant; (Austin, TX) ; Tsai;
Wilman; (Saratoga, CA) ; Kavalieros; Jack T.;
(Portland, OR) |
Correspondence
Address: |
TROP PRUNER & HU, PC
1616 S. VOSS ROAD, SUITE 750
HOUSTON
TX
77057-2631
US
|
Family ID: |
39792645 |
Appl. No.: |
11/728890 |
Filed: |
March 27, 2007 |
Current U.S.
Class: |
257/14 ;
438/400 |
Current CPC
Class: |
H01L 29/66431 20130101;
H01L 29/155 20130101; H01L 29/165 20130101; H01L 29/7782
20130101 |
Class at
Publication: |
257/14 ;
438/400 |
International
Class: |
H01L 29/02 20060101
H01L029/02 |
Claims
1. An apparatus comprising: a silicon (Si) substrate; a first
buffer layer formed of silicon germanium tin (SiGe(Sn)) on the Si
substrate; a barrier layer on the first buffer layer, the barrier
layer comprising silicon germanium (Si.sub.1-xGe.sub.x); and a
quantum well (QW) layer including: a lower QW barrier layer on the
barrier layer, the lower QW barrier layer formed of silicon
germanium carbon (Si.sub.1-yGe.sub.y(C)); a strained QW channel
layer formed of germanium on the lower QW layer; and an upper QW
barrier layer on the strained QW channel layer formed of
Si.sub.1-zGe.sub.z(C).
2. The apparatus of claim 1, wherein the first buffer layer is
formed of Si.sub.1-xGe.sub.x at an interface with the Si substrate
and is graded with increasing concentration of germanium (Ge) to
obtain a Ge concentration of at least approximately 80%.
3. The apparatus of claim 2, wherein x is greater than y.
4. The apparatus of claim 3, wherein z is less than or equal to
y.
5. The apparatus of claim 2, wherein the lower and upper QW barrier
layers are tensile strained.
6. The apparatus of claim 5, where the strained QW channel layer is
compressive strained.
7. The apparatus of claim 2, further comprising: a spacer layer
formed over the quantum well layer; a delta-doped layer formed over
the spacer layer; and an upper barrier layer formed over the
delta-doped layer, the upper barrier layer formed of
Si.sub.1-xGe.sub.x.
8. The apparatus of claim 7, wherein the apparatus comprises a high
electron mobility transistor (HEMT) or high hole mobility
transistor (HHMT), wherein the quantum well layer comprises a
channel of the HEMT or HHMT.
9. A method comprising: forming a first buffer layer of silicon
germanium tin (SiGe(Sn)) on a silicon (Si) substrate; forming a
barrier layer on the first buffer layer, the barrier layer
comprising silicon germanium (Si.sub.1-xGe.sub.x); and forming a
quantum well (QW) layer on the barrier layer including a lower QW
barrier layer formed of silicon germanium carbon
(Si.sub.1-yGe.sub.y(C)), a strained QW channel layer formed of
germanium on the lower QW layer, and an upper QW barrier layer on
the strained QW channel layer formed of Si.sub.1-zGe.sub.z(C).
10. The method of claim 9, wherein the first buffer layer is formed
of Si.sub.1-xGe.sub.x at an interface with the Si substrate and is
graded with increasing concentration of germanium (Ge) to obtain a
Ge concentration of at least approximately 80%.
11. The method of claim 10, wherein x is greater than y and z is
less than or equal to y.
12. The method of claim 11, wherein the lower and upper QW barrier
layers are tensile strained.
13. The method of claim 12, wherein the strained QW channel layer
is compressive strained.
14. The method of claim 13, further comprising forming a high
electron mobility transistor (HEMT) or a high hole mobility
transistor (HHMT), wherein the quantum well layer comprises a
channel of the HEMT or HHMT.
Description
BACKGROUND
[0001] A variety of electronic and optoelectronic devices can be
enabled by developing thin film relaxed lattice constant III-V
semiconductors on elemental silicon (Si) substrates. Surface layers
capable of achieving the performance advantages of III-V materials
may host a variety of high performance electronic devices such as
complementary metal oxide semiconductor (CMOS) and quantum well
(QW) transistors fabricated from extreme high mobility materials
such as, but not limited to, indium antimonide (InSb), indium
gallium arsenide (InGaAs) and indium arsenide (InAs).
[0002] Other transistors are formed using Group IV materials such
as germanium (Ge). However, such transistors have poor n-channel
properties, i.e., surface channel properties are poor due to high
interface state density near conduction band edges and these
devices are unable to form quantum wells. Furthermore, such Ge
transistors typically cannot be integrated into
complementary-channel metal oxide semiconductor field effect
transistors (MOSFETs) using standard complementary CMOS process
flows.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 is a cross section view of a device structure in
accordance with an embodiment of the present invention.
[0004] FIG. 2 is a band diagram of a structure in accordance with
an embodiment of the present invention.
[0005] FIG. 3 is a flow diagram of a method in accordance with an
embodiment of the present invention.
DETAILED DESCRIPTION
[0006] In various embodiments, Type I heterostructure channels may
be formed in Group IV materials to form CMOS devices. While the
scope of the present invention is not limited in this regard, in
some implementations a channel may be formed including a Group IV
material such as germanium (Ge). For example, in some embodiments a
silicon germanium carbon (SiGe(C))-based alloy may be used in a
channel region of MOSFET devices. Note that the element in the
internal parenthesis (i.e., carbon) is optional. The higher bandgap
of SiGe(C) and especially positive band offsets for both conduction
and valence band edges allows formation of buried channel QWs for
both n-channel MOSFETs (NMOS) and p-channel MOSFETs (PMOS).
Accordingly, conventional CMOS processing to complete a gate stack
may be implemented. Furthermore, presence of a SiGe(C) layer may
also provide higher thermal stability for a stack and minimized
dopant diffusion for ultra-shallow junctions.
[0007] Accordingly, in various embodiments nMOSFETs and pMOSFETs
may be formed on common Ge channels. Such devices may be realized
as transport in a high mobility channel may be possible with
modulation doping. Furthermore, reduced short channel effect (SCE)
within a QW may be realized by raising the bandgap and quantum
confinement. Furthermore, a sub-band may be populated with lower
effective mass. Still further, n-type dopant diffusions may be
reduced to form ultra-shallow junctions and furthermore,
compressive strain may be induced in a Ge layer to increase
effective electron mass, which improves PMOS performance and lowers
electron and hole mobility mismatch.
[0008] Referring now to FIG. 1, shown is a cross section view of a
device structure 10 in accordance with an embodiment of the present
invention. As shown in FIG. 1, structure 10 may be used to form
NMOS or PMOS devices on a substrate 30. In various embodiments,
substrate 30 may be a high resistivity n or p-type (100)
off-oriented Si substrate, although the scope of the present
invention is not limited in this regard.
[0009] As shown in FIG. 1, next a buffer layer 34 may be formed on
substrate 30. In various embodiments, buffer layer 34 may be a
graded silicon germanium tin (SiGe(Sn)) layer. Note again that the
element in the internal parenthesis (i.e., tin) is optional. Buffer
layer 34 may be formed via an ultra-high vacuum chemical vapor
deposition (UHVCVD) or reduced pressure chemical vapor deposition
(RPCVD), or another such process. In some embodiments, buffer layer
34 may be formed in a graded manner with increasing Ge
concentration from its interface with underlying substrate 30. As
an example, the buffer ramp rates may be in the range of
approximately 10-20% per micron of SiGe growth. In this way,
increasing Ge concentration is realized such that at a top portion,
the layer may have a Ge concentration of at least approximately
80%, in some embodiments. Alternately, buffer layer 34 may be
achieved by wafer bonding or an equivalent process. In still other
embodiments, buffer layer 34 may be a buried oxide. In some
embodiments, the thickness of buffer layer 34 may vary depending on
deposition method. For grading it may be 10 microns; for bonding
onto a buried oxide, the oxide could be of any thickness (e.g.,
100-1000 angstroms (.ANG.)).
[0010] A lower barrier layer 38 may be formed on buffer layer 34.
Lower barrier layer 38 may be formed of a higher bandgap material
than a quantum well layer to be formed thereon. Lower barrier layer
38 may be formed of silicon germanium (Si.sub.1-xGe.sub.x), in one
embodiment. Lower barrier layer 38 may be of sufficient thickness
to provide a potential barrier to charge carriers in the transistor
stack. In one embodiment, lower barrier layer 38 may have a
thickness of between approximately 100 .ANG.-250 .ANG.. In other
embodiments, lower barrier layer 38 may be between approximately
2-5 microns (.mu.m).
[0011] Referring still to FIG. 1, a quantum well layer 40 may be
formed over lower barrier layer 38. Quantum well layer 40 may be
formed of multiple materials having both smaller and larger
bandgaps than that of lower barrier layer 38. In one embodiment,
quantum well layer 40 may be formed of a lower QW barrier layer 41,
a QW channel layer 42, and an upper QW barrier layer 43. In one
embodiment, lower QW barrier layer 41 may be formed by a
pseudomorphic growth of a tensile strained silicon germanium carbon
(Si.sub.1-yGe.sub.y(C)) layer, where the germanium content (y) may
be lower than the germanium content (x) of barrier layer 38. Above
this lower QW barrier layer 41, a compressive strained germanium
layer may be pseudomorphically grown to form QW channel layer 42.
In turn, over QW channel layer 42 an upper QW barrier layer 43,
which may be formed of silicon germanium carbon
(Si.sub.1-zGe.sub.z(C)), whose Ge content (z), may be equal to y or
lower, may be formed. Quantum well layer 40 may be of sufficient
thickness to provide adequate channel conductance. In some
embodiments, quantum well layer 40 may be between approximately
10-50 nanometers (nm). Quantum well layer 40 may provide high
electron mobility and velocity for NMOS devices, and also may
provide high hole mobility and velocity for PMOS devices, both
compared to a Si-based device. In other embodiments, a quantum well
in accordance with an embodiment may be formed on a high Ge content
silicon germanium on insulator substrate. Yet in other embodiments
a quantum well may be grown on a strain compensated silicon
germanium tin allow buffer to favor the tensile strain introduction
to the QW barrier layers.
[0012] As further shown in FIG. 1, a spacer layer 44 optionally may
be formed over quantum well layer 40 to provide tensile strain.
Spacer layer 44 may be a Si.sub.1-xGe.sub.x spacer layer. Spacer
layer 44 may provide for carrier confinement and remote ion
scattering reduction as well as reduced interaction between a
doping layer and a two dimensional electron gas (2DEG) formed
inside the channel (i.e., the channel of quantum well layer 40). In
various embodiments, spacer layer 44 may be approximately 20 .ANG.
to 30 .ANG. thick.
[0013] A gate stack may then be formed above this spacer layer 44.
A doping layer may be formed over spacer layer 44. Doping layer 46
may be delta-doped, modulation doped and/or combinations thereof.
For example, in one embodiment doping layer 46 may be a modulation
delta-doped layer having a thickness of approximately 3 .ANG.-5
.ANG.. For an NMOS device, doping may be implemented using arsenic
(As) or phosphorus (P) impurities. As for a PMOS device, doping may
be boron (B).
[0014] Referring still to FIG. 1, an upper barrier layer 48 may be
formed over doping layer 46 to complete the device stack or layer.
In one embodiment, barrier layer 48 may be an Si.sub.1-xGe.sub.x
barrier layer. Barrier layer 48 may have a thickness of between
approximately 50 .ANG.-500 .ANG., and may be a Schottky barrier
layer for gate control.
[0015] As further shown in FIG. 1, a contact layer 52 may be
present to act as a contact layer to provide source and drain
contacts with low contact resistance and may be formed of
Si.sub.1-xGe.sub.x, in various embodiments. For an NMOS device,
contact layer 52 may be n+doped, while for a PMOS device, contact
layer 52 may be p+doped. Contact layer 52 may be between
approximately 30 .ANG.-300 .ANG. thick.
[0016] While not shown in FIG. 1, a fully completed device may
further include source and drain electrodes. Furthermore, a
dielectric material may be formed on barrier layer 48 over which a
gate electrode may be formed. Note that a gate recess etch may be
performed within upper barrier layer 48 to form a gate recess on
which the dielectric layer and gate electrode may be formed. Thus a
Schottky junction may be formed through which a gate electrode may
control quantum well layer 40.
[0017] Accordingly, in various embodiments devices may be formed
using a high electron mobility material to form high electron
mobility transistors (HEMTs) or high hole mobility transistors
(HHMTs) having high speed and low power consumption. Such devices
may have dimensions less than approximately 50 nm with a switching
frequency of approximately 562 gigahertz (GHz). Such devices may be
able to operate at between approximately 0.5-1.0 volts without
significant reduction of drive current. Furthermore, embodiments
may provide lower gate delay at a gate length than a silicon based
device.
[0018] Referring now to FIG. 2, shown is a band diagram of a
structure in accordance with an embodiment of the present
invention. As shown in FIG. 2, the band diagram illustrates, via
the top line a conduction band (i.e., E.sub.C) and via the lower
line a valence band (i.e., E.sub.V). Beginning at the left-hand
side of FIG. 2, the lower barrier layer, which may be silicon
germanium (i.e., Si.sub.1-xGe.sub.x) may be formed. Over this
layer, a lower QW barrier layer, which may be formed of tensile
strain silicon germanium carbon (Si.sub.1-yGe.sub.y(C)) may be
formed. As shown, this barrier layer has a higher bandgap than the
buffer layer over which it is formed. In turn, the compressive
strain germanium QW channel layer may be formed which has a smaller
bandgap than both the buffer and barrier layers. Over the QW
channel layer, an upper tensile strained silicon germanium carbon
(Si.sub.1-zGe.sub.z(C)) barrier layer may be formed that may, in
some embodiments have the same bandgap as the lower QW barrier
layer. Then, as shown in FIG. 2, an optional tensile strained
silicon layer may be formed over the upper QW barrier layer which
has a higher bandgap than the other layers.
[0019] Referring now to FIG. 3, shown is a flow diagram of a method
in accordance with an embodiment of the present invention. As shown
in FIG. 3, method 100 may begin by forming a buffer layer over a Si
substrate (block 110). As described above, in some embodiments the
buffer layer may be graded SiGe(Sn). Next, a lower barrier layer,
e.g., of Si.sub.1-xGe.sub.x, may be formed (block 120). Next, a QW
layer, which may be formed of a tensile strain
Si.sub.1-yGe.sub.y(C) lower QW barrier layer, a compressive strain
Ge QW channel layer, and a tensile strain Si.sub.1-xGe.sub.x(C)
upper QW barrier layer, is formed over the lower barrier layer
(block 130). Then a spacer layer may be formed over the quantum
well (QW) channel layer (block 140). Next, a modulation delta-doped
layer may be formed (block 150). To complete the device stack, an
upper barrier layer may be formed over the doped layer (block 160).
Then a contact layer of Si.sub.1-xGe.sub.x may be formed over the
barrier layer (block 170). Of course, from this contact layer,
source and drains of a device may be formed, and further a gate
electrode may be formed on a dielectric layer formed over the
contact layer. While shown with this particular implementation in
the embodiment of FIG. 3, the scope of the present invention is not
limited in this regard.
[0020] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
* * * * *