U.S. patent application number 12/110009 was filed with the patent office on 2008-08-21 for barrier for use in 3-d integration of circuits.
This patent application is currently assigned to Freescale Semiconductor, Inc.. Invention is credited to VARUGHESE MATHEW, LYNNE M. MICHAELSON, SCOTT K. POZDER.
Application Number | 20080197497 12/110009 |
Document ID | / |
Family ID | 38559646 |
Filed Date | 2008-08-21 |
United States Patent
Application |
20080197497 |
Kind Code |
A1 |
POZDER; SCOTT K. ; et
al. |
August 21, 2008 |
BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS
Abstract
A method for forming a semiconductor device includes providing a
first integrated circuit having a landing pad and attaching a
second integrated circuit to the first integrated circuit using at
least one bonding layer. The second integrated circuit has an
inter-circuit trace, the inter-circuit trace has an inter-circuit
trace opening. The method further includes forming an opening
through the second integrated circuit, the opening extending
through the inter-circuit trace opening, forming a selective
barrier on exposed portions of the inter-circuit trace in the
opening, extending the opening through the at least one bonding
layer to the landing pad, and filling the opening with a conductive
fill material. The selective barrier layer comprises at least one
of cobalt or nickel, and the conductive fill material electrically
connects the inter-circuit trace and the landing pad.
Inventors: |
POZDER; SCOTT K.; (Austin,
TX) ; MICHAELSON; LYNNE M.; (Providence, RI) ;
MATHEW; VARUGHESE; (Austin, TX) |
Correspondence
Address: |
FREESCALE SEMICONDUCTOR, INC.;LAW DEPARTMENT
7700 WEST PARMER LANE MD:TX32/PL02
AUSTIN
TX
78729
US
|
Assignee: |
Freescale Semiconductor,
Inc.
Austin
TX
|
Family ID: |
38559646 |
Appl. No.: |
12/110009 |
Filed: |
April 25, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11278042 |
Mar 30, 2006 |
7378339 |
|
|
12110009 |
|
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Current U.S.
Class: |
257/751 ;
257/E23.145; 257/E27.026 |
Current CPC
Class: |
H01L 2924/01042
20130101; H01L 24/92 20130101; H01L 2225/06541 20130101; H01L
2924/01074 20130101; H01L 2225/06513 20130101; H01L 2924/14
20130101; H01L 2924/01006 20130101; H01L 25/50 20130101; H01L
21/76805 20130101; H01L 2224/9202 20130101; H01L 2924/01046
20130101; H01L 2224/83191 20130101; H01L 27/0688 20130101; H01L
2924/01073 20130101; H01L 2924/14 20130101; H01L 24/94 20130101;
H01L 2924/01075 20130101; H01L 21/76898 20130101; H01L 2924/01019
20130101; H01L 2924/01078 20130101; H01L 23/481 20130101; H01L
2924/01033 20130101; H01L 2924/01029 20130101; H01L 2924/00
20130101; H01L 2924/01005 20130101 |
Class at
Publication: |
257/751 ;
257/E23.145 |
International
Class: |
H01L 23/522 20060101
H01L023/522 |
Claims
1-17. (canceled)
18. A semiconductor device, comprising: a first integrated circuit
having a landing feature and at least one bonding layer over the
landing feature; a second integrated circuit having an
inter-circuit trace and at least one bonding layer over the
inter-circuit trace, wherein the at least one bonding layer of the
second integrated circuit is attached to the at least one bonding
layer of the first integrated circuit; a conductive interconnect
extending through the second integrated circuit, through an opening
in the inter-circuit trace, through the at least one bonding layer
of the second integrated circuit, and through the at least one
bonding layer of the first integrated circuit to the landing
feature, the conductive interconnect electrically connecting the
inter-circuit trace to the landing feature; and a barrier layer
adjacent the inter-circuit trace comprising at least one material
selected from a group consisting of cobalt and nickel and located
in the opening of the inter-circuit trace, between the
inter-circuit trace and the conductive interconnect.
19. The semiconductor device of claim 18, further comprising: a
dielectric material at least partially surrounding the
inter-circuit trace; and a second barrier layer adjacent the
inter-circuit trace, wherein the second barrier layer is conductive
and different from the first barrier layer, and the second layer is
located between the dielectric material and the inter-circuit
trace.
20. The semiconductor device of claim 18, further comprising a
second barrier layer adjacent the landing feature and located
between the landing feature and the conductive interconnect,
wherein the landing feature comprises at least one material
selected from a group consisting of cobalt and nickel.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates in general to 3-D integration of
circuits and more specifically to a barrier for use in 3-D
integration of circuits.
[0003] 2. Description of the Related Art
[0004] Traditionally, 3-D integration of circuits is achieved using
face-to-face bonding of wafers, such as acceptor wafers and donor
wafers, or dies. Acceptor wafer is typically the bottom wafer and
donor wafer is typically the top wafer. Interconnects in the bonded
wafers or dies are connected using various techniques, such as
stitch vias. Formation of stitch vias, which are typically formed
on the backside of a donor wafer, is, however, time consuming and
requires additional steps for achieving 3-D integration of wafers
or dies. In particular, for example, formation of stitch vias
requires two inter-wafer vias having differing lengths that are
linked on the backside of the donor wafer.
[0005] Additionally, etching of inter-wafer vias can cause several
problems for etch processing. For example, etching of such
inter-wafer vias in low-K dielectric wafers requires etching
through multiple types of dielectric materials, such as silicon
nitride, silicon carbon-nitride, silicon-oxide, and SiCOH
containing low-K dielectrics. This in turn requires a wide range of
etch processes, such as both physical and chemical etch processes.
Certain physical and chemical etch processes can redistribute the
copper into the dielectric layers. This problem, for example,
especially occurs when inter-wafer connects are used as embedded
etch masks.
[0006] Thus, there is a need for improved 3-D integration of
circuits.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The present invention may be better understood, and its
numerous objects, features, and advantages made apparent to those
skilled in the art by referencing the accompanying drawings.
[0008] FIG. 1 is a partial side view of one embodiment of an
exemplary acceptor wafer during a processing stage, consistent with
one embodiment of the invention;
[0009] FIG. 2 is a partial side view of one embodiment of an
exemplary acceptor wafer, consistent with one embodiment of the
invention;
[0010] FIG. 3 is a partial side view of one embodiment of a
semiconductor device during a processing stage, consistent with one
embodiment of the invention;
[0011] FIG. 4 is a partial side view of one embodiment of a
semiconductor device during a processing stage, consistent with one
embodiment of the invention;
[0012] FIG. 5 is a partial side view of one embodiment of a
semiconductor device during a processing stage, consistent with one
embodiment of the invention;
[0013] FIG. 6 is a partial side view of one embodiment of a
semiconductor device during a processing stage, consistent with one
embodiment of the invention;
[0014] FIG. 7 is a partial side view of one embodiment of a
semiconductor device during a processing stage, consistent with one
embodiment of the invention;
[0015] FIG. 8 is a partial side view of one embodiment of a
semiconductor device during a processing stage, consistent with one
embodiment of the invention; and
[0016] FIG. 9 is a partial side view of one embodiment of a
semiconductor device during a processing stage, consistent with one
embodiment of the invention.
[0017] Skilled artisans appreciate that elements in the figures are
illustrated for simplicity and clarity and have not necessarily
been drawn to scale. For example, the dimensions of some of the
elements in the figures may be exaggerated relative to other
elements to help improve the understanding of the embodiments of
the present invention.
DETAILED DESCRIPTION
[0018] The following sets forth a detailed description of a mode
for carrying out the invention. The description is intended to be
illustrative of the invention and should not be taken to be
limiting.
[0019] In one aspect, a method for forming a semiconductor device
is provided. The method includes providing a first integrated
circuit having a landing pad and attaching a second integrated
circuit to the first integrated circuit using at least one bonding
layer. The second integrated circuit has an inter-circuit trace,
the inter-circuit trace has an inter-circuit trace opening. The
method further includes forming an opening through the second
integrated circuit, the opening extending through the inter-circuit
trace opening, forming a selective barrier on exposed portions of
the inter-circuit trace in the opening, extending the opening
through the at least one bonding layer to the landing pad, and
filling the opening with a conductive fill material. The selective
barrier layer comprises at least one of cobalt or nickel, and the
conductive fill material electrically connects the inter-circuit
trace and the landing pad.
[0020] In another aspect, a method for forming a semiconductor
device is provided. The method includes providing a first
integrated circuit having a landing pad. The method further
includes attaching a second integrated circuit to the first
integrated circuit using at least one bonding layer, the second
integrated circuit having an inter-circuit trace, the inter-circuit
trace having an opening. The method further includes forming an
opening through the second integrated circuit, the opening
extending through the inter-circuit trace opening. The method
further includes forming a selective barrier on exposed portions of
the inter-circuit trace in the opening, the selective barrier
comprising at least one material selected from a group consisting
of cobalt and nickel. The method further includes extending the
opening through the at least one bonding layer to the landing pad.
The method further includes after extending the opening, filling
the opening with a conductive fill material, wherein the conductive
fill is electrically connected to the inter-circuit trace and the
landing pad.
[0021] In yet another aspect, a semiconductor device including a
first integrated circuit having a landing pad and at least one
bonding layer over the landing pad, is provided. The semiconductor
device further includes a second integrated circuit having an
inter-circuit trace and at least one bonding layer over the
inter-circuit trace, wherein the at least one bonding layer of the
second integrated circuit is attached to the at least one bonding
layer of the first integrated circuit. The semiconductor device
further includes a conductive interconnect extending through the
second integrated circuit, through an opening in the inter-circuit
trace, through the at least one bonding layer of the second
integrated circuit, and through the at least one bonding layer of
the first integrated circuit to the landing pad, the conductive
interconnect electrically connecting the inter-circuit trace to the
landing pad. The semiconductor device further includes a barrier
layer adjacent the inter-circuit trace comprising at least one
material selected from a group consisting of cobalt and nickel and
located in the opening of the inter-circuit trace, between the
inter-circuit trace and the conductive interconnect.
[0022] FIG. 1 is a partial side view of one embodiment of an
acceptor wafer during a processing stage, consistent with one
embodiment of the invention. Acceptor wafer 10 may include an
interconnect layer 12, an active layer 14, and a semiconductor
layer 16. Interconnect layer 12 may include interconnect 20 and via
22. A landing feature, such as a landing pad 18 may be formed as
part of interconnect layer 12, as well. By way of example, a
conductive barrier 24 having cobalt or nickel may be formed on top
of landing pads. Although FIG. 1 shows only one of each of
interconnect layer 12, active layer 14, and semiconductor layer 16,
acceptor wafer 10 may include additional such layers. Further, as
shown in FIG. 2, a bonding layer 26 may be formed on top of
interconnect layer 12.
[0023] Referring now to FIG. 3, a donor wafer 30 may be bonded
face-to-face with acceptor wafer 10. Donor wafer 30 may include
similar layers as acceptor wafer 10. By way of example, donor wafer
30 may include an interconnect layer 32, an active layer 34, and a
semiconductor layer 36. Interconnect layer 32 may include an
inter-wafer connect trace 38 with an opening 40 formed in
inter-wafer connect trace 38. Inter-wafer connect trace 38 may look
like a line with a hole (opening 40) in it. Inter-wafer connect
trace 38 may be formed using copper or any other suitable
conductive material. Although described with respect to a wafer,
inter-wafer connect trace 38 may act as an inter-circuit trace in a
wafer or a die. Donor wafer 30 may have an etch-stop layer 50
formed on interconnect layer 32. A bonding layer 42 may be formed
over etch-stop layer 50. Although FIG. 3 shows separately formed
bonding layer 42 and etch-stop layer 50, etch-stop layer may be
formed as part of bonding layer 42. Alternatively, bonding layer 42
may act as an etch-stop layer. In addition, only one of acceptor
wafer 10 and donor wafer 30 may have a bonding layer.
[0024] Further, as shown in FIG. 3, active layer 34 and
semiconductor layer 36 may include align-keys 46 and 48, which may
be used to find features in interconnect layer 32, for example. In
particular, align-keys 46 and 48 may be used to align patterns on
the backside of donor wafer 30, which is the top surface of the
bonded wafer. Although FIG. 3 shows align-keys 46 and 48, these may
not be necessary in a SOI wafer, where features may be visible
through active layer 34 and semiconductor layer 36. Isolation
windows 47 and 49 may be formed in active layer 34 and
semiconductor layer 36 of donor wafer 30. Isolation windows 47 and
49 may be used to isolate conductive fill material formed in vias,
as explained further with respect to FIGS. 8 and 9. Isolation
windows 47 and 49 may contain an insulating material, such as an
oxide. Although FIG. 3 shows only one of each of interconnect layer
32, active layer 34, and semiconductor layer 36, donor wafer 30 may
include additional such layers. Additionally, although FIG. 3 shows
face-to-face bonding of acceptor wafer 10 and donor wafer 30, they
may be bonded in other configurations, as well.
[0025] Referring still to FIG. 3, a barrier layer 52 may be formed
on at least top and side surfaces of inter-wafer connect trace 38.
Barrier layer 52 may be formed using tantalum, titanium, tungsten
or alloys thereof. Although FIG. 3 does not show barrier layer 52
formed over other interconnect traces (20, for example), barrier
layer 52 may be formed over other interconnect traces in acceptor
wafer 10 and donor wafer 30, as well.
[0026] Referring now to FIG. 4, semiconductor layer 36 of donor
wafer 30 may be thinned using mechanical-chemical or
chemical-mechanical processes to form thinned semiconductor layer
44. Next, as shown in FIG. 5, a patterned masking layer 54 may be
formed over thinned semiconductor layer 44. Next, as shown in FIG.
6, by etching and using etch-stop layer 50, an opening 58 extending
through opening 40 (shown in FIG. 5) in donor wafer 30 may be
formed. Although etch-stop layer 50 is shown in FIG. 4 as being
directly adjacent to bonding layer 42, etch-stop layer 50 may be
placed at a different location in donor wafer 30. For example,
etch-stop layer 50 may be placed directly under inter-wafer connect
trace 38, if interconnect layer 32 did not have inter-wafer connect
trace 39 or if inter-wafer connect trace 39 were at the same level
as inter-wafer connect trace 38. Thus, by way of example, the
etch-stop layer may always be positioned directly below the
inter-wafer connect trace of an interconnect layer, such as
interconnect layer 32, that is closest to the bonding surface of
the wafer. Additional openings, as necessary, may be formed. For
example, FIG. 6 shows an additional opening 56. Openings 56 and 58
may expose portions of inter-wafer connect trace 38 and 39. In
particular, the etching process may etch away parts of barrier
layer 52 to expose portions of inter-wafer connect trace 38 and
39.
[0027] Next, as shown in FIG. 7, a barrier (60, 62) may be
selectively formed on exposed portions of inter-wafer connect trace
38 and 39. In one embodiment, barrier (60, 62) may be formed only
on the exposed portions of inter-wafer connect trace 38 and 39. In
one embodiment, prior to forming barrier (60, 62) exposed portions
of inter-wafer connect trace 38 and 39 may be treated. Such
treatment may include completely or partially removing barrier
layer 52 or treating the exposed portions with catalytic materials,
such as palladium or platinum. Exposed portions of inter-wafer
connect trace 38 and 39 may result in the trace material, such as
copper being exposed. Barrier (60, 62) may be formed directly on
the exposed copper, for example. Barrier (60, 62) may be cobalt or
nickel containing material, such as cobalt-tungsten-boron,
cobalt-tungsten-phosphorous, cobalt-molybdenum-boron,
cobalt-molybdenum-phosphorous, cobalt-rhenium-boron,
cobalt-rhenium-phosphorous, nickel-tungsten-boron,
nickel-tungsten-phosphorous, nickel-molybdenum-boron,
nickel-molybdenum-phosphorous, nickel-rhenium-boron,
nickel-rhenium-phosphorous, or it may be any other suitable etch
resistant material. In another embodiment, exposed portions of
inter-wafer connect trace 38 and 39 may still have a portion of
barrier layer 52 with at least some of the copper exposed. Exposed
portions of inter-wafer connect trace 38 and 39 may be used to grow
the barrier layer. Exposed portions of inter-wafer connect trace 38
and 39 may first be treated using palladium and/or platinum, prior
to growing the barrier layer.
[0028] Next, as shown in FIG. 8, using a second etch process,
opening 58 may be extended to a landing pad (e.g., a landing pad
similar to landing pad 18). Similarly, as part of the second etch
process, opening 56 may be extended to another landing pad.
Although FIG. 8 shows openings 56 and 58 extending to landing pads,
these openings may extend to any metal line of acceptor wafer 10 to
make appropriate interconnections.
[0029] Referring now to FIG. 9, conductive fill material 64 and 66
may be filled into openings 58 and 56, respectively, for
electrically interconnecting acceptor wafer 10 and donor wafer 30.
Conductive fill material 64 and 66 may be filled using processes,
such as electroplating. Isolation windows 47 and 49 may keep active
layer 34 and thinned semiconductor layer 44 electrically isolated
from conductive fill material. Although not shown, a liner and seed
layers may be formed in openings 56 and 58 prior to filling
conductive fill material 64 and 66 into these openings. These
layers may be formed using a chemical vapor deposition or a
physical vapor deposition process. When a physical vapor deposition
process along with a re-sputter process is used, the slight ledge
formed by selective barrier 60 results in a better bottom sidewall
coverage of liner and seed layers. Additionally, although not
shown, additional steps may be performed subsequently to create
singulated integrated circuits, for example.
[0030] In the foregoing specification, the invention has been
described with reference to specific embodiments. However, one of
ordinary skill in the art appreciates that various modifications
and changes can be made without departing from the scope of the
present invention as set forth in the claims below. Accordingly,
the specification and figures are to be regarded in an illustrative
rather than a restrictive sense, and all such modifications are
intended to be included within the scope of present invention.
[0031] Benefits, other advantages, and solutions to problems have
been described above with regard to specific embodiments. However,
the benefits, advantages, solutions to problems, and any element(s)
that may cause any benefit, advantage, or solution to occur or
become more pronounced are not to be construed as a critical,
required, or essential feature or element of any or all the claims.
As used herein, the terms "comprises," "comprising," or any other
variation thereof, are intended to cover a non-exclusive inclusion,
such that a process, method, article, or apparatus that comprises a
list of elements does not include only those elements but may
include other elements not expressly listed or inherent to such
process, method, article, or apparatus.
* * * * *