U.S. patent application number 12/109292 was filed with the patent office on 2008-08-21 for method of forming double gate dielectric layers and semiconductor device having the same.
This patent application is currently assigned to DONGBU ELECTRONICS CO., LTD.. Invention is credited to Yong Soo Ahn.
Application Number | 20080197427 12/109292 |
Document ID | / |
Family ID | 36610459 |
Filed Date | 2008-08-21 |
United States Patent
Application |
20080197427 |
Kind Code |
A1 |
Ahn; Yong Soo |
August 21, 2008 |
METHOD OF FORMING DOUBLE GATE DIELECTRIC LAYERS AND SEMICONDUCTOR
DEVICE HAVING THE SAME
Abstract
A method of forming double gate dielectric layers composed of an
underlying oxide layer and an overlying oxy-nitride layer is
provided to prevent degradation of gate dielectric properties due
to plasma-induced charges. In the method, the oxide layer is
thermally grown on a silicon substrate under oxygen gas atmosphere
to have a first thickness, and then the oxy-nitride layer is
thermally grown on the oxide layer under nitrogen monoxide gas
atmosphere to have a second thickness smaller than the first
thickness. The substrate may have a high voltage area and a low
voltage area, and the oxide layer may be partially etched in the
low voltage area so as to have a reduced thickness. The oxy-nitride
layer behaves like a barrier, blocking the inflow of the
plasma-induced charges.
Inventors: |
Ahn; Yong Soo; (Bucheon-si,
KR) |
Correspondence
Address: |
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER;LLP
901 NEW YORK AVENUE, NW
WASHINGTON
DC
20001-4413
US
|
Assignee: |
DONGBU ELECTRONICS CO.,
LTD.
Seoul
KR
|
Family ID: |
36610459 |
Appl. No.: |
12/109292 |
Filed: |
April 24, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11319531 |
Dec 29, 2005 |
7378319 |
|
|
12109292 |
|
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|
Current U.S.
Class: |
257/411 ;
257/E21.625; 257/E29.255; 257/E29.266 |
Current CPC
Class: |
H01L 21/28211 20130101;
H01L 21/28202 20130101; H01L 29/513 20130101; H01L 21/823462
20130101; H01L 29/518 20130101; H01L 29/7833 20130101 |
Class at
Publication: |
257/411 ;
257/E29.255 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 29, 2004 |
KR |
2004-0114679 |
Claims
1-6. (canceled)
7. A semiconductor device comprising: a silicon substrate having a
field region defining an active region, the silicon substrate
having a high voltage area and a low voltage area; source/drain
regions formed in the active region of the substrate, in each of
the high and low voltage areas; double gate dielectric layers
formed between the source/drain regions on the substrate, in each
of the high and low voltage areas, and including an underlying
oxide layer having a first thickness and an overlying oxy-nitride
layer having a second thickness smaller than the first thickness;
and a gate electrode formed on the double gate dielectric layers,
in each of the high and low voltage areas.
8. The device of claim 7, wherein a thickness of the double
dielectric layer in the high voltage area is different from a
thickness of the double dielectric layer in the low voltage
area.
9. The device of claim 7, wherein a thickness of the double
dielectric layer in the high voltage area is greater than a
thickness of the double dielectric layer in the low voltage
area.
10. The device of claim 8, wherein a thickness of the oxide layer
in the high voltage area is greater than a thickness of the oxide
layer in the low voltage area.
11. The device of claim 7, further comprising dielectric spacers
formed on sidewalls of the gate electrode.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This U.S. non-provisional application claims priority under
35 U.S.C. .sctn.119 from Korean Patent Application No. 2004-114679,
which was filed in the Korean Intellectual Property Office on Dec.
29, 2004, the contents of which are incorporated by reference
herein in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to semiconductor
technology and, more particularly, to a method of forming double
gate dielectric layers composed of an underlying oxide layer and an
overlying oxy-nitride layer, and a semiconductor device having
double gate dielectric layers.
[0004] 2. Description of the Related Art
[0005] A dramatic trend toward scaling down of a transistor in
integrated circuit chips continuously requires a much thinner gate
dielectric layer. The ultrathin gate dielectric layer may, however,
confront many problems to be solved. A decrease in gate oxide
integrity (GOI) property is one of such problems. This problem
related to GOI property may be caused by plasma-induced damage that
may often occur during several processes such as gate etch, metal
etch, via etch, and gap fill CVD that follow a gate oxidation
process.
[0006] In order to improve GOI property, an oxy-nitride layer has
been used for the gate dielectric layer. FIG. 1 shows, in a
cross-sectional view, a conventional semiconductor device having
the oxy-nitride gate dielectric layer.
[0007] Referring to FIG. 1, a field region 11 having STI (shallow
trench isolation) structure is formed in a silicon substrate 10 to
define an active region. A well region 12 is formed in the
substrate 10, and source/drain regions 15 having LDD (lightly doped
drain) structure are formed in the active region of the substrate
10. The oxy-nitride gate dielectric layer 13 is formed between the
source/drain regions 15 on the substrate 10, and further, a gate
electrode 14 is formed thereon.
[0008] Normally the oxy-nitride gate dielectric layer 13 is formed
using nitrogen monoxide (NO) gas during a typical gate oxidation
process. Such conventional method produces an oxy-nitride layer
within an oxide layer. However, this oxy-nitride layer may be
distributed with very poor uniformity, and further, nitrogen atoms
in the oxy-nitride layer may act as impurities that cause
degradation in GOI property. For example, with enough voltage
applied, plasma-induced charges trapped in the gate dielectric
layer 13 eventually succumb to the electrical pressure and thereby
electrons flow toward the p-type well region 12. Such a breakdown
voltage may be much lowered when there is a poorly uniform layer or
undesirable impurity in the gate dielectric layer.
[0009] FIG. 2 illustrates a breakdown phenomenon in the non-uniform
oxy-nitride gate dielectric layer. Referring to FIG. 2, electrons
20 induced by plasma are trapped in the gate dielectric layer 13
underneath the gate electrode 14 and then flow into the p-type well
12 at the breakdown voltage. Unfortunately, this phenomenon due to
plasma-induced charge may deteriorate characteristics of the
semiconductor device and also drop yield and reliability of the
device.
SUMMARY OF THE INVENTION
[0010] Exemplary, non-limiting embodiments of the present invention
provide a method of forming double gate dielectric layers so as to
prevent degradation of gate dielectric properties due to
plasma-induced charges and a semiconductor device having double
gate dielectric layers.
[0011] According to an exemplary embodiment of the present
invention, the method comprises thermally growing an oxide layer on
a silicon substrate under oxygen gas atmosphere to have a first
thickness, and thermally growing an oxy-nitride layer on the oxide
layer under nitrogen monoxide gas atmosphere to have a second
thickness smaller than the first thickness.
[0012] In the method, the substrate may have a high voltage area
and a low voltage area. Here, the method may further comprise,
after growing the oxide layer, the step of partially etching the
oxide layer in the low voltage area so as to have a reduced
thickness.
[0013] The first thickness of the oxide layer may be about
50.about.70 .ANG., and the second thickness of the oxy-nitride
layer may be about 5.about.15 .ANG.. Additionally, the reduced
thickness of the oxide layer may be about 20.about.30 .ANG..
[0014] According to another exemplary embodiment of the present
invention, the semiconductor device comprises a silicon substrate
having a field region defining an active region, source/drain
regions formed in the active region of the substrate, double gate
dielectric layers formed between the source/drain regions on the
substrate and including an underlying oxide layer having a first
thickness and an overlying oxy-nitride layer having a second
thickness smaller than the first thickness, and a gate electrode
formed on the double gate dielectric layers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a cross-sectional view showing a conventional
semiconductor device having an oxy-nitride gate dielectric
layer.
[0016] FIG. 2 illustrates a breakdown phenomenon in the non-uniform
oxy-nitride gate dielectric layer.
[0017] FIGS. 3A to 3C are cross-sectional views showing a method of
forming double gate dielectric layers of a semiconductor device in
accordance with an exemplary embodiment of the present
invention.
[0018] FIG. 4 is a cross-sectional view showing a semiconductor
device having double gate dielectric layers in accordance with
another exemplary embodiment of the present invention.
[0019] FIG. 5 illustrates plasma-induced charges blocked by the
double gate dielectric layers.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION
[0020] Exemplary, non-limiting embodiments of the present invention
will now be described more fully hereinafter with reference to the
accompanying drawings. This invention may, however, be embodied in
many different forms and should not be construed as limited to the
exemplary embodiments set forth herein. Rather, the disclosed
embodiments are provided so that this disclosure will be thorough
and complete, and will fully convey the scope of the invention to
those skilled in the art. The principles and features of this
invention may be employed in varied and numerous embodiments
without departing from the scope of the invention.
[0021] It is noted that well-known structures and processes are not
described or illustrated in detail to avoid obscuring the essence
of the present invention. It is also noted that the figures are not
drawn to scale.
[0022] FIGS. 3A to 3C are cross-sectional views showing a method of
forming double gate dielectric layers of a semiconductor device in
accordance with an exemplary embodiment of the present
invention.
[0023] Referring to FIG. 3A, an oxide layer 31 is formed on a
silicon substrate 30. The oxide layer 31 may be thermally grown to
a thickness of about 50.about.70 .ANG. under oxygen gas atmosphere
at a temperature of about 750.about.850.degree. C.
[0024] Next, referring to FIG. 3B, the oxide layer 31 is
selectively coated with a photoresist pattern 32. Specifically, the
photoresist pattern 32 covers only a first part 31a of the oxide
layer 31 and exposes a second part 31b of the oxide layer 31. The
first and second parts 31a and 31b of the oxide layer 31 correspond
to a high voltage area and a low voltage area, respectively. While
the photoresist pattern 32 masks the high voltage area, the low
voltage part 31b of the oxide layer 31 is partially etched to
reduce the thickness. Hence, the high voltage part 31a of the oxide
layer 31 maintains an initial thickness of about 50.about.70 .ANG.,
whereas the low voltage part 31b becomes thinner to a thickness of
about 20.about.30 .ANG.. Thereafter, the photoresist pattern 32 is
stripped.
[0025] Next, an oxy-nitride layer 33 is uniformly formed on the
oxide layer 31. The oxy-nitride layer 33 may be thermally grown to
a thickness of about 5.about.15 .ANG. under nitrogen monoxide gas
atmosphere at a temperature of about 750.about.850.degree. C.
Therefore, resultant double gate dielectric layers are composed of
the underlying oxide layer 31 and the overlying oxy-nitride layer
33. The whole thickness of the gate dielectric layers is about
55.about.85 .ANG. in the high voltage area and 25.about.45 .ANG. in
the low voltage area.
[0026] Next, normal subsequent processes are performed in sequence
to fabricate a semiconductor device. FIG. 4 shows, in a
cross-sectional view, the semiconductor device having double gate
dielectric layers in accordance with another exemplary embodiment
of the present invention.
[0027] Referring to FIG. 4, a silicon substrate 30 has a field
region 34 with STI (shallow trench isolation) structure defining an
active region. A well region 35 is formed in the substrate 30, and
source/drain regions 37 having LDD (lightly doped drain) structure
are formed in the active region of the substrate 3Q. The above
discussed double gate dielectric layers 31a (or 31b) and 33 are
formed between the source/drain regions 37 on the substrate 30.
Additionally, a gate electrode 36 is formed on the double gate
dielectric layers 31a (or 31b) and 33, and dielectric spacers 38
are formed on sidewalls of the gate electrode 36.
[0028] For clarity, illustrated structure represents only the high
voltage area or the low voltage area. However, the high and low
voltage areas have similar structures except for the thickness of
the double gate dielectric layers.
[0029] The double gate dielectric layers of the invention may be
effective in preventing degradation of gate dielectric properties
due to plasma-induced charges. FIG. 5 illustrates plasma-induced
charges blocked by the double gate dielectric layers.
[0030] Referring to FIG. 5, the oxy-nitride layer 33 that is formed
on the oxide layer 31a (or 31b) in a separate process may have
improved uniformity. In the subsequent processes; the oxy-nitride
layer 33 behaves like a barrier, blocking the inflow of the
plasma-induced charges 40. Therefore, the oxy-nitride layer 33 not
only prevents degradation of gate dielectric properties due to
plasma-induced charges, but also enhances characteristics, yield
and reliability of the device.
[0031] While this invention has been particularly shown and
described with reference to an exemplary embodiment thereof, it
will be understood by those skilled in the art that various changes
in form and details may be made therein without departing from the
spirit and scope of the invention as defined by the appended
claims.
* * * * *