U.S. patent application number 11/351696 was filed with the patent office on 2008-08-14 for symmetric charge pump replica bias detector.
This patent application is currently assigned to Douglas Sudjian. Invention is credited to David H. Shen, Douglas Sudjian.
Application Number | 20080191783 11/351696 |
Document ID | / |
Family ID | 36045559 |
Filed Date | 2008-08-14 |
United States Patent
Application |
20080191783 |
Kind Code |
A1 |
Sudjian; Douglas ; et
al. |
August 14, 2008 |
Symmetric charge pump replica bias detector
Abstract
A charge pump replica bias detector is disclosed which provides
a charge pump with a greater working output voltage range or larger
output compliance. A larger working range will provide a charge
pump with more symmetric source and sink currents than prior
designs with a reduction of the multiple frequency sideband levels
that occur in a voltage controlled oscillator of a phase-locked
loop synthesizer. Further improvements are the prevention of
disturbances of the loop filter voltage level due to unwanted
leakage currents in a charge pump that are dependent on the value
of loop filter voltage. Finally, by providing improved output
voltage compliance and limiting loop filter voltage disturbances
there are improvements in the reduction in reference frequency
feed-through, charge sharing and noise transient coupling and phase
noise in the phase-locked loop. Possible applications include but
are not limited to charge pump phase-locked loop designs for single
chip CMOS multi-band and multi-standard radio frequency transceiver
integrated circuits.
Inventors: |
Sudjian; Douglas; (Santa
Clara, CA) ; Shen; David H.; (Saratoga, CA) |
Correspondence
Address: |
FISH & RICHARDSON P.C.
P.O. BOX 1022
MINNEAPOLIS
MN
55440-1022
US
|
Assignee: |
Sudjian; Douglas
IRF Semiconductor, Inc.
|
Family ID: |
36045559 |
Appl. No.: |
11/351696 |
Filed: |
February 10, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10809033 |
Mar 25, 2004 |
7361220 |
|
|
11351696 |
|
|
|
|
60487614 |
Jul 17, 2003 |
|
|
|
Current U.S.
Class: |
327/536 |
Current CPC
Class: |
H03L 7/0896 20130101;
H03L 7/0895 20130101 |
Class at
Publication: |
327/536 |
International
Class: |
G05F 1/10 20060101
G05F001/10 |
Claims
1. A replica bias clamp detector that maximizes a charge pump's
output voltage compliance by monitoring and limiting the leakage
current in a charge pump circuit comprising: a voltage buffer
follower responsive to a charge pump circuit output voltage level
and providing a voltage output and current output; a voltage
comparator whose output signal limits a circuit's leakage current
by responding to an input voltage sensing level; a constant
discharging current source to establish a fixed dc input voltage
level for a comparator in the absence of charge pump leakage; an
inverter circuit whose output is responsive to a sensing input
voltage; a replica pull-up current source of an existing charge
pump circuit responsive to a charge pump output and providing a
charging leakage current path; and a transmission switch responsive
to the bi-directional flow of a current;
2. The replica bias clamp detector of claim 1 further comprising: a
second voltage comparator whose output signal limits a circuit's
leakage current by responding to a second input voltage sensing
level; a constant charging current source to establish a second
fixed dc input voltage level for a second comparator in the absence
of charge pump leakage; a second inverter circuit whose output is
responsive to a second sensing input voltage; a replica pull-down
current source of an existing charge pump circuit responsive to a
charge pump output and providing a discharge leakage current path;
and a second transmission switch responsive to the bi-directional
flow of a current.
3. The replica bias clamp detector claim 1 wherein the transmission
switch includes: a complimentary transmission gate coupled to the
replica pull-up current source and a leakage detection comparator
input and constant current source bias supply coupled between the
transmission gate and supply.
4. The replica bias clamp detector claim 2 wherein the second
transmission switch includes: a second complimentary transmission
gate coupled to the replica pull-down current source and a second
leakage detection comparator input and second constant current
source bias supply coupled between the second transmission gate and
ground.
5. The comparator of claim 1 whereby a constant discharging current
is used to establish a fixed dc input voltage level for an inverter
circuit whose output will change state responsive to an external
discharge current.
6. A second comparator of claim 2 whereby a constant charging
current is used to establish a fixed dc input voltage level for a
second inverter circuit whose output will change state responsive
to an external discharge current.
7. A method of monitoring and limiting a charge pump's reverse
leakage current that maximizes the charge pump's output voltage
compliance using a replica bias clamp detector comprising: a
voltage follower buffer responsive to a charge pump circuit output
voltage level and providing an output voltage and output current; a
replica pull-up current source that provides a reverse leakage
current responsive to a voltage follower buffer output voltage
level; a complimentary transmission gate switch coupled to the
pull-up current source and a leakage detection comparator input and
a pull-down constant current source bias supply coupled between the
complementary transmission gate and ground; a constant discharging
current source to establish a fixed dc input voltage sensing level
at the input of a comparator in the absence of charge pump leakage;
and a voltage comparator responsive to an input voltage sensing
level that controls transmission switch closure in a given charge
pump to limit leakage current.
8. The method of claim 6 further comprising: a replica pull-down
current source that provides a reverse leakage current responsive
to a voltage follower buffer output voltage and current levels; a
second complimentary transmission gate switch coupled to the
pull-down current source and a second leakage detection comparator
input and a pull-up constant current source bias supply coupled
between the complementary transmission gate and ground; a constant
charging current source to establish a fixed dc input voltage
sensing level at the input of a second comparator in the absence of
charge pump leakage coupled between the supply; and a second
voltage comparator responsive to an input voltage sensing level
that controls a second transmission switch closure in a given
charge pump to limit leakage current.
9. The method of claim 6 wherein the replica pull-up current source
provides; an accurate measure of reverse leakage current in an
existing charge pump circuit.
10. The method of claim 6 wherein the unity gain voltage buffer
source provides; an accurate measure of reverse leakage current in
existing charge pump circuit to a transmission switch coupled to
the pull-up current source and a second leakage detection
comparator input and a pull-down constant current source bias
supply coupled between the complementary transmission gate and
ground.
11. The method of claim 7 wherein the replica pull-down current
source provides; an accurate measure of reverse leakage current in
an existing charge pump circuit.
12. The method of claim 7 wherein the unity gain voltage buffer
source provides; an accurate measure of reverse leakage current in
existing charge pump circuit to a second transmission switch
coupled to the pull-down current source and a second leakage
detection comparator input and a pull-up constant current source
bias supply coupled between the complementary transmission gate and
ground.
Description
[0001] THIS APPLICATION IS BASED ON THE PROVISIONAL APPLICATION No.
60/487,614 FILED ON Jul. 17, 2003 and application Ser. No.
10/809,033 FILED ON Jul. 13, 2004
REFERENCES
[0002] [1] Chih-Ming Hung and Kenneth K. O, "A Fully integrated
1.5V 5.5 GHz CMOS Phase-Locked Loop", IEEE JSSC, Vol. 37, No. 4,
April 2002. [0003] [2] William Wilson, Un-Ku Moon, Kadaba R.
Lakshmikumar and Liang Dai "A Self-Calibrating Frequency
Synthesizer", IEEE JSSC, Vol. 35, No. 10, October 2000.
BACKGROUND
[0004] 1. Technical Field of Invention
[0005] The present invention relates to a replica bias detector and
circuit design used in a high efficiency symmetric CMOS charge pump
architecture that can be used in phase-locked loop (PLL) frequency
synthesizers. The PLL application examples include but are not
limited to radio frequency receivers and transmitters for all
wireless communication standards including cellular 2.5G/3G/4G
wireless communications, optical fiber communications, network
communications and storage systems.
[0006] 2. Background of the Invention and Discussion of Prior
Art
[0007] The growing demand for wireless communications has motivated
attempts to design radios that permit the integration of more
components onto a single chip. The recent advances in CMOS
semiconductor processing allow the integration of the radio
receiver and transmitter into a single chip radio frequency (RF)
transceiver to reduce cost, size and power consumption.
BACKGROUND OF THE INVENTION
Phase-Locked Loop
[0008] Phase-locked loop (PLL) frequency synthesizer, one of the
most important and challenging building blocks of the RF
transceiver, is most suitable for low cost CMOS integration of
wireless communication integrated circuits. PLL's are used but not
limited in wireless receivers and transmitters in part for
frequency synthesis where a synthesized local oscillator (LO)
frequency is needed to mix down the Receive Signal Carrier such
that the modulated signal is down-converted and the resulting
base-band signal can be processed. Since the receive signal can
operate in different bands or at discrete frequencies as part of
the data transmission standard, an agile PLL frequency synthesizer
is needed in order to track the receiver frequency by adjusting the
LO frequency. A charge pump PLL is comprised of a reference
oscillator (usually crystal based), a phase-frequency detector
(PFD), charge pump (either voltage or current mode), a loop filter,
a voltage-controlled oscillator (VCO), and a programmable feedback
frequency divider. Each of the PLL building elements represents
architecture and circuit design challenges. The generation of
sideband levels in a PLL is a major concern that usually drives a
charge pump's design and loop filtering requirements. In the most
stringent GSM receiver area, the channel spacing (200 kHz) is
considerably narrower than other wireless communication standards.
When using an integer M/N PLL in a frequency synthesizer, the input
reference frequency must be of the same order of magnitude relative
to the channel spacing frequency specification. The PLL is able to
synthesize frequencies with frequency steps equal to an integer
multiple of the input reference frequencies. The maximum loop
filter bandwidth is limited by the update rate of the PFD, which is
the sample rate of the loop. As a rule of thumb, loop filter
bandwidth should be much less than one tenth ( 1/10) of the PFD
update rate to avoid instability of the PLL. If the sample rate of
the input reference frequency and the PLL loop bandwidth becomes
relatively close, then discrete time techniques may be needed or
added to stabilize and predict PLL transient and steady state
performance to avoid signal degradation. With the stringent loop
filter bandwidth and reference frequency feed through filtering
requirements, the charge pump PLL is a most suitable solution with
the charge pump itself drawing considerable interest and study. The
charge pump design works in conjunction with the PFD to improve the
PLL performance. FIG. 1 show the combination of a PFD, 1, and a
charge pump, 2. The PFD is a common Type Four, tri-state approach
that can be implemented with various digital design methods. This
design detects the phase and/or frequency difference between the
reference signal, f1 and the divided VCO output signal f2 as shown
in the timing diagram in FIG. 2. The resulting output signals, PU
and PD, are used to control the relative current commutation times
in the charge pump output current Iout. The charge pump output
drives a passive loop-filter LF, which can include passive load
elements of resistance, capacitance and inductance.
Charge Pump
[0009] Charge pumps as well as PLL frequency synthesizers are used
in many computer, consumer and communication applications. Charge
pumps can operate in either current or voltage mode and are
implemented in different ways with fully differential or
single-ended signal designs. Within these two classifications,
there are multiple design options with their own inherent benefits
and flaws.
[0010] The simplest charge pump design is the single-ended signal
design where the charge pump is controlled by full swing digital
signals to open a current source switch for a sourcing or sinking
operation. In addition, the digital signal control will be used to
quickly turn off the current source switch in the high impedance or
tri-state mode. Rapid turn-on and turn-off times as well as the
relative ease of matching the timing of the source and sink
controlling signals are the benefits of this approach. However,
relatively large transients can be induced across parasitic
junction capacitance's that inject unwanted spurious noise.
Furthermore, full swing designs always suffer from transient
currents being induced through the power supply and ground return
paths as well as introducing low efficiency in the charge pump
because of asymmetrical current sourcing and current sinking
behavior.
[0011] Differential signal charge pump designs using constant
current mode operation have also been proposed for the charge pump
to overcome the shortcomings of the single-ended design. The
differential signal design approach has the benefits of high
common-mode rejection to power supply noise and providing
symmetrical pump currents. The differential approach while looking
favorable in many areas has its own limitations such as constant
power loss and charge injection from the charge pump into the loop
filter load. In certain charge pump architectures, relatively small
sized differential devices are used to steer the currents in order
to reduce parasitic capacitance, charge injection and charge
sharing effects. However, undesirably larger driving signals are
still needed to completely steer current across the small sized
differential pair devices. In this situation, larger driving
signals again lead to the above mentioned effects of transients
induced across parasitic junction capacitance's that inject
unwanted spurious noise contributing to increased reference
frequency feed-through in the PLL.
The Reference Frequency Feed-Through/Modulation Sideband Theory
[0012] Due to the fact that the VCO is typically controlled by a
node voltage, any reference frequency feed-through effects from the
phase detector/charge pump design can modulate this voltage thereby
creating modulation sidebands at the VCO RF frequency. Shown below
is a mathematical description of this modulation process where
modulation tones are shown to be linear in power level for small
modulation indexes.
[0013] .omega..sub.c--Carrier frequency
[0014] m.sub.p--modulation index
[0015] g(t)--modulation function (sinusoid)
m(t)=A cos(.omega..sub.ct+.PHI.) 1.
.PHI.=m.sub.p*g(t) 2.
g(t)=cos .omega..sub.nt 3.
m(t)=A cos(.omega..sub.ct+m.sub.p*cos(.omega..sub.mt) 4.
cos(.alpha.+.beta.=cos .alpha. cos .beta.-sin .alpha. sin .beta.
5.
m(t)=A cos .omega..sub.ct cos(m.sub.p*cos(.omega..sub.mt))-A sin
.omega..sub.ct sin(m.sub.p*cos(.omega..sub.mt)) 6.
cos(z cos
.THETA.)=J.sub.0(z)+2.SIGMA..sub.n=0(-1).sup.nJ.sub.2n(z)cos(2n.THETA.)
7.
sin(z cos
.THETA.)=2.SIGMA..sub.n=0(-1).sup.nJ.sub.2n+1(z)cos(2n+1).THETA.
8.
m(t)=A{(cos(.omega..sub.ct)J.sub.0(m.sub.p)+2.SIGMA..sub.n=1(-1).sup.nJ.-
sub.2(m.sub.p)*cos .omega..sub.ct
cos(2n.omega..sub.mt)-2.SIGMA..sub.n=0(-1).sup.nJ.sub.2n+1(m.sub.p)sin
.omega..sub.ct cos(2n+1).omega..sub.mt} 9.
cos x cos y=1/2[cos(x+y)+cos(x-y)] 10.
sin x sin y=1/2[sin(x+y)+sin(x-y)] 11.
m(t)=A{(cos(.omega..sub.ct)J.sub.0(m.sub.p)+.SIGMA..sub.n=1(-1).sup.nJ.s-
ub.2n(m.sub.p)[cos
.omega..sub.ct+2n.omega..sub.ct)+cos(.omega..sub.ct-2n.omega..sub.mt)]-.S-
IGMA..sub.n=0(-1).sup.nJ.sub.2n+1(m.sub.p)*sin
.omega..sub.ct+(2n+1).omega..sub.mt+sin(.omega..sub.ct-(2n+1).omega..sub.-
mt)]}
m(t)=A{J.sub.0(m.sub.p)cos
.omega..sub.ct+J.sub.1(m.sub.p)[sin(.omega..sub.c+.omega..sub.m)t+sin(.om-
ega..sub.c-.omega..sub.m)t]-J.sub.2(m.sub.p)[cos(.omega..sub.ct+2.omega..s-
ub.m)t+cos(.omega..sub.ct-2.omega..sub.m)t]+J.sub.3(m.sub.p)[sin(.omega..s-
ub.ct+3.omega..sub.m)t+sin(.omega..sub.ct-3.omega..sub.m)t]- . . .
} 12.
The final expression shows that a carrier modulated by a single
sinusoid produces sets of sidebands offset from the carrier by
every possible multiple of the modulating frequency. The Bessel
coefficients (J.sub.n) are a function of the modulation index. If
m.sub.p is small, the higher frequency sideband terms are not
significant. Thus, for small modulation index only the first-order
sidebands are significant. The resulting frequency spectrum will
resemble a carrier undergoing amplitude modulation.
DISCUSSION OF PRIOR ART
[0016] New charge pump designs [1] are being proposed to improve
the PLL performance by adding cascoded devices for faster turn-on
and turn-off and for reducing charge sharing problems of operating
the high and low side switch together. However, this type of design
suffers from larger internal dynamic voltage swings that increase
the reference frequency feed through from the switching elements to
the filter load.
[0017] FIG. 3 shows a charge pump design known as prior art [2]
with the added cascode device M1 between the charge pump current
source, 1 and the output node, Iout; and the added cascode device
M2 between the charge pump current sink, 2 and output node, Iout. A
bias voltage circuit is connected to the cascaded devices M1 and
M2. The design improves the symmetry of both the turn-on and
turn-off times by isolating the feed-through of the controlling
signals, PU and PD that drive the switches, 3 and 4, from the
charge pump output node, Iout. However, since the internal circuit
nodes settle to their own internal turn-on and turn-off voltages,
this leads to potentially long and asymmetric turn-off decays. In
addition, switching transients are still not optimally reduced in
these designs.
OBJECTS AND ADVANTAGES OF THE INVENTION
[0018] Accordingly, it is a primary object of the present invention
to provide a new charge pump design for high performance CMOS
Frequency Synthesizers. The application is intended for the very
stringent design specifications of high integration RF receivers
and/or transmitters requiring low cost, small size and low power.
In a common architecture where a charge pump drives a passive
filter load, the resulting voltage used to control a
voltage-controlled oscillator (VCO) translates directly to the AC
performance of the VCO and the overall PLL control loop system.
Static phase detector offset, reference frequency feed-through, and
high sideband levels are direct results of non-idealities in the
charge pump design. Asymmetry in the charge pump drive such as
non-ideal current transitions driving a passive loop filter
contribute to transient spurs on the VCO control voltage node
resulting in unwanted frequency side band spectra. These errors and
effects due to the charge pump current switching inefficiencies'
are greatly magnified in a frequency synthesizer architecture that
uses a Sigma-Delta modulator (SDM). Reference spurs and other
frequency spectra must be controlled in SDM designs for PLL
implementations. Accurate charge pumps are required for GSM
receiver synthesizers to meet the most rigid phase noise and
frequency sideband specifications in wireless communications.
[0019] The following lists the advantages of the invention compared
to prior art charge pumps. [0020] 1. Reference frequency sidebands
are minimized due to improved matching in the current source and
current sink drivers compared to the prior art same type charge
pump designs and compared to other types of charge pump designs.
[0021] 2. Current sink and source driver symmetry and path matching
properties remain the same over temperature and manufacturing
process variations. [0022] 3. Double-cascoded design in both the
source and sink driver eliminates or reduces the transient
feed-through at turn-on and turn-off events. [0023] 4. The charge
pump is scalable by adding multiple source and sink stages to
achieve larger increase in charge pump current levels while the
matching and symmetry properties of both the source and sink
sections remain. [0024] 5. An active replica bias clamp circuit
detects and controls the leakage current in the charge pump
off-state.
SUMMARY OF THE INVENTION
[0025] The present invention achieves the above objects and
advantages by providing a new method for implementing a charge pump
with double cascoded drivers, a reference signal generator and a
replica bias clamp detection circuit. The following lists the new
design features of the charge pump for this invention. [0026] 1.
Double cascoded source and sink drivers designed to have very
symmetrical turn-on and turn-off effects and high output impedance
in the off-state. [0027] 2. Single or multiple reference voltage
generators to balance the symmetry of the turn-on and turn-off
currents over operating temperature. [0028] 3. Signal path matching
is optimized with matched differential CMOS full swing control
signals. [0029] 4. Transmission gates implemented for both current
sink and current source to achieve low leakage current in the
off-state and fast turn-on time in the on-state. [0030] 5. A
replica bias clamp detection circuit which limits the reverse
off-state leakage current in the charge pump. [0031] 6. Overall
architecture enables independent symmetry and matching optimization
of the turn-on and turn-off current transients in both the current
source and current sink drivers/switches.
DESCRIPTION OF DRAWINGS
[0032] FIG. 1 is a schematic of a prior art PFD and charge pump
combination circuit.
[0033] FIG. 2 is a timing diagram of a prior art PFD circuit.
[0034] FIG. 3 is a schematic of a prior art charge pump.
[0035] FIG. 4 is a schematic of a PMOS current source of a charge
pump constructed with the principles of the invention.
[0036] FIG. 5 is a schematic of the symmetric charge pump
constructed with the principles of the invention.
[0037] FIG. 6 is a schematic of the symmetric charge pump with two
independent reference bias voltage sources constructed with the
principles of the invention.
[0038] FIG. 7 is a schematic of the charge pump reference bias
voltage constructed with the principles of the invention.
[0039] FIG. 8 is a schematic of the charge pump with a replica bias
clamp detection circuit constructed with the principles of the
invention.
[0040] FIG. 9 is a schematic of the replica bias clamp detection
circuit constructed with the principles of the invention.
[0041] FIG. 10 is a schematic of the charge pump circuit with the
replica bias clamp detection circuit constructed with the
principles of the invention.
[0042] FIG. 11 is a schematic of the differential charge pump
circuit with the replica bias clamp detection circuits constructed
with the principles of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0043] FIG. 4 is a schematic of the top-side PMOS current source of
a charge pump constructed in accordance with the principles of the
present invention. The charge pump theory of operation is common
between the top-side PMOS current source and bottom-side current
sink circuits. Therefore the explanation on the PMOS top-side
circuit is sufficient for the total charge pump section. This
embodiment is for a new Charge Pump architecture and design for use
in a PLL frequency synthesizer for radio frequency applications
including but not limited GSM standard with a very symmetrical
charge pump current drive. This novel architecture permits the
symmetrical turn-on time, rise time and fall time to be independent
in the design and optimization process. The generation of
differential output phases for both pump-up, PU and pump-down, PD
is synchronized by a PFD and charge pump driver and buffer. All
current source and sink cells are identical and should track very
well over manufacturing process and operating temperature
variations. When the transmission switch, S1, consisted of M7 and
M8 is open, M3 and M5 act as a cascode current mirror arrangement.
M2 is always turned on and will operate in the triode region. M1
turns on when its gate is pulled low by the buffered pump up
control signal, PU. M1 then pulls up the source of M3 towards the
power supply, Vcca relative to M3's gate voltage. As M3 starts to
turn on, M5's source voltage also rises higher than its gate
voltage. The turn-on speed capability of this current path is
limited by the charging capacitance at the source nodes of M3 and
M5. The sizes of transistors M1, M3 and M5 can be scaled up as
multiples of that of transistors M2, M4 and M6, respectively to
deliver a (known) desired current level. Note that the source of M3
pulls up much faster than the source of M5 due to the lower
impedance provided by M1 to the power supply than that of M3. The
cascode arrangement allows a softer turn-on of currents and
isolates transients from reaching the output. Both M3 and M5's gate
voltages are capacitively filtered to absorb the parasitic coupling
by the large source voltage variations during turn-on and turn-off.
Transmission switch S1 is turned on to lower the source voltage of
M5 thus enabling M5's fast turn-off while M1 is turned off via the
CMOS differential buffer circuit. Vbias is a voltage that is
connected to M5's source at turn-off through transmission switch,
S1. For complete turn-off of M5, Vbias when connected in the
off-state must be a voltage that leaves M5's gate-to-source voltage
at less than one threshold. Those skilled in the present state of
the art will recognize that the invention does not limit to the
transmission switch circuit represented here. The transmission
switch can be designed with many other methods for this
invention.
[0044] FIG. 5 shows the schematic of the symmetric charge pump.
Dummy load devices, 1 are used to balance out charge sharing and to
equalize the load capacitance on the differential CMOS control
lines, 2. Dummy load transistors as shown with the drain and source
shorted together are connected together across the transmission
switch, S1 and S2. The dummy loading capacitances from the M5/M3'
source/drain connection and the control voltage, Vbias, balance out
the charge injected across the parasitic capacitance of
transmission switch, S1 due to the switching of the CMOS
differential control signal pair, PU. In addition, the dummy
loading capacitances equalize the capacitive load of the CMOS
driving control signals, PU and PD to maintain the symmetry of
these signals' rise and fall times as more charge pump stages are
added.
[0045] When higher circuit output voltages are needed, the optimum
bias voltage for complete output current turn-off diverges from a
common reference bias voltage, Vbias, as shown in FIG. 4 for both
charge pump up and pump down operations.
[0046] FIG. 6 shows the schematic of the symmetric charge pump with
two independent reference bias voltage sources, Vbiasp, 1 and
Vbiasn, 2 for generating high output voltages. The unwanted leakage
current mechanism is due to the fact that the charge pump output
cascode transistors M5 or M9 of FIG. 5 or FIG. 6 may become turned
on in the reverse direction which provides an un-wanted leakage
current path in the reverse direction. The reverse current
mechanism is due to the fact that transistors M5 and M9 each have
two terminals, gate and source, that are biased independent of the
third common terminal, Iout. The source terminals of transistor M5
and M9 are biased together or independently at fixed values as
shown in FIG. 5 or 6 respectively. The value of node voltage, Iout,
at the drain terminal of M5 can increase and exceed the turn-on
threshold voltage between M5's gate and drain. In addition, The
value of node voltage, Iout, at the drain terminal of M9 can
decrease and exceed the turn-on threshold voltage between M9's gate
and drain. The leakage current is due to the fact of either M5 or
M9 may become forward biased in the reverse direction. Thus, during
the charge pump off-state time with the transmission switches S1,
S2 shorted to the appropriate reference voltage, Vbiasp/Vbiasn, a
large un-wanted leakage current may flow in either direction
relative to the loop filter node, Iout.
[0047] FIG. 7 shows the schematic of a Charge Pump source/sink
reference bias voltage. A reference voltage with minimal variation
over manufacture process is developed by sourcing a current through
the proper monolithic resistance. The current varies inversely with
resistance to keep the internal reference voltage, 1 at a constant
potential. The operational amplifier (OPAMP), 2 and the additional
output stage, 3 form a two-stage amplifier that keeps the output
impedance at node Vbias low such that the circuit acts as a good
voltage source. The network, 4 between the first and second stage
performs frequency compensation to guarantee stability. Those
skilled in the present state of the art will recognize that the
invention does not limit to the bias circuit, OPAMP, additional
output stage and the frequency compensation network as represented
here. These blocks can be designed by many other methods for this
invention.
[0048] FIG. 8 shows an extension of the original charge pump design
as shown in FIGS. 4, 5 and 6 by adding a replica bias clamp
detection circuit which limits the reverse leakage current in the
off-state. The function of the replica bias clamp circuit is to
detect leakage current in a replica charge pump circuit and to open
the switch, S2, to disable the transmission switch S1 in the charge
pump from connecting to the voltage reference node, Vbias. This
circuit monitors leakage current on both the top side and bottom
side current source and sink drivers, respectively.
[0049] FIG. 9 shows the full replica bias clamp detection circuit.
The replica bias clamp detection circuit consists of a high-side
charge pump current replica circuit, 1, a low-side charge pump
current replica circuit, 2, a high-side leakage detection
comparator circuit, 3, a low-side leakage detection comparator
circuit, 4, and a unity-gain voltage follower buffer, 5. The high
and low-side charge pump current replica circuits together comprise
an identical scaled-down version of the charge pump in the
switched-off state. This is due to the fact that transmission
switched S1 and S2 are always active or on. The replica bias clamp
detection circuit monitors the reverse leakage current effect due
to high or low loop filter voltages that are seen on the output of
the charge pump, Iout. In the preferred embodiment of this
invention, it is preferable to buffer the charge pump/loop filter
voltage back to the replica section with a unity gain voltage
follower, 5. In addition, the unity gain buffer is preferred to
have "wide swing" input and output stages, such that extreme high
and low output voltage levels across the loop filter that the
charge pump is driving can be accurately sensed. Those skilled in
the present state of the art will recognize that there are many
ways to construct "wide-swing OPAMPS and buffer circuits. In the
detection circuit configuration, the unity gain voltage follower
can deliver the a bi-directional replica leakage current to the
charge pump replica bias detector without discharge of the loop
filter node, Iout. The scaled-down replica circuit of FIG. 9 tracks
the actual charge pump transistor output stage, Iout, of either
FIG. 5 or FIG. 6. In the event of a high or low voltage present at
node Iout which would trigger an unknown value and direction of
leakage current in the charge pump, a current would also flow
through the replica charge pump source transistor M1 or sink
transistor M2 in the reverse direction. This charging action will
change the sensing voltage at the input of inverters 3 or 4. When
the sensing voltage at the inverter inputs changes state, the
output signal will turn off the appropriate series switch S3 as
shown in FIG. 10. For example, if the node voltage at Iout is one
threshold voltage above M5's gate in FIG. 6 and M1's gate in FIG.
9, M5 and M1 will turn on in the reverse direction and deliver
charge through the transmission switch S1. However, in the replica
bias clamp detection circuit of FIG. 9, this charging action will
increase the voltage at the input of inverter 3. Additionally, if
the node voltage at Iout is one threshold voltage below M9's gate
in FIG. 6 and M2's gate in FIG. 9, M2 will turn on in the reverse
direction and deliver charge through the replica transmission
switch S2. This charging action will decrease the voltage at the
input of inverter 4. The inputs of both inverters 3 and 4 have
current sources that sink and source small constant currents
respectively to bias the inverters inputs when no reverse leakage
current is present. Current source I.sub.1 will discharge the input
node of inverter 3 at a low level when no leakage current is
present. Current source I.sub.2 will charge the input node of
inverter 4 at a high level when no reverse leakage current is
present. Thus, when the un-wanted leakage current condition exists,
a current will flow through either M1 or M2 with a charging
polarity that is opposite to the charging polarity of either
I.sub.1 or I.sub.2 in FIG. 9. When this reverse charging action is
greater than either I.sub.1 or I.sub.2 the voltage will change from
a low to high state at the input of inverter 3 or from a high to
low state at the input of inverter 4.
[0050] FIG. 10 shows the schematic of the charge pump circuit with
the replica bias clamp detection circuit as described in FIGS. 6
and 9. The outputs of inverter 3 and inverter 4 in FIG. 9 are used
to open or close the secondary switches, S3 of FIG. 10. Depending
on the voltage present across the loop filter load, LF, the replica
bias clamp detection circuit will limit the charge or discharge of
the loop filter node due to over/under voltage situations at Iout
that can cause large unwanted reverse leakage currents to flow
through the cascode charge pump. Without the bias clamp in place,
this condition has the possibility to occur during circuit power-up
and PLL lockup transient conditions. Thus, for occasions where the
loop filter voltage can exceed the output voltage compliance of the
charge pump, this replica bias clamp detection circuit is very
important.
[0051] FIG. 11 shows the schematic of a differential charge pump
with their respective replica bias clamp detection circuits. The
differential charge pump is an extension of the single-ended design
as described in FIGS. 5, 8 and 9. The differential charge pump
sections drive the same passive loop filter, LF which is in
parallel with a common mode feedback circuit, CMFB, to maintain the
"common mode" voltage across the LF load. The LF load has two nodes
with opposite polarities at all times. Common mode feedback
circuitry is widely used in electrical design and the block shown
can represent many different design approaches. To charge the LF in
the positive direction, a current is sourced from the left charge
pump into the LF positive node and a current is sunk into the right
charge pump from the negative node of the LF. Charging the LF
voltage in the negative direction requires the currents to flow in
the reverse directions.
* * * * *