Sudjian; Douglas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sudjian; Douglas.The latest application filed is for "detection circuit for overdrive conditions in a wireless device".

Company Profile

0.12.6

Sudjian; Douglas - Santa Clara CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Detection circuit for overdrive conditions in a wireless device Grant 8,688,060 - Sudjian April 1, 2	2014-04-01
Comparator with hysteresis Grant 8,310,279 - Sudjian November 13, 2	2012-11-13
Detection Circuit For Overdrive Conditions In A Wireless Device App 20100321096 - Sudjian; Douglas	2010-12-23
Comparator With Hysteresis App 20100289531 - Sudjian; Douglas	2010-11-18
Low power high speed latch for a prescaler divider Grant 7,521,976 - Sudjian , et al. April 21, 2	2009-04-21
Symmetric charge pump replica bias detector App 20080191783 - Sudjian; Douglas ; et al.	2008-08-14
System and method for recovering a clock using a reduced rate linear phase detector and voltage controlled oscillator Grant 7,409,027 - Sudjian August 5, 2	2008-08-05
Symmetric charge pump Grant 7,015,736 - Sudjian , et al. March 21, 2	2006-03-21
Triple input phase detector and methodology for setting delay between two sets of phase outputs Grant 6,774,689 - Sudjian August 10, 2	2004-08-10
High-speed latch with integrated gate Grant 6,737,899 - Sudjian May 18, 2	2004-05-18
System and method for generating interleaved multi-phase outputs from a nested pair of phase locked loops Grant 6,657,466 - Sudjian December 2, 2	2003-12-02
Method and apparatus for isolating circuits using deep substrate n-well Grant 6,633,073 - Rezvani , et al. October 14, 2	2003-10-14
High-speed logic gate Grant 6,628,145 - Sudjian September 30, 2	2003-09-30
High-speed Latch With Integrated Gate App 20030141912 - Sudjian, Douglas	2003-07-31
Method and apparatus for isolating circuits using deep substrate n-well App 20030013268 - Rezvani, Ali ; et al.	2003-01-16
Phase-lock loop with reduced acquistion time Grant 5,675,291 - Sudjian October 7, 1	1997-10-07

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.