U.S. patent application number 12/101965 was filed with the patent office on 2008-08-07 for trench isolation structure and a method of manufacture therefor.
This patent application is currently assigned to TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Mark S. Rodder, Rick L. Wise.
Application Number | 20080185675 12/101965 |
Document ID | / |
Family ID | 35481152 |
Filed Date | 2008-08-07 |
United States Patent
Application |
20080185675 |
Kind Code |
A1 |
Wise; Rick L. ; et
al. |
August 7, 2008 |
Trench Isolation Structure and a Method of Manufacture Therefor
Abstract
The present invention provides a trench isolation structure, a
method of manufacture therefor and a method for manufacturing an
integrated circuit including the same. The trench isolation
structure (130), in one embodiment, includes a trench located
within a substrate (110), the trench having a buffer layer (133)
located on sidewalls thereof. The trench isolation structure (130)
further includes a barrier layer (135) located over the buffer
layer (133), and fill material (138) located over the barrier layer
(135) and substantially filling the trench.
Inventors: |
Wise; Rick L.; (Fairview,
TX) ; Rodder; Mark S.; (University Park, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
US
|
Assignee: |
TEXAS INSTRUMENTS
INCORPORATED
Dallas
TX
|
Family ID: |
35481152 |
Appl. No.: |
12/101965 |
Filed: |
April 12, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10870020 |
Jun 17, 2004 |
7371658 |
|
|
12101965 |
|
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Current U.S.
Class: |
257/506 ;
257/E21.546; 257/E21.633; 257/E21.642; 257/E23.002 |
Current CPC
Class: |
H01L 21/823878 20130101;
H01L 21/823807 20130101; H01L 21/76224 20130101 |
Class at
Publication: |
257/506 ;
257/E23.002 |
International
Class: |
H01L 23/58 20060101
H01L023/58 |
Claims
1. (canceled)
2. (canceled)
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. (canceled)
10. (canceled)
11. (canceled)
12. A trench isolation structure, comprising: a trench located
within a substrate, the trench having sidewalls and a bottom
surface; a buffer layer located on the sidewalls of the trench; and
fill material located over the buffer layer, the fill material
substantially filling the trench.
13. The trench isolation structure as recited in claim 12 wherein a
barrier layer is located between the buffer layer and the fill
material.
14. The trench isolation structure as recited in claim 13 wherein
the barrier layer has a thickness ranging from about 4 nm to about
20 nm.
15. The trench isolation structure as recited in claim 13 wherein
the buffer layer is a layer of silicon.
16. The trench isolation structure as recited in claim 15 wherein
the barrier layer is a silicon dioxide barrier layer located on the
layer of silicon.
17. The trench isolation structure as recited in claim 12 wherein
an interface exists between the buffer layer and the sidewalls.
18. The trench isolation structure as recited in claim 12 wherein
the substrate includes a first portion comprising silicon germanium
and a second portion comprising silicon.
19. The trench isolation structure as recited in claim 18 wherein
at least a portion of the buffer layer proximate the first portion
includes germanium.
20. The trench isolation structure as recited in claim 12 wherein
the buffer layer has a thickness ranging from about 1 nm to about 5
nm.
21. The trench isolation structure as recited in claim 12 wherein
the buffer layer is further located on the bottom surface.
22. (canceled)
23. (canceled)
24. (canceled)
25. (canceled)
26. (canceled)
27. (canceled)
28. (canceled)
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention is directed, in general, to a trench
isolation structure and, more specifically, to a trench isolation
structure having a buffer layer located along sidewalls of the
trench, a method of manufacture therefor, and a method for
manufacturing an integrated circuit including the same.
BACKGROUND OF THE INVENTION
[0002] An important aim of ongoing research in the semiconductor
industry is increasing semiconductor performance while decreasing
the size of semiconductor devices. One known step the industry has
taken to attain this increased semiconductor performance is to
implement strained silicon technology. Fortunately, strained
silicon technology allows for the formation of higher speed
devices.
[0003] Strained-silicon transistors may be created a number of
different ways, including by introducing a dislocation loop, or
excess plane of atoms, into a crystalline material. In one instance
strained layers are created by forming a layer of silicon germanium
(SiGe) below a silicon epitaxial layer. The average distance
between atoms in the SiGe crystal lattice is greater than the
average distance between atoms in an ordinary silicon lattice.
[0004] Because there is a natural tendency of atoms inside
different crystals to align with one another when a second crystal
is formed over a first crystal, when silicon is deposited on top of
SiGe, or vice-versa, the silicon crystal lattice tends to stretch
or "strain" to align the silicon atoms with the atoms in the SiGe
layer. Fortunately, as the electrons in the strained silicon
experience less resistance and flow up to 80% faster than in
unstrained silicon, the introduction of the strained silicon layer
allows for the formation of higher speed devices. Problems
currently exist, however, with the integration of the strained
silicon technology with preexisting technologies.
[0005] Accordingly, what is needed in the art is a semiconductor
device and method of manufacture therefore that experiences the
benefits of strained silicon technology without experiencing its
drawbacks.
SUMMARY OF THE INVENTION
[0006] To address the above-discussed deficiencies of the prior
art, the present invention provides a trench isolation structure, a
method of manufacture therefor and a method for manufacturing an
integrated circuit including the same. The trench isolation
structure, in one embodiment, includes a trench located within a
substrate, the trench having a buffer layer located on sidewalls
thereof. The trench isolation structure further includes a barrier
layer located over the buffer layer, and fill material located over
the barrier layer and substantially filling the trench.
[0007] As indicated above, the present invention further provides a
method for manufacturing a trench isolation structure. The method
for manufacturing a trench isolation structure, among other steps,
includes forming a trench in a substrate, forming a buffer layer on
sidewalls of the trench, forming a barrier layer over the buffer
layer, and forming fill material over the barrier layer to
substantially fill the trench.
[0008] The foregoing has outlined preferred and alternative
features of the present invention so that those skilled in the art
may better understand the detailed description of the invention
that follows. Additional features of the invention will be
described hereinafter that form the subject of the claims of the
invention. Those skilled in the art should appreciate that they can
readily use the disclosed conception and specific embodiment as a
basis for designing or modifying other structures for carrying out
the same purposes of the present invention. Those skilled in the
art should also realize that such equivalent constructions do not
depart from the spirit and scope of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The invention is best understood from the following detailed
description when read with the accompanying FIGURES. It is
emphasized that in accordance with the standard practice in the
semiconductor industry, various features are not drawn to scale. In
fact, the dimensions of the various features may be arbitrarily
increased or reduced for clarity of discussion. Reference is now
made to the following descriptions taken in conjunction with the
accompanying drawings, in which:
[0010] FIG. 1 illustrates a cross-sectional view of one embodiment
of a semiconductor device constructed according to the principles
of the present invention;
[0011] FIG. 2 illustrates a cross-sectional view of a partially
completed semiconductor device manufactured in accordance with the
principles of the present invention;
[0012] FIG. 3 illustrates a cross-sectional view of the partially
completed semiconductor device illustrated in FIG. 2 after forming
a buffer layer on sidewalls of the trenches;
[0013] FIG. 4 illustrates a cross-sectional view of the partially
completed semiconductor device illustrated in FIG. 3 after forming
a barrier layer over the buffer layer;
[0014] FIG. 5 illustrates a cross-sectional view of the partially
completed semiconductor device illustrated in FIG. 4 after
depositing a blanket layer of fill material over the substrate and
within the trenches, and subsequent thereto polishing the blanket
layer of fill material resulting in fill material plugs;
[0015] FIG. 6 illustrates a cross-sectional view of the partially
completed semiconductor device illustrated in FIG. 5 after forming
a well region within the substrate; and
[0016] FIG. 7 illustrates a cross-sectional view of a conventional
integrated circuit (IC) incorporating the trench isolation
structures constructed according to the principles of the present
invention.
DETAILED DESCRIPTION
[0017] Strained silicon technology, and more specifically, strained
silicon technology employing silicon germanium (SiGe) as the strain
inducing layer, is well known and commonly used in today=s high
technology fields. Unfortunately, as initially recognized by the
present invention, compatibility issues arise when the strained
silicon technology employing SiGe is integrated with conventional
trench isolation structures. The present invention, in contrast to
the prior art, recognizes that at least a portion of the
compatibility issues can be attributed to undesirable effects
occurring at the interface between the SiGe layer and the barrier
layer lining the sidewalls of the trench isolation structures.
Particularly, it has been observed that the growth of the barrier
layer at this interface causes the germanium at the interface to
pile up. Substantial experimentation indicates that the germanium
pile up causes device problems (e.g., edge diode leakage issues),
becoming more pronounced as the width of the transistors continues
to decrease.
[0018] Given the aforementioned recognition, one inventive aspect
of the present invention is the realization that a buffer layer may
be employed between the SiGe layer located along the sidewalls of
the trench and the barrier layer to provide a sufficient cushion
between the SiGe layer and barrier layer so as to substantially
reduce, or even eliminate, the germanium pile up. Therefore, the
buffer layer may be introduced into the manufacture of the trench
isolation structures to reduce the aforementioned integration
issues associated with the strained silicon technology.
[0019] Referring initially to FIG. 1, illustrated is a
cross-sectional view of one embodiment of a semiconductor device
100 constructed according to the principles of the present
invention, which benefits from the unique recognition discussed
above. In the embodiment illustrated in FIG. 1, the semiconductor
device 100 includes a substrate 110. The substrate 110, as
illustrated, may comprise any combination of one or more layers.
The particular embodiment of FIG. 1, however, illustrates the
substrate 110 including a first substrate portion 113 comprising
SiGe and a second substrate portion 118 comprising strained
silicon.
[0020] Located within the substrate 110 in the embodiment of FIG. 1
is a well region 120. Located within the substrate 110, and in this
embodiment partially overlapping the well region 120, are novel
trench isolation structures 130. The novel trench isolation
structures 130 each include a buffer layer 133 located on the
sidewalls of the trench. The buffer layer 133, which may comprise a
thin layer of silicon in an exemplary embodiment, may also be
located on a bottom surface of the trench. Similarly, if the buffer
layer 133 remains, it might have a thickness ranging from about 1
nm to about 5 nm.
[0021] Formed over, and in this particular embodiment directly on
the buffer layer 133, is a barrier layer 135. The barrier layer
135, among other materials, may comprise an oxide, such as silicon
dioxide. Similarly, the barrier layer 135 may have a thickness,
among others, ranging from about 4 nm to about 20 nm. While the
embodiment of FIG. 1 illustrates that the barrier layer 135 be
located over the buffer layer 133, and more particularly in between
the buffer layer 133 and the fill material 138, such is not always
the case. It is believed that in certain embodiments the barrier
layer 135 may be dispensed with, the buffer layer 133 providing the
requisite buffer between the trench surface and the fill material
138. In this instance the buffer layer 133 would retard the
formation of germanium pile-up, as might be the case were the fill
material 138 to be formed directly on the trench surfaces.
[0022] Additionally located over the barrier layer 135, and
substantially filling the trench of the trench isolation structure
130, is a fill material 138. The fill material 138 may comprise a
multitude of different materials while staying within the scope of
the present invention.
[0023] As illustrated in FIG. 1, additionally located over the
substrate 110 and well region 120, and between the trench isolation
structures 130, is a gate structure 140. The gate structure 140
illustrated in FIG. 1 includes a conventional gate dielectric 143
located over the substrate 110, as well as a conventional gate
electrode 148 located over the gate dielectric 143. The
semiconductor device 100 additionally includes conventional
source/drain regions 150 located within the substrate 110 and
proximate the gate dielectric 143. The source/drain regions 150, as
is common, may each include an extension portion 153 as well as a
source/drain portion 158. While the semiconductor device 100
illustrated in FIG. 1 includes only a limited number of features,
those skilled in the art understand that the semiconductor may, and
in most instances will, contain a multitude of other features while
staying within the scope of the present invention.
[0024] Turning now to FIGS. 2-5, illustrated are cross-sectional
views of detailed manufacturing steps instructing how to, in an
advantageous embodiment, manufacture a semiconductor device similar
to the semiconductor device 100 depicted in FIG. 1. FIG. 2
illustrates a cross-sectional view of a partially completed
semiconductor device 200 manufactured in accordance with the
principles of the present invention. The partially completed
semiconductor device 200 of FIG. 2 initially includes a substrate
210. The substrate 210 may, in an exemplary embodiment, be any
layer located in the partially completed semiconductor device 200,
including a wafer itself or a layer located above the wafer (e.g.,
epitaxial layer). Similarly, the substrate 210 may comprise one or
more layers while staying within the scope of the present
invention.
[0025] In the embodiment illustrated in FIG. 2, the substrate 210
includes a first substrate portion 213 comprising SiGe and a second
substrate portion 218 comprising strained silicon. It has been
observed that many of the novel aspects of the present invention
are particularly useful when used in conjunction with the
aforementioned first and second substrate portions 213, 218. Those
skilled in the art understand many of the specific processing steps
that might be used to form the illustrative first and second
substrate portions 213, 218, therefore, no further detail will be
given at this time. Even though the exemplary embodiment of FIGS.
2-5 has been discussed with respect to the first and second
substrate portions 213, 218, comprising SiGe and strained silicon,
respectively, other materials could be used for the substrate
210.
[0026] The substrate 210 of FIGS. 2-5 is a P-type substrate;
however, one skilled in the art understands that the substrate 210
could be an NBtype substrate without departing from the scope of
the present invention. In such a case, each of the dopant types
described throughout the remainder of this document would be
reversed. For clarity, no further reference to this opposite scheme
will be discussed.
[0027] Conventionally formed within the substrate 210 using a
patterned resist layer 220, as well as a dielectric stack (e.g.,
oxide layer 224 and nitride layer 228), are trenches 230. An
exemplary lithographic process has been used to form the trenches
230 in the substrate 210. Lithography refers to a process for
pattern transfer between various media. The lithographic process
may include forming a radiation sensitive resist coating over the
layer to be patterned, in this case the substrate 210. The
radiation sensitive resist coating may then be patterned by
selectively exposing the resist through a mask. In turn, the
exposed areas of the coating become either more or less soluble
than the unexposed areas, depending on the type of resist. A
solvent developer may then be used to remove the less soluble areas
leaving the patterned resist layer 220.
[0028] After the resist layer 220 is patterned, the dielectric
layer stack, comprising the oxide layer 224 and the nitride layer
228, and substrate 210 may be etched using the patterned resist
layer 220 as a mask to transfer the pattern to the substrate 210.
Etch processes, among others, might include plasma etching,
reactive ion etching, wet etching, or combinations thereof.
Nevertheless, plasma etching is preferred.
[0029] The resulting trenches 230, in an advantageous embodiment,
have a depth ranging from about 0.2 .PHI.m to about 0.5 .PHI.m and
a width ranging from about 0.1 .PHI.m to about 0.5 .PHI.m. Other
depths and widths may nonetheless be used.
[0030] Turning now to FIG. 3, illustrated is a cross-sectional view
of the partially completed semiconductor device 200 illustrated in
FIG. 2 after removing the resist layer 220 and forming a buffer
layer 310 on the sidewalls of the trenches 230. As illustrated, the
buffer layer 310 may also advantageously be formed on the bottom
surface of the trenches 230, and forms an interface with the
substrate 210.
[0031] The thickness of the buffer layer 310 is at least partially
dependent on the thickness of the barrier layer 410 that will be
formed thereover (FIG. 4). For instance, the buffer layer 310 in an
exemplary embodiment should initially be formed to a thickness of
approximately half the thickness of the resulting barrier layer 410
(FIG. 4). Accordingly, in an advantageous embodiment, the buffer
layer 310 may have a thickness ranging from about 2 nm to about 10
nm, and more particularly a thickness ranging from about 2 nm to
about 5 nm. The buffer layer 310 may further comprise a number of
different materials while staying within the scope of the present
invention. In the illustrative embodiment, however, the buffer
layer 310 comprises a layer of silicon. Other buffer layers 310
could nonetheless be used.
[0032] The buffer layer 310 may be formed using many different
processes. For example, the embodiment of FIG. 3 illustrates the
buffer layer 310 being formed on the sidewalls and bottom surface
of the trenches 230 using a deposition process, and more
specifically a chemical vapor deposition (CVD) process. As the
dielectric stack comprising the oxide layer 224 and nitride layer
228 remains on the substrate 210 at this time, the buffer layer 310
is selectively deposited on the sidewalls and bottom surfaces of
the trenches 230. Accordingly, the buffer layer 310 need not be
removed from the upper surface of the substrate 210 in the
embodiment shown.
[0033] In the embodiment where the buffer layer 310 is deposited
using the CVD process, a pressure ranging from about 10 torr to
about 100 torr, a temperature of less than about 850 EC, a H.sub.c
flow ranging from about 10 slm to about 50 slm, a SiH.sub.cCl.sub.c
gas flow ranging from about 10 sccm to about 300 sccm, and a HCl
gas flow ranging from about 10 sccm to about 300 sccm could be
used. It goes without saying that other deposition parameters and
techniques are equally as applicable to the present invention. The
temperatures used to form the buffer layer 310, as well as
subsequent layers, may cause a portion of the germanium from the
first substrate portion 213 to diffuse into the buffer layer 310.
As the concentration of germanium within the buffer layer 310 is
minimal, it should not cause any significant problems.
[0034] Turning now to FIG. 4, illustrated is a cross-sectional view
of the partially completed semiconductor device 200 illustrated in
FIG. 3 after forming a barrier layer 410 over the buffer layer 310.
While not shown, the barrier layer 410 may comprise any combination
of one or more layers. In the illustrative embodiment shown, the
barrier layer 410 is located on the buffer layer 310. Nevertheless,
the buffer layer 310 might not always remain on the sidewalls and
bottom surfaces of the trenches 230, as the barrier layer 410 might
consume the entire buffer layer 310 during its formation. In this
instance the barrier layer 410 might be located over, and more
particularly directly on, the sidewalls and bottom surface of the
trenches 230. Nevertheless, the embodiment of FIG. 4 has a thin
buffer layer 310 remaining on the sidewalls and bottom surfaces of
the trenches 230. In an ideal situation the remaining buffer layer
310 should have a thickness ranging from about 1 nm to about 5
nm.
[0035] The barrier layer 410 advantageously has a thickness ranging
from about 4 nm to about 20 nm, and more particularly a thickness
ranging from about 5 nm to about 10 nm. Similarly, the barrier
layer 410 ideally comprises silicon dioxide. Other materials,
including a nitrided oxide, could also be used for the barrier
layer 410.
[0036] The barrier layer 410 may be formed using a number of
different processes. For instance, the particular process used
might depend on the material chosen for the buffer layer 310. In
the illustrative embodiment of FIGS. 3-4 the buffer layer 310
comprises a layer of silicon. Thus, in this exemplary embodiment, a
thermal oxidation process might be used to form the barrier layer
410. If a thermal oxidation process were used, the partially
completed semiconductor device could be subjected to a temperature
of less than about 850 EC in the presence of oxygen for a time
period ranging from about 20 minutes to about 60 minutes to form
the barrier layer 410. Obviously the oxidation temperature and time
could be optimized to provide a particular barrier layer 410
thickness or quality. Those skilled in the thermal growth of oxides
would understand how to tailor these process parameters. Even
though the formation of the barrier layer 410 is discussed with
respect to a thermal growth process, any known or later discovered
deposition process could also be used.
[0037] Turning now to FIG. 5, illustrated is a cross-sectional view
of the partially completed semiconductor device 200 illustrated in
FIG. 4 after depositing a blanket layer of fill material over the
substrate 210 and within the trenches 230, and subsequent thereto
polishing the blanket layer of fill material, and removing the
dielectric stack comprising the oxide layer 224 and nitride layer
228, resulting in fill material plugs 510. As is illustrated, the
fill material plugs 510 substantially, if not completely, fill the
trenches 230.
[0038] Those skilled in the art understand the specific processes
that could be used to deposit the blanket layer of fill material
and polish it back to the substrate 210. For instance, a blanket
layer of dielectric material, or in another instance a blanket
layer of slightly conductive material, could be CVD deposited in
such a way as to substantially fill the trenches 230. Thereafter, a
conventional chemical mechanical planarization (CMP) process might
be used to polish the undesirable portions of the blanket layer of
fill material back to the substrate 210. Other deposition and
polishing processes could also be used.
[0039] What results after the blanket deposition and polishing
processes are completed trench isolation structures 520. Each of
the completed trench isolation structures 520 includes the barrier
layer 410 and the fill material plug 510. In certain embodiment of
the invention, as discussed above, a portion of the buffer layer
310 remains between the sidewalls and bottom surface of the
substrate 210 and the barrier layer 410. This circumstance might
occur where the barrier layer 410 does not completely consume the
buffer layer 310. This is actually an exemplary embodiment, as the
barrier layer 410 does not have a chance to interact with the
germanium of the first substrate portion 213, and thus, the
germanium pile up is reduced, if not eliminated.
[0040] Turning now to FIG. 6, illustrated is a cross-sectional view
of the partially completed semiconductor device 200 illustrated in
FIG. 5 after forming a well region 610 within the substrate 210.
The well region 610, in light of the P-type substrate 210, would
more than likely contain an NBtype dopant. For example, the well
region 610 would likely be doped with an NBtype dopant dose ranging
from about 1E13 atoms/cm.sup.2 to about 1E14 atoms/cm.sup.2 and at
an energy ranging from about 100 keV to about 500 keV. This results
in the well region 610 having a peak dopant concentration ranging
from about 5E17 atoms/cm.sup.3 to about 1E19 atoms/cm.sup.3. After
completing the well region 610, the semiconductor manufacturing
process would continue in a conventional manner until a device
somewhat similar to the semiconductor device 100 of FIG. 1 was
obtained.
[0041] Referring finally to FIG. 7, illustrated is an exemplary
cross-sectional view of an integrated circuit (IC) 700
incorporating trench isolation structures 710 constructed according
to the principles of the present invention. The IC 700 may include
devices, such as transistors used to form CMOS devices, BiCMOS
devices, Bipolar devices, as well as capacitors or other types of
devices. The IC 700 may further include passive devices, such as
inductors or resistors, or it may also include optical devices or
optoelectronic devices. Those skilled in the art are familiar with
these various types of devices and their manufacture. In the
particular embodiment illustrated in FIG. 7, the IC 700 includes
transistor devices 715 located between the trench isolation
structures 710. As is illustrated in FIG. 7, dielectric layers 720
may be located over the trench isolation structures 710 and
transistor devices 715. Additionally, interconnect structures 730
are located within the dielectric layers 720 to interconnect
various devices, thus, forming the operational integrated circuit
700.
[0042] Although the present invention has been described in detail,
those skilled in the art should understand that they can make
various changes, substitutions and alterations herein without
departing from the spirit and scope of the invention in its
broadest form.
* * * * *