U.S. patent application number 12/062068 was filed with the patent office on 2008-08-07 for structure and method for forming asymmetrical overlap capacitance in field effect transistors.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Haining Yang.
Application Number | 20080185662 12/062068 |
Document ID | / |
Family ID | 37910389 |
Filed Date | 2008-08-07 |
United States Patent
Application |
20080185662 |
Kind Code |
A1 |
Yang; Haining |
August 7, 2008 |
STRUCTURE AND METHOD FOR FORMING ASYMMETRICAL OVERLAP CAPACITANCE
IN FIELD EFFECT TRANSISTORS
Abstract
A method for forming asymmetric spacer structures for a
semiconductor device includes forming a spacer layer over at least
a pair of adjacently spaced gate structures disposed over a
semiconductor substrate. The gate structures are spaced such that
the spacer layer is formed at a first thickness in a region between
the gate structures and at a second thickness elsewhere, the second
thickness being greater than said first thickness. The spacer layer
is etched so as to form asymmetric spacer structures for the pair
of adjacently spaced gate structures.
Inventors: |
Yang; Haining; (Wappingers
Falls, NY) |
Correspondence
Address: |
CANTOR COLBURN LLP - IBM FISHKILL
20 Church Street, 22nd Floor
Hartford
CT
06103
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
37910389 |
Appl. No.: |
12/062068 |
Filed: |
April 3, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11163165 |
Oct 7, 2005 |
|
|
|
12062068 |
|
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Current U.S.
Class: |
257/386 ;
257/E21.427; 257/E21.62; 257/E21.626 |
Current CPC
Class: |
H01L 29/66659 20130101;
H01L 29/7835 20130101; H01L 29/6656 20130101; H01L 21/823468
20130101; H01L 21/26586 20130101; H01L 21/823425 20130101; H01L
29/6659 20130101 |
Class at
Publication: |
257/386 ;
257/E21.427 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Claims
1. A semiconductor device, comprising: at least a pair of field
effect transistor (FET) structures including a pair of adjacently
spaced gate structures formed over a semiconductor substrate; each
of said pair of FET structures having a pair of asymmetric spacer
structures adjacent sidewalls thereof; wherein inner spacer
structures located in a region between said pair of gate structures
are thinner than outer spacer structures located on the outside of
said pair of gate structures.
2. The device of claim 1, wherein said asymmetric spacer structures
further comprise offset spacers used in the definition of halo and
extension implantation regions.
3. The device of claim 1, further comprising extensions implanted
within said substrate, wherein said extensions corresponding to
thinner offset spacers have a longer gate overlap than said
extensions corresponding to thicker offset spacers.
4. The device of claim 1, wherein said asymmetric spacer structures
further comprise second spacers formed over offset spacers, used in
the definition of source and drain regions.
5. The device of claim 4, further comprising source and drain
regions implanted within said substrate, wherein said source
regions correspond to thinner second spacers and said drain regions
correspond to thicker second spacers.
6. The device of claim 5, wherein said source regions have shorter
extensions than said drain regions.
7. The device of claim 1, wherein a distance between said pair of
adjacently spaced gate structures is about 1 to 3 times a height of
said gate structures.
8. A field effect transistor (FET) device, comprising: a gate
structure formed over a semiconductor substrate; a first pair of
spacer structures formed on sidewalls of said gate structure; a
second pair of spacer structures formed adjacent said first pair of
spacer structures, said second pair of spacer structures having an
asymmetrical thickness with respect to one another; a source region
and extension thereof implanted on one side of said gate structure;
and a drain region and extension thereof implanted on the other
side of said gate structure; wherein the extension of said source
region has a different length than the extension of said drain
region, in accordance with said asymmetrical thickness of said
second pair of spacer structures.
9. The FET device of claim 8, wherein said source region
corresponds to a thinner one of said second pair of spacer
structures and said drain regions corresponds to a thicker one of
said second pair of spacer structures.
10. The FET device of claim 9, wherein the extension of said source
region is shorter than the extension of said drain region.
11. The FET device of claim 8, wherein said first pair of spacer
structures also have an asymmetrical thickness with respect to one
another.
12. The FET device of claim 11, wherein one of said source and
drain extensions corresponding to a thinner one of said first pair
of spacer structures has a longer gate overlap than the other of
said source and drain extensions corresponding to a thicker one of
said first pair of spacer structures.
13. The FET device of claim 12, wherein the extension of said
source region has a longer gate overlap than the extension of said
drain region.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. patent application
Ser. No. 11/163,165, filed Oct. 7, 2005, the disclosure of which is
incorporated by reference herein in its entirety.
TRADEMARKS
[0002] IBM.RTM. is a registered trademark of International Business
Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein
may be registered trademarks, trademarks or product names of
International Business Machines Corporation or other companies.
BACKGROUND
[0003] The present invention relates generally to semiconductor
device processing techniques, and, more particularly, to a
structure and method for forming asymmetrical overlap capacitance
in field effect transistors (FETs).
[0004] In the manufacture of semiconductor devices, there is a
constant drive to increase the operating speed of certain
integrated circuit devices such as microprocessors, memory devices,
and the like. This drive is fueled by consumer demand for computers
and other electronic devices that operate at increasingly greater
speeds. As a result of the demand for increased speed, there has
been a continual reduction in the size of semiconductor devices,
such as transistors. For example, in a device such as a field
effect transistor (FET), device parameters such as channel length,
junction depth and gate dielectric thickness, to name a few, all
continue to be scaled downward.
[0005] Generally speaking, the smaller the channel length of the
FET, the faster the transistor will operate. Moreover, by reducing
the size and/or scale of the components of a typical transistor,
there is also an increase in the density and number of the
transistors that may be produced on a given amount of wafer real
estate, thus lowering the overall cost per transistor as well as
the cost of integrated circuit devices incorporating such
transistors.
[0006] Unfortunately, reducing the channel length of a transistor
also increases "short channel" effects, as well as "edge effects"
that are relatively unimportant in long channel transistors. One
example of a short channel effect includes, among other aspects, an
increased drain to source leakage current when the transistor is
supposed to be in the "off" or non-conductive state, due to an
enlarged depletion region relative to the shorter channel length.
In addition, one of the edge effects that may also adversely
influence transistor performance is what is known as Miller
capacitance. The Miller capacitance is a parasitic overlap
capacitance (C.sub.ov) that arises as a result of the doped
polycrystalline silicon gate electrode and gate dielectric that
(almost invariably) overlaps with a conductive portion of the more
heavily doped source/drain regions and/or the less heavily doped
source/drain extension (SDE) regions (if present) of the FET.
[0007] Moreover, as transistor dimensions continue to scale down,
the gate to source/drain extension overlap needs to be kept
relatively constant so that drive current can be maintained. For
example, a minimum of about 20 nm/side of overlap is necessary to
prevent transistor drive current (I.sub.dsat) degradation. When an
overlap is too small, a high resistance region will be created
between the extension and the channel. As devices become smaller,
the source extension to drain extension distance becomes narrower,
resulting in a severe punchthrough problem.
[0008] Accordingly, it would be desirable to be able to fabricate
an FET device that maintains a low series resistance between the
gate and the source of the device, while at the same time
minimizing adverse consequences such as short channel effects, hot
carrier effects, punchthrough and parasitic Miller capacitance
formed by excessive gate to drain overlap.
SUMMARY
[0009] The foregoing discussed drawbacks and deficiencies of the
prior art are overcome or alleviated by a method for forming
asymmetric spacer structures for a semiconductor device. In an
exemplary embodiment, the method includes forming a spacer layer
over at least a pair of adjacently spaced gate structures disposed
over a semiconductor substrate. The gate structures are spaced such
that the spacer layer is formed at a first thickness in a region
between the gate structures and at a second thickness elsewhere,
the second thickness being greater than said first thickness. The
spacer layer is etched so as to form asymmetric spacer structures
for the pair of adjacently spaced gate structures.
[0010] In another embodiment, a method for forming field effect
transistor (FET) structures for a semiconductor device includes
forming at least a pair of adjacently spaced gate structures over a
semiconductor substrate, and forming a spacer layer over the
adjacently spaced gate structures. The gate structures are spaced
such that the spacer layer is formed at first thickness in a region
between the gate structures and at a second thickness elsewhere,
the said second thickness being greater than said first thickness.
The spacer layer is etched so as to form asymmetric spacer
structures adjacent sidewalls of the pair of adjacently spaced gate
structures, and the substrate is implanted with doped regions
having asymmetric characteristics in accordance with the asymmetric
spacer structures.
[0011] In still another embodiment, a method for forming field
effect transistor (FET) structures for a semiconductor device
includes forming at least a pair of adjacently spaced gate
structures over a semiconductor substrate, forming offset spacers
adjacent sidewalls of the pair of adjacently spaced gate
structures, and forming extension regions in the substrate. A
second spacer layer is formed over the offset spacers, the gate
structures and the substrate. The second spacer layer is subjected
to a single, angled ion implantation of a neutral species, the
angled ion implantation originating from a single direction. The
second spacer layer is etched, wherein portions of the second
spacer layer subjected to said angled ion implantation are etched
at a faster rate than unexposed portions thereof, thereby forming
asymmetrical second spacers adjacent the offset spacers. The
substrate is then implanted with source and drain regions.
[0012] In still another embodiment, a field effect transistor (FET)
device, includes a gate structure formed over a semiconductor
substrate, a first pair of spacer structures formed on sidewalls of
the gate structure, and a second pair of spacer structures formed
adjacent the first pair of spacer structures, the second pair of
spacer structures having an asymmetrical thickness with respect to
one another. A source region and extension thereof is implanted on
one side of the gate structure, and a drain region and extension
thereof is implanted on the other side of the gate structure. The
extension of the source region has a different length than the
extension of the drain region, in accordance with said asymmetrical
thickness of the second pair of spacer structures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Referring to the exemplary drawings wherein like elements
are numbered alike in the several Figures:
[0014] FIGS. 1 through 3 are a series of a cross sectional views
illustrating the formation of asymmetrical source and drain overlap
regions in an FET device, in accordance with an exemplary
embodiment of the invention;
[0015] FIGS. 4 through 7 and FIG. 9 are a series of a cross
sectional views illustrating the formation of asymmetrical source
and drain extension regions in an FET device, in accordance with an
alternative embodiment of the invention;
[0016] FIG. 8 is an exemplary SEM image of a device formed in
accordance with the processing step shown in FIG. 7;
[0017] FIG. 10 is an exemplary SEM image of a portion of an SRAM
cell having asymmetric spacers;
[0018] FIGS. 11 through 14 are a series of a cross sectional views
illustrating the formation of asymmetrical source and drain overlap
regions in an FET device, in accordance with an alternative
embodiment of the invention; and
[0019] FIGS. 15 through 20 are a series of a cross sectional views
illustrating the formation of asymmetrical source and drain
extension regions in an FET device, in accordance with still
another embodiment of the invention.
DETAILED DESCRIPTION
[0020] Disclosed herein is a method and structure for reducing
overlap capacitance in field effect transistors (FETs). In a
conventional FET fabrication process, the spacer structures formed
on opposite sides of the gate conductor are generally symmetrical,
such that subsequently formed source and drain extensions have the
same amount of overlap with respect to the gate. However, because
the transistor drive current is primarily controlled by the amount
of source side overlap (i.e., gate to source resistance), the
amount of drain side overlap can still be reduced without adversely
impacting drive current. On the other hand, the reduction in gate
to drain overlap is beneficial in terms of short channel effects,
punchthrough, hot carrier effects and parasitic capacitance, for
example.
[0021] Furthermore, as device dimensions shrink, the extension
resistance becomes dominant. A shorter source side extension (as a
result of a narrow spacer width) will reduce the series resistance
and improve device performance, without also causing problems such
as hot carrier effects, since the drain side extension (as a result
of not reducing the spacer width) is still maintained at an
appropriate length. This is in contrast to conventionally formed
symmetrical extensions for the source and drain sides, which in
turn result in symmetrical source and drain extension lengths.
[0022] Accordingly, as described in further detail herein, the
disclosed invention embodiments utilize various fabrication
techniques to produce asymmetric spacer structures that in turn
result in source and drain extension having long and short
overlaps, as well as long and short extensions themselves.
[0023] Referring initially to FIGS. 1 through 3, there is shown a
series of a cross sectional views illustrating the formation of
asymmetrical source and drain overlap regions for a pair of FET
devices 100, in accordance with an exemplary embodiment of the
invention. In particular, FIG. 1 illustrates a pair of adjacent
gate conductors 102 formed over a semiconductor substrate 104
(e.g., silicon), with the gates 102 being formed on corresponding
gate oxide layers 106. Shallow trench isolation (STI) structures
108 are also illustrated for electrically isolating individual
devices from one another on the substrate 104. As the basic FET
structures are well known to one skilled in the art, certain
features such as the STIs 108 and gate oxide layers 106 are not
discussed in further detail herein.
[0024] As is also shown in FIG. 1, a spacer layer 130 of
non-uniform thickness is formed over a pair of gate structures 102.
The embodiment of FIG. 1 makes use of two neighboring gates in
close proximity (e.g., a separation therebetween of about 1 to 3
times the gate height). By selectively tuning the deposition
parameters in forming the spacer layer 130, a thinner film will be
formed over the region between the two gates with respect to the
regions on the outside of the gates. As such, when the spacer layer
130 is patterned and etched, the asymmetric spacers 114a, 114b will
result from the constant etch rate of a layer of non-uniform
thickness, as illustrated in FIG. 2.
[0025] Following the formation of the asymmetrical spacers, FIG. 3
illustrates a halo and extension implantation step in accordance
with standard device processing. After an anneal to drive the
implanted dopant materials, it is seen that the extensions 116
corresponding to the thinner spacers 114b have longer overlaps than
the extensions 118 corresponding to the thicker spacers 114a. In
other words, the "long overlap" extensions 116 extend further
beneath the gate than do the "short overlap" extensions 118. In a
preferred embodiment, the source terminal of the FET structures
will be located at the long overlap extension side of the gate (to
maintain drive current) while the drain terminal is located at the
short overlap extension side of the gate (to reduce overall overlap
capacitance and improve short channel effects).
[0026] The principles of asymmetric spacer formation through
non-uniform layer formation may also be applied during the
formation of the deep source and drain regions as well. FIGS. 4
through 7 and FIG. 9 are a series of a cross sectional views
illustrating the formation of asymmetrical source and drain
extension regions in an FET device, in accordance with another
embodiment of the invention. Beginning in FIG. 4, offset spacers
114 are initially formed over the FET gate structures.
[0027] The spacers 114 may be symmetrical (i.e., substantially
equal thickness on both sides of the gate) as in a conventional
process or, alternatively, the spacers 114 could be formed
asymmetrically as shown in FIG. 2. For purposes of illustration,
the offset spacers 114 are depicted as symmetric in the present
sequence. FIG. 5 illustrates a halo and extension implantation step
in accordance with standard device processing, followed by an
anneal to diffuse the implanted dopant materials. For symmetrical
offset spacers 114, the resulting extensions 120 on both sides of
the gates will have substantially equal overlaps. On the other
hand, if the spacers 114 are formed in accordance with the
processing shown in FIGS. 1-2, then asymmetrical extensions will
appear as shown in FIG. 3.
[0028] As then shown in FIG. 6, a non-uniform second spacer layer
132 (e.g., Si.sub.3N.sub.4) is formed over the device. Similar to
the embodiment of FIG. 1, the second spacer layer 132 (given a
sufficiently close distance between gates and properly tuned
process conditions) will be formed thinner in the region between
the gates, and thicker in the regions outside the gates. Once the
second spacer layer 132 is patterned and etched in FIG. 7, the
asymmetric spacers 124a, 124b are formed. By way of illustration,
FIG. 8 is an exemplary SEM image of a device formed in accordance
with the processing step shown in FIG. 7.
[0029] Through the formation of the asymmetric spacers 124a, 124b,
the source/drain ion implantation step shown in FIG. 9 results in
extensions with different lengths. More specifically, the
extensions 120a on the outside of the gates are longer in
comparison to the extensions 120b between the gates. This is due to
the fact that the deep source/drain implant comes closer to the
gate where the second set of spacers is thinner, thus shortening
the extension regions formed in FIG. 5. With such shorter
extensions, there is a lower resistance to carriers (e.g.,
electrons or holes). In such an embodiment, it would be practical
to have a common source terminal located between the gates to
reduce the series resistance, while the drain terminals are located
outside the gates where the extensions are longer.
[0030] One suitable example of such an application could be the
PFET device pair of an SRAM cell, which has the source terminals
thereof connected to the supply voltage (V.sub.DD). FIG. 10 is an
exemplary SEM image of a portion of an SRAM cell having asymmetric
spacers, similar to the embodiment shown in FIG. 9. As will be
noted, the thinner spacers are located between the two gates.
[0031] FIGS. 11 through 14 illustrate another technique for forming
asymmetric spacers, in accordance with a further embodiment of the
invention. As with the previous embodiments discussed above, FIG.
11 illustrates a pair of gate conductors 102 formed over a
semiconductor substrate 104, gate oxide layers 106 and STI
structures 108. In addition, a spacer layer 110 (e.g., oxide, TEOS,
silicon nitride) is formed over the devices 100 for the purpose of
forming spacers prior to dopant implantation.
[0032] Conventionally, the spacer layer 110 of FIG. 11 would then
be patterned and uniformly etched to result in substantially
symmetric spacers along the sidewalls of the gate conductors 102.
However, as shown in FIG. 12, the wafer is then subjected to an
angled ion implantation (arrows 112) of a neutral dopant species
such as germanium (Ge) or xenon (Xe), for example. This results in
the spacer layer 110, on one side of the gate structures, having
receiving the angled ion implant. In an exemplary embodiment, the
implant angle may be on the order from about 10 degrees to about 35
degrees. The effect of such an implant is to increase the etch rate
of implanted portions of the spacer layer 110 with respect to the
remainder of the layer. Thus, when the implanted spacer layer 110
is subsequently patterned and etched, as shown in FIG. 13, each
gate is left with a pair of spacers 114a, 114b, wherein the spacers
114b on the implanted side of the gate are thinner (i.e.,
asymmetrical) with respect to the spacers 114a on the non-implanted
side of the gate.
[0033] Following the formation of the asymmetrical spacers, FIG. 14
illustrates a halo and extension implantation step to form the
extensions having longer and shorter overlaps 116, 118, similar to
the structure of FIG. 3. However, whereas the longer overlaps 116
of FIG. 3 are located on the inside of the gates, the longer
overlaps 116 of FIG. 14 are located on the right side of the
gates.
[0034] The principles of asymmetric spacer formation through ion
implantation may also be applied during the formation of the source
and drain regions as well. FIGS. 15 through 20 are a series of a
cross sectional views illustrating the formation of asymmetrical
source and drain extension regions in an FET device, in accordance
with another embodiment of the invention. Beginning in FIG. 15, the
FET structures are shown after the formation of offset spacers 114.
As with FIG. 4, the offset spacers 114 may either by symmetrically
formed or asymmetrically formed prior to the halo/extension ion
implant step of FIG. 5.
[0035] FIG. 16 illustrates a halo and extension implantation step
in accordance with standard device processing, followed by an
anneal to diffuse the implanted dopant materials. For symmetrical
offset spacers, the resulting extensions 120 on both sides of the
gates will have substantially equal overlaps. On the other hand, if
the spacers 114 are formed in accordance with the processing shown
in FIGS. 12-13, then the extensions 120 will appear as shown in
FIG. 14. In either case, a second spacer layer 122 (e.g.,
Si.sub.3N.sub.4) is then formed over the device as shown in FIG.
17.
[0036] Then, as shown in FIG. 18, the second spacer layer 122 is
subjected to an angled ion implantation (arrows 112) of a neutral
dopant species, in a manner similar to that discussed in the
previous embodiment. Again, this has the effect of increasing the
etch rate of the implanted portions of the layer 122. Thus, when
the layer 122 is patterned and etched as shown in FIG. 19, a second
set of spacers 124a, 124b is formed over the first set of offset
spacers 114. Regardless of whether the first set of offset spacers
114 is symmetric or asymmetric, the second set of spacers will in
fact be asymmetric due to the angled implantation shown in FIG. 18.
In particular, the non-implanted side of the gate structures
include thicker spacers 124a, while the implanted side of the gate
structure includes thinner spacers 124b.
[0037] As finally illustrated in FIG. 20, the wafer is then
subjected to a (deep) source/drain implantation in accordance with
conventional process doping. However, on the side of the gates
corresponding to the thinner spacers 124b, the resulting extensions
120b that remain after the deep source/drain implant become shorter
in length than the extensions 120a on the side of the gates
corresponding to the thicker spacers 124a. Thus, in a preferred
embodiment, the source side of the FETs is located at the sides of
the gate corresponding to the thinner spacers 124b. In contrast,
the drain side extensions are still maintained at a certain length
in order to prevent hot carrier effects.
[0038] Through the use of an angled, neutral dopant implantation
step in order to increase the etch rate of a spacer layer, an FET
device having asymmetrical spacer thicknesses may be achieved. This
in turn allows for extensions with long/short overlaps, as well as
longer and shorter extensions themselves. However, additional
methods are also contemplated that will result in the asymmetric
spacers such as discussed above.
[0039] While the invention has been described with reference to a
preferred embodiment or embodiments, it will be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted for elements thereof without departing from the
scope of the invention. In addition, many modifications may be made
to adapt a particular situation or material to the teachings of the
invention without departing from the essential scope thereof.
Therefore, it is intended that the invention not be limited to the
particular embodiment disclosed as the best mode contemplated for
carrying out this invention, but that the invention will include
all embodiments falling within the scope of the appended
claims.
* * * * *