U.S. patent application number 12/055852 was filed with the patent office on 2008-07-24 for techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effects.
Invention is credited to Barry Lee Dorfman, Thomas Edward Rosser, Jeffrey Paul Soreff.
Application Number | 20080177517 12/055852 |
Document ID | / |
Family ID | 32849754 |
Filed Date | 2008-07-24 |
United States Patent
Application |
20080177517 |
Kind Code |
A1 |
Dorfman; Barry Lee ; et
al. |
July 24, 2008 |
TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES
INCLUDING TRANSISTOR GATE CAPACITANCE LOADING EFFECTS
Abstract
Techniques for modeling delay and transition times of logical
circuit blocks including transistor gate capacitance loading
effects provides improved simulation of logical circuit block
transition times and delay times. The non-linear behavior of
transistor gates of other logical circuit block inputs that are
connected to the logical circuit block output is taken into account
by a transition time function and a delay time function that are
each separately dependent on static capacitance and transistor gate
capacitance and can be used to determine logical circuit block
timing and output performance. A separate N-channel and P-channel
gate capacitance may also be used as inputs to the transition time
and delay time functions to provide further improvement, or a ratio
of N-channel to P-channel capacitances may alternatively be used as
input to the transition time and delay time functions.
Inventors: |
Dorfman; Barry Lee; (Austin,
TX) ; Rosser; Thomas Edward; (Austin, TX) ;
Soreff; Jeffrey Paul; (Poughkeepsie, NY) |
Correspondence
Address: |
IBM CORPORATION (MH);c/o MITCH HARRIS, ATTORNEY AT LAW, L.L.C.
P.O. BOX 515
LAKEMONT
GA
30552-0515
US
|
Family ID: |
32849754 |
Appl. No.: |
12/055852 |
Filed: |
March 26, 2008 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10366439 |
Feb 13, 2003 |
|
|
|
12055852 |
|
|
|
|
Current U.S.
Class: |
703/2 |
Current CPC
Class: |
G06F 30/367
20200101 |
Class at
Publication: |
703/2 |
International
Class: |
G06F 17/11 20060101
G06F017/11 |
Claims
1. A method for modeling, in a computer system, the behavior of a
logical circuit block, the method comprising: first calculating in
said computer system a transition time of said logical circuit
block as a first mathematical function of a transistor gate
capacitance of one or more logical circuit inputs connected to an
output of said logical circuit block and a static load capacitance
value, wherein said first mathematical function is separately
dependent on said transistor gate capacitance and said static load
capacitance value; second calculating in said computer system a
delay time of said logical circuit block as a second mathematical
function of said transistor gate capacitance and said static load
capacitance value, wherein said second mathematical function is
separately dependent on said transistor gate capacitance and said
static load capacitance value, and wherein coefficients of said
first and second mathematical functions with respect to said
transistor gate capacitance are determined in conformity with a
variation of said transistor gate capacitance with respect to
transistor gate voltage; and displaying by said computer system, a
result of at least one of said first and second calculating.
2. The method of claim 1, wherein said first and second
mathematical functions are functions of a total capacitance and a
ratio of said transistor gate capacitance to a total capacitance
connected to said output of said logical circuit block, and wherein
said method further comprises: first computing said transistor gate
capacitance by multiplying said total capacitance by said ratio;
and second computing said static capacitance by subtracting said
transistor gate capacitance from said total capacitance.
3. The method of claim 1, further comprising: first computing a
first capacitance for modeling one or more N-channel devices
connected to said output of said logical circuit block; second
computing a second capacitance for modeling one or more P-channel
devices connected to said output of said logical circuit block, and
wherein said first and second mathematical functions are further
functions of said first and second capacitances, whereby loading
effects of said N-channel and P-channel devices are separately
accounted for in said first and second calculating.
4. The method of claim 3, further comprising: first totaling a
first plurality of gate capacitances of said N-channel devices to
determine said first capacitance; and second totaling a second
plurality of gate capacitances of said P-channel devices to
determine said first capacitance.
5. The method of claim 1, wherein said first and second
mathematical functions are further functions of a ratio of a first
capacitance of one or more N-channel devices connected to said
output of said logical circuit block and a second capacitance of
one or more P-channel devices connected to said output of said
logical circuit block.
6. A workstation computer system including a memory for storing
program instructions and data, and a processor for executing said
program instructions, and wherein said program instructions
comprise program instructions for: first calculating a transition
time of said logical circuit block as a first mathematical function
of a transistor gate capacitance of one or more logical circuit
inputs connected to an output of said logical circuit block and a
static load capacitance value, wherein said first mathematical
function is separately dependent on said transistor gate
capacitance and said static load capacitance value, second
calculating delay time of said logical circuit block as a second
mathematical function of said transistor gate capacitance and said
static load capacitance value, wherein said second mathematical
function is separately dependent on said transistor gate
capacitance and said static load capacitance value, and wherein
coefficients of said first and second mathematical functions with
respect to said transistor gate capacitance are determined in
conformity with a variation of said transistor gate capacitance
with respect to transistor gate voltage, and displaying a result of
at least one of said first and second calculating.
7. The workstation computer system of claim 6, wherein said first
and second mathematical functions are functions of a total
capacitance and a ratio of said transistor gate capacitance to a
total capacitance connected to said output of said logical circuit
block, and wherein program instructions further comprise program
instructions for: first computing said transistor gate capacitance
by multiplying said total capacitance by said ratio; and second
computing said static capacitance by subtracting said transistor
gate capacitance from said total capacitance.
8. The workstation computer system of claim 6, wherein said program
instructions further comprise program instructions for: first
computing a first capacitance for modeling one or more N-channel
devices connected to said output of said logical circuit block;
second computing a second capacitance for modeling one or more
P-channel devices connected to said output of said logical circuit
block, and wherein said first and second mathematical functions are
further functions of said first and second capacitances, whereby
loading effects of said N-channel and P-channel devices are
separately accounted for in said first and second calculating.
9. The workstation computer system of claim 8, wherein said program
instructions further comprise program instructions for: first
totaling a first plurality of gate capacitances of said N-channel
devices to determine said first capacitance; and second totaling a
second plurality of gate capacitances of said P-channel devices to
determine said first capacitance.
10. The workstation computer system of claim 6, wherein said first
and second mathematical functions are further functions of a ratio
of a first capacitance of one or more N-channel devices connected
to said output of said logical circuit block and a second
capacitance of one or more P-channel devices connected to said
output of said logical circuit block.
11. A computer program product comprising a computer-readable
storage medium encoding program instructions and data for execution
on a general-purpose computer system, wherein said program
instructions comprise program instructions for: first calculating a
transition time of said logical circuit block as a first
mathematical function of a transistor gate capacitance of one or
more logical circuit inputs connected to an output of said logical
circuit block and a static load capacitance value, wherein said
first mathematical function is separately dependent on said
transistor gate capacitance and said static load capacitance value,
second calculating delay time of said logical circuit block as a
second mathematical function of said transistor gate capacitance
and said static load capacitance value, wherein said second
mathematical function is separately dependent on said transistor
gate capacitance and said static load capacitance value, and
wherein coefficients of said first and second mathematical
functions with respect to said transistor gate capacitance are
determined in conformity with a variation of said transistor gate
capacitance with respect to transistor gate voltage, and displaying
a result of at least one of said first and second calculating.
12. The computer program product of claim 11, wherein said first
and second mathematical functions are functions of a total
capacitance and a ratio of said transistor gate capacitance to a
total capacitance connected to said output of said logical circuit
block, and wherein program instructions further comprise program
instructions for: first computing said transistor gate capacitance
by multiplying said total capacitance by said ratio; and second
computing said static capacitance by subtracting said transistor
gate capacitance from said total capacitance.
13. The computer program product of claim 11, wherein said program
instructions further comprise program instructions for: first
computing a first capacitance for modeling one or more N-channel
devices connected to said output of said logical circuit block;
second computing a second capacitance for modeling one or more
P-channel devices connected to said output of said logical circuit
block, and wherein said first and second mathematical functions are
further functions of said first and second capacitances, whereby
loading effects of said N-channel and P-channel devices are
separately accounted for in said first and second calculating.
14. The computer program product of claim 13, wherein said program
instructions further comprise program instructions for: first
totaling a first plurality of gate capacitances of said N-channel
devices to determine said first capacitance; and second totaling a
second plurality of gate capacitances of said P-channel devices to
determine said first capacitance.
15. The computer program product of claim 11, wherein said first
and second mathematical functions are further functions of a ratio
of a first capacitance of one or more N-channel devices connected
to said output of said logical circuit block and a second
capacitance of one or more P-channel devices connected to said
output of said logical circuit block.
Description
[0001] The present Application is a Division of U.S. patent
application Ser. No. 10/366,439 filed on Feb. 13, 2003.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention is related to circuit modeling methods
and software, and more particularly to logic circuit modeling
methods and software that compute loading effects on logical
circuit block signal performance.
[0004] 2. Description of Related Art
[0005] Circuit modeling methods, typically implemented in software
tools that simulate the performance of circuits for design
verification provide a mechanism for optimizing and ensuring proper
performance of Integrated Circuits (IC) including Very-Large-Scale
Integrated (VLSI) circuits. Logical circuits are typically
represented as circuit blocks having a modeled response to input
state changes. In response to an input change, a delay time and a
transition time are generally used to generate the output voltage
of the logical circuit block within the model.
[0006] The transition time and delay time of a logical circuit
block vary over various parameters of the circuit block, such as
output transistor size, power supply voltage and temperature. The
transition time and delay time may also be modeled in terms of
input voltage swing and transition time. Existing models take all
or some of the above factors into account in order to determine the
output signal produced by a logical circuit block.
[0007] Additionally, output loading characteristics have a large
effect on the output signal and various techniques have been
developed within present circuit models and modeling software to
take loading effects into account. The simplest model used in
present simulation tools is a lumped capacitance coupled to the
output of the logical circuit block. The lumped capacitance
represents all of the loading capacitance connected to the output
of the logical circuit block, and may in the simplest case be equal
to all of the capacitance connected to the logical circuit block
output, or may be a capacitance value determined by sophisticated
models of the interconnect resistance and capacitances at various
points in the circuits connected to the output of the logical
circuit block.
[0008] The above-referenced patent application describes a
pi-network model that includes two capacitors determined from
distributed capacitances connected to the output of a logical
circuit block, along with the effects of the wire resistances
connecting the capacitances. The pi-network model provides an
improved calculation of the effects of distributed capacitances
connected to the output of the logical circuit block.
[0009] However, present circuit models have progressively reduced
accuracy as the logical circuit block output loading capacitance
becomes dominated by transistor gate capacitances. Since the load
on the output of a logical circuit block is typically at least one
logical gate input connected via a typically low-resistance
interconnect, the transistor gate capacitance, which is not in
actuality a linear capacitance but a non-linear capacitance that
varies with output signal voltage, has a significant impact on the
logical circuit block transition time and delay time. The
non-linear nature of the loading gate capacitances causes the
transition time and delay time to diverge from values predicted by
a simple capacitive model, making a simple shunt capacitance load
model or fixed capacitive network load model ineffective for
predicting both the transition time and delay time of a logical
circuit block.
[0010] However, modeling gate capacitance loading effects on a
circuit output is a complicated simulation task, as logical circuit
block performance must be modeled over the complete range of device
sizes that are encountered in actual designs. Transistor device
size (and hence gate capacitance) is typically a static value in
designs simulated by circuit simulation tools such as SPICE.
[0011] Therefore, it would be desirable to provide modeling methods
and modeling software that accurately predict the performance of a
logical circuit block as the logical circuit block output load
varies between predominantly transistor gate capacitance and
predominantly wire capacitance. It would further be desirable to
predict non-linear effects of logical circuit block loading on
logical circuit block transition time and delay time. It would
further be desirable to provide a method for determining
characteristics of the logical circuit block without having to
model the logical circuit block over loading circuit transistor
device size changes.
SUMMARY OF THE INVENTION
[0012] The above objectives of accurately predicting the
performance of a logical circuit block as the logical circuit block
output load varies between predominantly transistor gate
capacitance and predominantly wire capacitance and predicting
non-linear effects of logical circuit block loading on logical
circuit block transition time and delay time are accomplished in a
method for modeling logical circuit block behavior.
[0013] The method may be embodied in a computer system executing
program instructions for carrying out the steps of the method and
may further be embodied in a computer program product containing
program instructions in computer-readable form for carrying out the
steps of the method.
[0014] The method computes a transition time of a logical circuit
block output as a first mathematical function of transistor gate
capacitance connected to the output of the logical circuit block
and a delay time as a second mathematical function of the
transistor gate capacitance. The first and second functions may
also include dependence on N-channel and P-channel gate
capacitances separately or dependence on a N-channel to P-channel
capacitance ratio. The first and second functions also include
dependence on a "static capacitance", a term used here to represent
wire and pin capacitances, etc. that are linear, separate from the
transistor gate capacitance.
[0015] The method also includes a technique for determining the
effects of gate capacitance loading on transition times and delay
times to determine coefficients of the first and second
mathematical functions above. A logical circuit block output
including loading transistor(s) and a variable static capacitance
are simulated using a circuit simulation tool such as SPICE. A
current controlled current source is used to shunt output current
in response to a measured current entering the loading
transistor(s), providing a means for changing the apparent size of
(or effectively removing) the transistors from the model without
changing transistor device sizes.
[0016] The foregoing and other objectives, features, and advantages
of the invention will be apparent from the following, more
particular, description of the preferred embodiment of the
invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 is a pictorial diagram of a workstation computer
system in which methods in accordance with an embodiment of the
present invention are performed.
[0018] FIG. 2 is a schematic diagram of a portion of a logical
integrated circuit model in accordance with an embodiment of the
present invention.
[0019] FIG. 3 is a schematic diagram of a measurement circuit that
can be used to determine characteristics of a circuit model in
accordance with an embodiment of the present invention.
[0020] FIG. 4 is a flow chart of a method in accordance with an
embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
[0021] Referring to the figures, and particularly to FIG. 1, a
workstation computer system, in which methods according to an
embodiment of the present invention are performed, is depicted. A
workstation computer 12, having a processor 16 coupled to a memory
17, for executing program instructions from memory 17, wherein the
program instructions include program instructions for executing one
or more methods in accordance with an embodiment of the present
invention.
[0022] Workstation computer 12 is coupled to a graphical display 13
for displaying program output such as simulation results and
circuit structure input and verification programs implementing
embodiments of the present invention. Workstation computer 12 is
further coupled to input devices such as a mouse 15 and a keyboard
14 for receiving user input. Workstation computer may be coupled to
a public network such as the Internet, or may be coupled to a
private network such as the various "intra-nets", or may not be
connected to any network at all, and software containing program
instructions embodying methods in accordance with embodiments of
the present invention may be located on remote computers or locally
within workstation computer 12.
[0023] Referring now to FIG. 2, a portion of an integrated circuit
is depicted to illustrate a model in accordance with an embodiment
of the present invention. Logic block L1 is simulated to produce an
output voltage waveform V.sub.o (shown in balloon 11), calculated
according to the illustrated model as a response to input voltage
waveform V.sub.i (shown in balloon 10). The illustrated model uses
a delay time T.sub.d and transition time T.sub.r to determine a
linear voltage response to V.sub.i. The 50% voltage point of output
signal V.sub.o is set at interval T.sub.d after the 50% voltage
point of input signal V.sub.i and the transition time T.sub.r
determines the slope of output voltage waveform V.sub.o. While this
linear waveform model is of a type in common use and is sufficient
to illustrate the techniques of the present invention, the model of
the present invention may be used with other types of waveform
modeling including higher-order waveshape models or piecewise
linear models that compute an output waveform using calculations
performed on sampled input voltage waveform points.
[0024] All of the illustrations and formulations in the following
description are directed toward a rising transition time and a
delay time. Actual models will generally include separate falling
transition times and may include two or more delay times--for
falling edges, rising edges and the various transfer functions of
the circuit. The model of the present invention is equally
applicable to rising transition time and falling transition time
modeling either separately computed or provided by one formula and
it should be understood that they can be used interchangeably with
respect to the discussion hereinafter, excepting the actions of
transistors described with respect to a particular signal edge,
etc.
[0025] The model of the present invention provides the mathematical
functions that calculate T.sub.r and T.sub.d in conformity with a
multitude of circuit variables. Generally the mathematical
functions employed to compute T.sub.r and T.sub.d are functions of
input voltage swing and slew rate, power supply voltages,
temperature, device sizes and types. The model also includes
response to various and varying load conditions and the present
invention concerns the accurate modeling of load response by
including a model of response to non-linear capacitance provided by
gates of transistors (N2,P2,N3,P3) that are connected to the
logical circuit block (L1) output being modeled. The input
capacitance of a MOS transistor increases as the channel widens, so
that the total input capacitance of a logical gate is a complex
function of the gate voltage and depends on both devices (for a
CMOS input such as those illustrated by logical circuit blocks L2
and L3). The separate consideration of circuit response to static
capacitance C.sub.S and transistor gate capacitance provides a more
accurate model than previously used models that produce a response
only to static capacitance.
[0026] Typically, prior art models include a response only to
static capacitance which may be the total of all load capacitance
or an effective capacitance from a network that takes into account
wiring resistance, such as the pi-network model described in the
above-referenced patent application. The techniques of the present
invention may also be used with network models, but the
illustration provided herein is one in which the transition time
and delay time of a logical circuit block is modeled directly from
input variables that ignore resistance and consider only the totals
of the various capacitances.
[0027] One model in accordance with the present invention models
the response of the circuit to N-channel device gate capacitance
and a separate response to P-channel device gate capacitance. These
capacitances might be obtained by totaling all of the gate
capacitances of the N-channel devices (N2 and N3) in the connected
inputs of logical circuit blocks L2 and L3 to generate a total NFET
gate capacitance C.sub.N and all of the gate capacitances of the
P-channel devices (P2 and P3) in the connected inputs of logical
circuit blocks L2 and L3 to generate a total NFET gate capacitance
Cp. The illustration depicts two inputs connected to the output of
circuit block L1, but a circuit may be loaded by any number of
connected circuit inputs and is also not restricted to a particular
configuration of circuit inputs. For example, an NMOS circuit (as
opposed to the depicted CMOS circuit) would include a single
N-channel gate connection per input.
[0028] The model also includes a response to the total of all
static shunt capacitance C.sub.S not due to the input gate
capacitances of logical circuit blocks L2 and L3, such as output
capacitances, wire capacitances and other interconnect
capacitances. The representative static capacitance is included in
the transition time and delay time model along with, but separate
from the transistor gate capacitances. The result is that the
dependence of the capacitive effect of the gate connections can be
modeled more accurately for: the two different edges of signal
transition, the device temperatures and other factors.
[0029] The model is generated by measuring (or simulating using
precise analog simulation tools) logical circuit block L1 output
behavior (transition time and delay time) at various sampling
points of the input variables (temperature, input slew rate, power
supply voltage, static load capacitance, N-channel device
transistor load capacitance, P-channel transistor gate load
capacitance (or combined gate-load capacitance), etc.) and
curve-fitting the transition time and delay time equations to the
measured data, or generating a lookup-table model of the measured
data.
[0030] The transition time and delay time equations may be
expressed as follows:
T.sub.r=f1(C.sub.S, C.sub.N, C.sub.P, . . . )
T.sub.d=f2(C.sub.S, C.sub.N, C.sub.P, . . . )
[0031] Where C.sub.S=total of all static capacitances connected to
the output of logical circuit block L1, C.sub.N=total of all
N-channel input capacitances connected, and C.sub.P=total of all
P-channel input capacitances connected. The totals may also be
adjusted; for example, the P-channel and N-channel totals may be
reduced to take into account wire resistance R.sub.W or other
effects, and the static capacitance may also be adjusted as well.
The primary feature of the models of the present invention is the
separate treatment of transistor gate capacitance.
[0032] An alternative model expresses the transition time and delay
time in terms of the ratio of N-channel to P-channel transistor
gate capacitances:
T.sub.r=f3(C.sub.S, C.sub.T, R.sub.N/P, . . . )
T.sub.d=f4(C.sub.S, C.sub.T, R.sub.N/P, . . . )
Where C.sub.T may be either of the gate capacitances or their sum
and R.sub.N/P=C.sub.N/C.sub.P.
[0033] Another alternative is to express the transistor gate
capacitance as a fraction (or a separate fraction for N-channel and
P-channel devices) of the static capacitance, yielding:
T.sub.r=f5(C.sub.S, R.sub.T/S, . . . )
T.sub.d=f6(C.sub.S, R.sub.T/S, . . . )
Where R.sub.T/S is the ratio of the transistor gate capacitances to
the static capacitances, or
T.sub.r=f7(C.sub.S, R.sub.N/S, R.sub.P/S . . . )
T.sub.d=f8(C.sub.S, R.sub.N/S, R.sub.P/S, . . . )
Where R.sub.N/S and R.sub.P/S are the ratios of the individual (N
or P) transistor gate capacitances to the static capacitances,
respectively.
[0034] In essence, all of the above models are equivalent to either
the model treating N and P channel devices together (as one lumped
transistor gate capacitance) or the model that treats them
separately. The exemplary models presented above represent a
reformulation of the delay time and transition time model in
various combinations depending on desired input variables. While
they are illustrative of the method of the present invention, they
are not intended to be exhaustive or otherwise limiting.
[0035] Referring now to FIG. 3, a circuit that may be used in an
analog simulator or for other measurement purposes to determine the
characteristics of the model for transition time and delay time is
shown. A circuit simulator such as SPICE may be used to simulate
the circuit of FIG. 3, in order to determine the transition time
and delay time functions of logical circuit block L1. Loading
transistors Nx and Px have a channel width set to a convenient
value of "gate capacitance" and capacitance C.sub.X is set to
represent a typical load at the output of transistors Nx and Px.
Variable capacitor VC1 represents the static capacitance C.sub.S
and can be set to different values including zero to simulate
variation over the wire capacitance variable in the logical circuit
models. A current meter (I.sub.P,I.sub.N) is inserted into each
transistor gate circuit. The current meters can then control
current dependent shunt current source IdIs, which is used to
multiply the gate current of the transistors in order to simulate
varying the individual gate capacitances of each transistor type (N
or P channel). If shunt current IdIs is set to a value of
-1*(I.sub.P+I.sub.N), the transistors are effectively removed
leaving only capacitor VC1. If the capacitance of capacitor VC1 is
set to zero, and shunt current IdIs is set to a value of
-1*(I.sub.P-I.sub.N), then a measurement can be taken for zero wire
capacitance and, C.sub.P=0 and C.sub.N=2*NFET capacitance. In
general, if shunt current IdIs is set to a value of
(k.sub.PI.sub.P+k.sub.NI.sub.N), where k.sub.P, k.sub.N are
variable coefficients, then the P-channel transistor gate
capacitance is effectively multiplied by (1+k.sub.P) and the
N-channel transistor gate capacitance is effectively multiplied by
(1+k.sub.N), and k.sub.P and k.sub.N can be swept independently
over a range of interest without having to modify the model.
[0036] Referring now to FIG. 4, a method in accordance with an
embodiment of the present invention is depicted in a flowchart.
Timing analysis generates an input waveform for a logic transition
at an input of a first logical circuit block. The input waveform
(which may be just the 50% voltage time point) is received by the
method (step 30). Next, the method calculates the transition time
and delay time of the first logical circuit block output as a
function of circuit variables and load variables, where the load
variables include a static connected capacitance value and at least
one transistor gate capacitance value representing transistors in
the input stage of a second logical circuit block connected to the
output of the first logical circuit block (step 32). Finally, an
output voltage waveform of the first logical circuit block is
generated from the transition time and delay time of the first
logical circuit block and the input waveform (step 34).
[0037] While the invention has been particularly shown and
described with reference to the preferred embodiments thereof, it
will be understood by those skilled in the art that the foregoing
and other changes in form, and details may be made therein without
departing from the spirit and scope of the invention.
* * * * *