U.S. patent application number 11/949800 was filed with the patent office on 2008-06-19 for leadframe on heat sink (lohs) semiconductor packages and fabrication methods thereof.
This patent application is currently assigned to MEDIATEK INC.. Invention is credited to Nan-Jang Chen, Hong-Chin Lin.
Application Number | 20080142937 11/949800 |
Document ID | / |
Family ID | 39526122 |
Filed Date | 2008-06-19 |
United States Patent
Application |
20080142937 |
Kind Code |
A1 |
Chen; Nan-Jang ; et
al. |
June 19, 2008 |
LEADFRAME ON HEAT SINK (LOHS) SEMICONDUCTOR PACKAGES AND
FABRICATION METHODS THEREOF
Abstract
The invention relates to leadframe semiconductor packages
mounted on a heat-sink and fabrication thereof. A system in package
(SiP) comprises a leadframe having extension leads, configured with
divisional heat sinks serving as power and ground nets. A set of
semiconductor dies is attached by adhesive on the central region of
the lead frame. Pluralities of wire bonds electrically connect the
set of semiconductor dies to the leadframe and to the divisional
heat sinks respectively. An encapsulation encloses the leadframe,
but leaves the extension leads and the divisional heat sink
uncovered, exposing a heat dissipating surface.
Inventors: |
Chen; Nan-Jang; (Hsinchu
City, TW) ; Lin; Hong-Chin; (Taichung City,
TW) |
Correspondence
Address: |
THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LLP
600 GALLERIA PARKWAY, S.E., STE 1500
ATLANTA
GA
30339-5994
US
|
Assignee: |
MEDIATEK INC.
Hsin-Chu
TW
|
Family ID: |
39526122 |
Appl. No.: |
11/949800 |
Filed: |
December 4, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60870445 |
Dec 18, 2006 |
|
|
|
Current U.S.
Class: |
257/675 ;
257/E23.101; 438/122 |
Current CPC
Class: |
H01L 2224/73265
20130101; H01L 2924/01074 20130101; H01L 23/3107 20130101; H01L
2224/73215 20130101; H01L 2924/00014 20130101; H01L 2924/01082
20130101; H01L 2924/014 20130101; H01L 2924/351 20130101; H01L
2924/1433 20130101; H01L 2224/48247 20130101; H01L 2224/49109
20130101; H01L 23/49589 20130101; H01L 2224/4826 20130101; H01L
2224/73265 20130101; H01L 2924/01046 20130101; H01L 23/49541
20130101; H01L 2924/181 20130101; H01L 24/49 20130101; H01L
2924/19041 20130101; H01L 2924/01028 20130101; H01L 2924/14
20130101; H01L 2224/4826 20130101; H01L 2924/01029 20130101; H01L
2924/181 20130101; H01L 23/49575 20130101; H01L 2224/48091
20130101; H01L 2924/30107 20130101; H01L 2224/48091 20130101; H01L
2224/4824 20130101; H01L 2924/01006 20130101; H01L 2924/01033
20130101; H01L 2924/01087 20130101; H01L 2924/00014 20130101; H01L
2924/01023 20130101; H01L 2224/73265 20130101; H01L 2924/01047
20130101; H01L 23/4334 20130101; H01L 2924/01078 20130101; H01L
2924/00012 20130101; H01L 2224/49109 20130101; H01L 2224/32245
20130101; H01L 2224/48247 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101; H01L 2224/32245
20130101; H01L 2224/32245 20130101; H01L 2924/3011 20130101; H01L
24/48 20130101; H01L 2924/00014 20130101; H01L 2224/49109 20130101;
H01L 2924/3025 20130101; H01L 2224/4824 20130101; H01L 2924/351
20130101; H01L 2224/45099 20130101; H01L 2924/00014 20130101; H01L
2224/32245 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2224/05599 20130101; H01L 2224/48247 20130101; H01L 2924/00
20130101; H01L 2224/49109 20130101; H01L 2224/4826 20130101; H01L
2224/49109 20130101; H01L 2224/48091 20130101; H01L 2224/73215
20130101; H01L 2224/4911 20130101; H01L 2924/01013 20130101; H01L
2924/01079 20130101 |
Class at
Publication: |
257/675 ;
438/122; 257/E23.101 |
International
Class: |
H01L 23/36 20060101
H01L023/36 |
Claims
1. A system in package, comprising: a leadframe having extension
leads, configured with divisional heat sinks serving as power and
ground nets; a set of semiconductor dies, attached by adhesive on
the central region of the lead frame; a plurality of wire bonds
electrically connecting the set of semiconductor dies to the
leadframe and to the divisional heat sinks respectively; and an
encapsulation enclosing the leadframe, but leaving the extension
leads and the divisional heat sink uncovered.
2. The system in package as claimed in claim 1, wherein the set of
semiconductor dies comprises a vertically stacked pair of
semiconductor dies.
3. The system in package as claimed in claim 2, wherein the
vertically stacked pair of semiconductor dies comprises a digital
chip and an analog chip, an RF chip and a BB chip, or a DSP chip
and a memory chip.
4. The system in package as claimed in claim 1, further comprising
an interconnection section as a bridge electrically connecting the
set of semiconductor dies and the divisional heat sinks by wire
bonds.
5. The system in package as claimed in claim 1, wherein the
interconnection section is disposed crossing two adjacent
divisional heat sinks.
6. The system in package as claimed in claim 1, wherein the heat
dissipating surface of the divisional heat sinks comprises a
plurality of protrusions or bumps.
7. The system in package as claimed in claim 1, further comprising
a dielectric layer interposed between the leadframe and the
divisional heat sinks.
8. The system in package as claimed in claim 1, further comprising
passive devices on peripheral regions of the divisional heat
sinks.
9. The system in package as claimed in claim 1, further comprising
a die paddle on the central region of the lead frame for supporting
the set of semiconductor dies.
10. A fabrication method for a system in package, comprising:
assembling a leadframe having extension leads, configured with
divisional heat sinks; attaching a set of semiconductor dies by
adhesive on the central region of the lead frame; bonding wires
connecting the set of semiconductor dies to the leadframe and to
the divisional heat sinks respectively; and molding an
encapsulation layer enclosing the leadframe, but leaving the
extension leads and the divisional heat sink uncovered.
11. The fabrication method as claimed in claim 10, wherein assembly
of the leadframe comprises: providing a top metal, a dielectric
material and a bottom metal; pressing an assembly of the top metal,
a dielectric material and a bottom metal; etching the top metal to
create a leadframe with extension leads and an opening at a central
region thereof; etching bottom metal to create divisional heat
sinks; forming through holes proliferating the assembly; removing
the dielectric material within the opening; forming a solder mask
at the peripheral region of the leadframe; and electroplating a
metal on the leadframe.
12. The fabrication method as claimed in claim 10, wherein assembly
of the leadframe comprises: providing a top metal, a dielectric
material and a bottom metal; pressing an assembly of the top metal,
a dielectric material and a bottom metal; etching the top metal to
create a leadframe with extension leads and an opening with a die
paddle at a central region thereof; etching bottom metal to create
divisional heat sinks; forming through holes proliferating the
assembly; removing the dielectric material within the opening;
forming a solder mask at the peripheral region of the leadframe;
and electroplating a metal on the leadframe.
13. The fabrication method as claimed in claim 10, wherein the heat
dissipating surface of the divisional heat sinks comprises a
plurality of protrusions or bumps.
14. The fabrication method as claimed in claim 10, wherein
attachment of the set of semiconductor dies comprises vertically
stacking a pair of semiconductor dies on both sides of the central
region of the leadframe and the pair of semiconductor dies
comprises a digital chip and an analog chip, an RF chip and a BB
chip, or a DSP chip and a memory chip.
15. The fabrication method as claimed in claim 10, further
comprising mounting the system in package on a PCB.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Application No. 60/870,445 filed on Dec. 18, 2006, the entirety of
which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to semiconductor packages, and in
particular, to leadframe semiconductor packages mounted on a
heat-sink and fabrication thereof.
[0004] 2. Description of the Related Art
[0005] Requirements for faster signal transmissions are being
driven by consumer demand for electronic devices with greater
bandwidth capacity. Two main semiconductor packaging challenges
encountered with high-speed data transmissions are: 1) thermal
problems due to greater power consumption requirements; and 2)
electrical problems due to higher signal bandwidth. In order to
solve signal and power integrity (F.sub.3dB=0.35/t.sub.r) and heat
dissipation (P=C.sub.L.times.f.times.V.sub.DD.sup.2) issues,
semiconductor packaging with both lower parasitic effects and lower
costs are required for high speed integrated circuit
applications.
[0006] Conventional semiconductor quad flat packages (QFPs) are
used for low cost applications. The low cost applications require
improved power dissipation benefit from the use of drop-in heat
sink (DHS), die pad heat sink (DPH), exposed drop-in heat sink
(EDHS), or exposed pad low profile in QFP (E-PAD LQFP),
respectively. However, letting the heat sink act as a ground plane
or floating ground plane does not improve the electrical
performance effectively.
[0007] FIGS. 1A-1D are cross sections of traditional quad flat
packages with different heat sinks enhancing thermal performance.
Referring to FIG. 1A, a drop-in heat sink quad flat package
(DHS-QFP) 100a comprises a semiconductor die 110 attached on a die
pad 125 with an adhesion 120 therebetween. The die pad 125 is
mounted on a heat sink 130. The semiconductor die 110 electrically
connects leads 150 through bonding wires 140. An encapsulation 160
encloses the semiconductor die 110, the die pad 125, the heat sink
130 and wire bonding between the semiconductor chip and leads.
[0008] Alternatively, the semiconductor die 110 can be directly
mounted on the heat sink 130 with adhesion 120. The heat sink 130
can also serve as a die pad. Both ends of the heat sink 130 are
connected to the lead 150 through the polyimide tape 135, as shown
in the die pad heat sink quad flat pack (DPH-QFP) 100b in FIG. 1B.
However, the problem, of this type designed is that electrical
performance can not be improved with the heat sink acting as a
floating plane.
[0009] Referring to FIG. 1C, a bottom surface 132 of the heat sink
130 can be exposed to the outer environment as an exposed drop-in
heat sink quad flat pack (EHDS-QFP) 110c. The heat sink 130 can be
integrated with the leadframe to meet low profile requirements as
shown in an exposed pad low profile quad flat pack (E-PAD LQFP)
100d in FIG. 1D. E-PAD LQFPs are ideal for a wide range of devices,
such as microprocessors, controllers, DSPs, high speed logic,
FPGAs, PLDs, and ASICs. Applications include laptops, telecom
devices, high end audio/video devices and CPU/GUI boards.
Electrical performances can be improved with the bottom surfaces of
the heat sink acting as a ground plane.
[0010] U.S. Pat. Nos. 6,326,678 and 6,552,417, the entirety of
which is hereby incorporated by reference, disclose molded plastic
packages with heat sinks and enhanced electrical performance. FIG.
2A is a cross section of a conventional EDHS-QFP package. As shown
in FIG. 2A, a semiconductor die 211 is attached by a film of
thermally conductive epoxy 210 to a thick copper heat sink 201. An
annular ceramic ring 206 is attached by a dielectric adhesive 213
onto the heat sink 201 on one surface of a ceramic ring 206 and
onto a lead frame 205 on an opposite surface of the ceramic ring
206. Package 200 forms a transmission line for each lead in the
lead frame 205, with the heat sink 201 acting as a ground plane. In
addition, lead frame 205 includes an interposer ring 208 which
surrounds a semiconductor die 211 inside the window 212 of a
ceramic ring 206. Interposer ring 208 is separated into four
sections 208a-208d to allow independent connections to the power
and ground terminals.
[0011] FIG. 2B is a 3D view of package 200 with the plastic molding
204 removed to clearly show the lead frame 205 and the interposer
ring 208. The interposer ring sections 208a-208d are attached to
the heat sink 201 with dielectric adhesive 213. Interposer ring
sections 208a-208d are further supported by tie bars 241a-241d,
which are embedded in plastic molding 204. Lead frame 205 is
severed to provide electrically isolated leads 250. Each of the
interposer ring sections 208a-208d is wire bonded to one of the
leads 250. Further, interposer ring sections 241b and 241d, which
are dedicated for connections to a ground terminal, are
electrically connected to heat sink 201 via electrically conductive
epoxy 240. Alternatively, spot welding or other suitable mechanism
can be used to electrically connect interposer ring sections 208b
and 208d to heat sink 201. Interposer ring 208 is designed to
surround semiconductor die 211 in close proximity without being in
contact with semiconductor die 211. Consequently, very short wire
bonds to both semiconductor die 211 and leads 250 are possible.
Such wire bonds have low inductance, which, in turn, reduces the
parasitic impedances of package 200, thereby enhancing package
200's electrical performance. Because the interposer ring sections
are internal to package 200 and are accessed readily for
connections, the number of leads on lead frame 205 required for
power and ground connections is reduced, thereby effectively
increasing the available lead count of package 200. However, the
drawback of the semiconductor packages 200 is that lead inductance
is very large thereby detrimental to power integrity.
[0012] Taiwan Patent No. 1249829, the entirety of which is hereby
incorporated by reference, discloses leadframe based semiconductor
packages and fabrication methods thereof. An embedded and/or
exposed heat sink is disposed between the chip and the leads to
promote electrical and thermal performance.
[0013] FIG. 3 is a cross section of a conventional chip-on heat
sink leadframe package. Referring to FIG. 3, a chip on heat sink,
COHS-LF package 300 includes a chip 330 attached with adhesive 342
on a leadframe 336 integrated with a heat sink 360 structure. The
leadframe 336 is defined with inner leads 362 and outer leads 364.
Dielectric layer 344 is interposed between the leadframe 336 and
the heat sink 360. Bond pads 332 of the chip 330 are electrically
connected to the inner leads 362 through the bonding wires 334. An
encapsulation 338 encloses the chip 330, the heat sink 360 and wire
bonding 334 between the chip and inner leads 362. After the heat
sink 360 is attached to the front side of a chip 330, the leadframe
package is grounded to improve heat dissipation and to control
impedance of the leads. The drawback of the COHS-LF package 300 is
that it is not compatible to a standard leadframe packaging
processes and the heat sink only acts as a ground net.
[0014] Thus, a novel semiconductor packing processes is desired,
which is capable of fulfilling both high performance and low
production costs for applications related to high speed product
integration requirements such as using the system in package (SiP)
to integrate RF+BB chips or DTV+DDR SDRAMs.
BRIEF SUMMARY OF THE INVENTION
[0015] A detailed description is given in the following embodiments
with reference to the accompanying drawings.
[0016] The invention relates to integration of leadframe on heat
sink (LOHS) with multi-chips (system) mounted in a package (SiP).
Meanwhile, the heat sink can be pre-divided into several PWR and
GND regions to reduce number of leads further shrinking package
dimensions
[0017] An embodiment of the invention provides a system in package,
comprising: a leadframe having extension leads, configured with
divisional heat sinks serving as power and ground nets; a set of
semiconductor dies attached by adhesive on the central region of
the lead frame; a plurality of wire bonds electrically connecting
the set of semiconductor dies to the leadframe and to the
divisional heat sinks respectively; and an encapsulation layer
enclosing the leadframe, but leaves the extension leads and the
divisional heat sink uncovered, exposing a heat dissipating
surface.
[0018] Another embodiment of the invention further provides an
electronic system, comprising: a printed circuit board (PCB) with a
plurality of different chips with different types of semiconductor
packaging and electronic devices mounted thereon; a system in
package (SiP) attached on the PCB with solders, wherein the system
in package is operatically synergized with the plurality of
different chips with different types of semiconductor packaging and
electronic devices. The system in package (SiP) comprises a
leadframe having extension leads, configured with divisional heat
sinks serving as power and ground nets; a set of semiconductor dies
attached by adhesive on the central region of the lead frame; a
plurality of wire bonds electrically connecting the set of
semiconductor dies to the leadframe and to the divisional heat
sinks respectively; and an encapsulation layer enclosing the
leadframe, but leaving the extension leads and the divisional heat
sink uncovered, exposing a heat dissipating surface.
[0019] Another embodiment of the invention further provides a
fabrication method for a system in package, comprising: assembling
a leadframe having extension leads, configured with divisional heat
sinks; attaching a set of semiconductor dies by adhesive on the
central region of the lead frame; bonding wires connecting the set
of semiconductor dies to the leadframe and to the divisional heat
sinks respectively; and molding an encapsulation layer enclosing
the leadframe, but leaving the extension leads and the divisional
heat sink uncovered, exposing a heat dissipating surface.
[0020] Note that assembling of the leadframe comprises providing a
top metal, a dielectric material and a bottom metal; pressing an
assembly of the top metal, a dielectric material and a bottom
metal; etching the top metal to create a leadframe with extension
leads and an opening at a central region thereof; etching bottom
metal to create divisional heat sinks; forming through holes
proliferating the assembly; removing the dielectric material within
the opening; forming a solder mask at the peripheral region of the
leadframe; and electroplating a metal on the wirebonding area.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The invention can be more fully understood by reading the
subsequent detailed description and examples with references made
to the accompanying drawings, wherein:
[0022] FIGS. 1A-1D are cross sections of a traditional quad flat
packages with different heat sinks enhancing thermal
performance;
[0023] FIG. 2A is a cross sectional view of a conventional EDHS-QFP
package;
[0024] FIG. 2B is a 3D view of a conventional LOHS-QFP package with
plastic molding removed to clearly show the lead frame and the
interposer ring;
[0025] FIG. 3 is a cross section of a conventional chip-on heat
sink leadframe package;
[0026] FIG. 4A is a cross section of an embodiment of a lead on
heat sink (LOHS) system in package (SiP) of the invention;
[0027] FIG. 4B is a plan view of the LOHS-SiP of FIG. 4A;
[0028] FIGS. 5A-5H are cross sections of each fabrication step of
an embodiment of an LOHS structure of the invention;
[0029] FIGS. 6A-6H are cross sections of each fabrication step of
another embodiment of an LOHS structure of the invention;
[0030] FIG. 7 is a schematic view of an enlargement of the exposed
surface of the heat sink of some embodiments of the invention;
[0031] FIG. 8 is a schematic model showing the system in package
and lead geometry, as well as materials used;
[0032] FIG. 9 depicts the heat sink divided into several power and
ground nets;
[0033] FIG. 10A is a plan view of another embodiment of a lead on
heat sink system in package (LOHS-SiP) of the invention; and
[0034] FIG. 10B is a plan view of yet another embodiment of
LOHS-SiP with RF+Baseband chip stacks of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0035] It is to be understood that the following disclosure
provides many different embodiments, or examples, for implementing
different features of various embodiments. Specific examples of
components and arrangements are described below to simplify the
present disclosure. These are merely examples and are not intended
to be limiting. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself indicate a relationship between the various
embodiments and/or configurations discussed. Moreover, the
formation of a first feature over or on a second feature in the
description that follows may include embodiments in which the first
and second features are formed in direct contact or not in direct
contact.
[0036] FIG. 4A is a cross section of an embodiment of a lead on
heat sink (LOHS) system in package (SiP) of the invention. FIG. 4B
is a plan view of the LOHS-SiP of FIG. 4A. A lead on heat sink
system in package (LOHS-SiP) 400 includes a leadframe 440 having
extension leads 442, configured with divisional heat sinks
430a-430d serving as power and ground nets. A dielectric layer 435
is interposed between the leadframe 440 and the divisional heat
sinks 430. Semiconductor dies 420 and 450 are attached by adhesive
on the central region of the lead frame. Semiconductor dies 420 and
450 are a set of vertically stacked pair of dies including a
digital chip and an analog chip, an RF chip and a BB chip, or a DSP
chip and a DDR SDRAM chip. A plurality of wire bonds 450a-450d are
electrically connected to the semiconductor dies 420 and 450 to the
leadframe and to the divisional heat sinks respectively. An
encapsulation 460 encloses the leadframe 440, leaving the extension
leads 442 and the divisional heat sink uncovered, exposing a heat
dissipating surface.
[0037] The LOHS-SiP 400 further comprises an interconnection
section 432 as a bridge electrically connecting the set of
semiconductor dies and the divisional heat sinks by wire bonds. A
die paddle 436 is optionally disposed on the central region of the
lead frame 440 for supporting the set of semiconductor dies 420 and
450. The LOHS-SiP 400 is mounted on a printed circuit board (PCB)
480 with solders 470 and 475.
[0038] The leadframe and the heat sink are fabricated by compatible
semiconductor processes, and then bonded with the stacked chips.
The added heat sink not only improves heat removal, but also
creates several power and ground planes. For example, the heat sink
can be pre-divided into several PWR/GND regions to reduce number of
leads further shrinking package dimensions. Since the number of the
leads can be thus reduced, better signal integrity and power
integrity with fine lead pitch can also be achieved. Furthermore,
the power and ground planes are bonded to the corresponding power
and ground pads on the die and then soldered to the power and
ground nets on the printed circuit board (PCB). Since power and
ground do not need to go through the leads on the COHS-LF package,
there is more space available to design the lead geometry for
high-speed application, and therefore increased opportunity to
reduce the package size.
[0039] FIGS. 5A-5H are cross sections of each fabrication step of
an embodiment of an LOHS structure of the invention. Referring to
FIG. 5A, a top metal layer 510, a dielectric material layer 520 and
a bottom metal layer 530 are provided. The top and bottom metal
layers can be metals (such as Cu and Al) and alloys (such as C7025,
A42, and A192). The dielectric material layer can be FR-4, BT,
ceramic, epoxy prepeg (PP), polyimide tape, and adhesive film. The
top metal layer 510, the dielectric material layer 520 and the
bottom metal layer are pressed into an assembly, as shown in FIG.
5B.
[0040] Referring to FIG. 5C, the top metal layer 510 is etched to
create a leadframe with extension leads and openings 515a and an
elevated central region as a die paddle 512. The bottom metal layer
is then etched to create a concave region 535 for die attachment
and divisional heat sinks as PWR/GND nets, as shown in FIG. 5D.
[0041] Referring to FIG. 5E, through holes 540 are proliferated
through the assembly serving as chip openings for subsequently wire
bonding. The exposed dielectric material layer within the openings
515a is then removed using the top metal layer as a mask, as shown
in FIG. 5F.
[0042] Referring to FIG. 5G, a solder mask 512 is applied covering
the subsequently undesired electroplating regions. A conventional
dam bar on the leadfame can be simultaneously omitted due to
formation of the solder mask 512 at the peripheral region of the
leadframe. A metal layer 550 is then electroplated on the top metal
layer, as shown in FIG. 5H. Materials for the metal layer 550 can
be a single Au, Ag, Ni, Cu, or Pd layer, or different metal
laminated electroplating to enhance adhesion between the bondwires
and the leads.
[0043] FIGS. 6A-6H are cross sections of each fabrication step of
another embodiment of an LOHS structure of the invention. Elements
of the LOHS structure of FIGS. 6A-6H are substantially similar to
those in FIGS. 5A-5H, with the similar steps omitted herein. The
difference therebetween is that the central die paddle is removed
after the top metal layer is etched as shown in FIG. 6C. A central
opening 515b is created, and stacked dies can be attached on both
sides of the heat sink. Note that if said heat sink is pre-divided
into several PWR/GND regions, shapes, and through holes before
pressing assembly in FIG. 5B, the subsequent steps in FIGS. 5D-5E
can be omitted.
[0044] Since the abovementioned LOHS structures include a solder
mask, the contact region with injection mold is flat. As such, the
dam bar design is unnecessary, thus subsequent conventional
deflash/trim or dejunk/trimming steps are omitted.
[0045] FIG. 7 is a schematic view of an enlargement of the exposed
surface of the heat sink of some embodiments of the invention. An
encapsulation 560 is subsequently molded exposing a heat
dissipating surface 530' of the divisional heat sinks 530. The heat
dissipating surface 530' of the divisional heat sinks comprises a
plurality of protrusions or bumps to improve adhesion between resin
and the divisional heat sinks. Since the exposed heat dissipating
surface 530' includes small trenches, thermal stress due to
coefficient of thermal expansion (CTE) can be ameliorated.
[0046] The ground divisional heat sinks beneath the leads allow for
controlling of impedance. FIG. 8 is a schematic model showing the
system in package and lead geometry, as well as materials used. A
leadframe having extension leads 631-638 is configured with
divisional heat sinks 610 serving as power and ground nets. A
dielectric layer 620 is interposed between the leadframe and the
divisional heat sinks. An encapsulation 640 pacifies and covers the
package. Adjust the lead geometries and the dielectric thickness
620 and 640, the target leads 634 and 635 can be designed as
required impedance, such as 50.OMEGA. single-ended or 100.OMEGA.
differential impedance, for better signal integrity.
[0047] Heat flows (Th) from the higher temperature chip to the
lower temperature ambient outer environment. Therefore, a higher
thermal conductivity (.kappa.) between chip and ambient enhances
heat removal (e.g., copper .kappa..apprxeq.400 W/mK). Thermal and
electrical analysis of the package with chip surface attached to
the exposed heat sink showed it had even smaller temperature
increment, less signal losses and cross-talk than the conventional
BGA package and LOC-TSOP packages.
[0048] FIG. 9 is a plan view of embodiment for the heat sink 830
divided into several power and ground nets 830a-830d. Due to
shorter bondwires and larger power and ground nets compared to
traditional QFPs, lower parasitic parameters from the LOHS-QFP are
expected.
[0049] FIG. 10A is a plan view of another embodiment of a lead on
heat sink system in package (LOHS-SiP) of the invention. A LOHS-SiP
900 includes a multi-chip stacked application. The drawback of the
conventional DSP+DDR SDRAM chip stacks include lengthy wires due to
the bonding pads being disposed at the center of the DDR SDRAM,
resulting in wire sweep problems, deteriorated electrical
performances and production yields.
[0050] Referring to FIG. 10A, an LOHS-SiP 900 includes divisional
heat sinks 930a-930d pasted with a top die (DSP chip) 910 and a
bottom die (SDRAM chip) 920 embedded therein. The heat sink 930
contains an opening 940 around the chip-bonding pads 925, and thus
shorter bondwires 950a and 950b are obtained. The bottom die 920
interconnects a top die 910 through the wire bonding 950a via a
proper opening 940 of the heat sink. Thus, the lengths of the
bondwires 950a are shorter with better electrical performance and
termination can be omitted. Some passive devices 980 such as
capacitors or inductors are disposed on the peripheral regions
between adjacent divisional heat sinks. Furthermore, with the die
peddle 905 able to serve as a buffer between dies 910 and 920,
packaging yield can be increased. Meanwhile, because the top metal
can be etched into interconnected sections 936a and 936b, the
length of the bondwires 950b and 950c can be further reduced.
[0051] FIG. 10B is a plan view of yet another embodiment of
LOHS-SiP with RF+Baseband chip stacks of the invention. An LOHS-SiP
1000 with RF+Baseband chip stacks include divisional heat sinks
1030 pasted with a top die (RF chip) 1010 and a bottom die (BB
chip) 1020 embedded therein. The heat sink 1030 contains opening
1015 around the chip-bonding pads 1022, and thus shorter bondwire
1050b are obtained. The bottom die 1020 interconnects a top die
1010 through bondwires 1050d via an interconnection section 1046 or
a common bar. Thus, the crossover of wirebonding can be avoided.
With the die peddle 1045 able to serve as a buffer between dies
1010 and 1020, packaging yield can be increased. Furthermore, the
die peddle 1045 can effectively block RF signal interference.
[0052] While the invention has been described by way of example and
in terms of the preferred embodiments, it is to be understood that
the invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
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