U.S. patent application number 12/018441 was filed with the patent office on 2008-06-12 for apparatus and process for precise encapsulation of flip chip interconnects.
Invention is credited to Rajendra D. Pendse.
Application Number | 20080134484 12/018441 |
Document ID | / |
Family ID | 26765567 |
Filed Date | 2008-06-12 |
United States Patent
Application |
20080134484 |
Kind Code |
A1 |
Pendse; Rajendra D. |
June 12, 2008 |
Apparatus and process for precise encapsulation of flip chip
interconnects
Abstract
A method for encapsulating flip chip interconnects includes
applying a limited quantity of encapsulating resin to the
interconnect side of an integrated circuit chip, and thereafter
bringing the chip together with a substrate under conditions that
promote the bonding of bumps on the interconnect side of the chip
with bonding pads on the substrate. In some embodiments, the step
of applying resin to the chip includes dipping the interconnect
side of the chip to a predetermined depth in a pool of resin, and
then withdrawing the chip from the resin pool. In some embodiments
the step of applying resin to the chip includes providing a
reservoir having a bottom, providing a pool of resin in the
reservoir to a shallow depth over the reservoir bottom, dipping the
chip into the resin pool so that the bumps contact the reservoir
bottom, and then withdrawing the chip from the resin pool. Also,
apparatus for applying a precise volume of encapsulating resin to a
chip, includes a reservoir having a bottom, and means for
dispensing a pool of encapsulating resin to a predetermined depth
over the reservoir bottom.
Inventors: |
Pendse; Rajendra D.;
(Fremont, CA) |
Correspondence
Address: |
QUARLES & BRADY LLP
RENAISSANCE ONE, TWO NORTH CENTRAL AVENUE
PHOENIX
AZ
85004-2391
US
|
Family ID: |
26765567 |
Appl. No.: |
12/018441 |
Filed: |
January 23, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10456434 |
Jun 6, 2003 |
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12018441 |
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10081425 |
Feb 22, 2002 |
6780682 |
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10456434 |
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60272280 |
Feb 27, 2001 |
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Current U.S.
Class: |
29/25.01 ;
257/E21.503 |
Current CPC
Class: |
H01L 2924/181 20130101;
H01L 2924/00014 20130101; H01L 2224/83191 20130101; H01L 2924/14
20130101; H01L 21/563 20130101; H01L 24/29 20130101; H01L
2224/16225 20130101; H01L 2924/181 20130101; H01L 2224/73204
20130101; H01L 2224/0401 20130101; H01L 2924/00 20130101; H01L
2224/73203 20130101; H01L 2224/11822 20130101; H01L 2924/00014
20130101; H01L 2924/01033 20130101 |
Class at
Publication: |
29/25.01 |
International
Class: |
H01L 21/76 20060101
H01L021/76 |
Claims
1-4. (canceled)
5. A semiconductor device manufacturing tool for applying
encapsulating resin to an area of the semiconductor device,
comprising: a semiconductor device support tool; a semiconductor
device having a plurality of interconnect bumps formed on a first
surface of the semiconductor device, the interconnect bumps having
a standoff height as measured from a distal end of the interconnect
bumps to the first surface, the semiconductor device further having
a second surface opposite the first surface, the second surface of
the semiconductor device being attached to the semiconductor device
support tool; a support structure having a recessed area defining a
reservoir which contains the encapsulating resin, the reservoir
having a depth not greater than the standoff height of the
interconnect bumps, wherein the interconnect bumps of the
semiconductor device are dipped into the reservoir so the distal
ends of the interconnect bumps contact a bottom of the reservoir
and the encapsulating resin is deposited on the interconnect bumps
and first surface of the semiconductor device; and a substrate
having interconnect pads on a surface, the semiconductor device
support tool positioning the semiconductor device so that the
interconnect bumps on the semiconductor device contact the
interconnect pads of the substrate, wherein the encapsulating resin
deposited on the first surface of the semiconductor device is
transferred to the surface of the substrate in proper quantity to
encapsulate an area between the semiconductor device and substrate
without excessive bleed out of the encapsulating resin.
6. The semiconductor device manufacturing tool of claim 5, wherein
the depth of the reservoir is less than the standoff height of the
interconnect bumps.
7. The semiconductor device manufacturing tool of claim 5, wherein
the semiconductor device is a flip chip semiconductor device.
8. The semiconductor device manufacturing tool of claim 5, wherein
the semiconductor device and substrate are aligned prior to
contacting the interconnect bumps to the interconnect pads.
9. The semiconductor device manufacturing tool of claim 5, wherein
a quantity of encapsulating resin deposited on the first surface of
the semiconductor device by dipping the interconnect bumps into the
reservoir is determined by a depth of encapsulating resin in the
reservoir.
10. The semiconductor device manufacturing tool of claim 5, wherein
the encapsulating resin forms a fillet around a perimeter of the
semiconductor device.
11. An apparatus for applying encapsulating resin to an area of the
semiconductor device, comprising: a semiconductor device having a
plurality of interconnect bumps formed on a first surface of the
semiconductor device, the interconnect bumps having a standoff
height as measured from a distal end of the interconnect bump to
the first surface; a support structure having a recessed area
defining a reservoir which contains the encapsulating resin, the
reservoir having a depth not greater than the standoff height of
the interconnect bumps, wherein the interconnect bumps of the
semiconductor device are dipped into the reservoir so the distal
ends of the interconnect bumps contact a bottom of the reservoir
and the encapsulating resin is deposited on the interconnect bumps
and first surface of the semiconductor device; and a substrate
having interconnect pads on a surface, the interconnect bumps of
the semiconductor device contacting the interconnect pads of the
substrate so that the encapsulating resin deposited on the first
surface of the semiconductor device is transferred to the surface
of the substrate in proper quantity to encapsulate an area between
the semiconductor device and substrate without excessive bleed out
of the encapsulating resin.
12. The apparatus of claim 11, wherein the depth of the reservoir
is less than the standoff height of the interconnect bumps.
13. The apparatus of claim 11, wherein the semiconductor device is
a flip chip semiconductor device.
14. The apparatus of claim 11, wherein the semiconductor device and
substrate are aligned prior to contacting the interconnect bumps to
the interconnect pads.
15. The apparatus of claim 11, wherein a quantity of encapsulating
resin deposited on the first surface of the semiconductor device by
dipping the interconnect bumps into the reservoir is determined by
a depth of the encapsulating resin in the reservoir.
16. The apparatus of claim 11, wherein the encapsulating resin
forms a fillet around a perimeter of the semiconductor device.
17. An apparatus for applying encapsulating resin to an area of the
semiconductor device, comprising: a semiconductor device having a
plurality of interconnect bumps formed on a first surface of the
semiconductor device, the interconnect bumps having a standoff
height as measured from a distal end of the interconnect bumps to
the first surface; a support structure having a recessed area
defining a reservoir which contains the encapsulating resin, the
reservoir having a depth not greater than the standoff height of
the interconnect bumps, wherein the interconnect bumps of the
semiconductor device are dipped into the reservoir so the distal
ends of the interconnect bumps contact a bottom of the reservoir
and the encapsulating resin is deposited on the interconnect bumps;
and a substrate having interconnect pads on a surface, the
interconnect bumps of the semiconductor device contacting the
interconnect pads of the substrate so that the encapsulating resin
deposited on the interconnect bumps of the semiconductor device is
transferred to the surface of the substrate to encapsulate an area
between the semiconductor device and substrate.
18. The apparatus of claim 17, wherein the depth of the reservoir
is less than the standoff height of the interconnect bumps.
19. The apparatus of claim 17, wherein the semiconductor device is
a flip chip semiconductor device.
20. The apparatus of claim 17, wherein the semiconductor device and
substrate are aligned prior to contacting the interconnect bumps to
the interconnect pads.
21. The apparatus of claim 17, wherein a quantity of encapsulating
resin deposited on the first surface of the semiconductor device by
dipping the interconnect bumps into the reservoir is determined by
a depth of encapsulating resin in the reservoir.
22. The apparatus of claim 17, wherein the encapsulating resin
forms a fillet around a perimeter of the semiconductor device.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No.
10/081,425 filed 22 Feb. 2002, which claims priority from
Provisional Application No. 60/272,280, filed Feb. 27, 2001.
BACKGROUND
[0002] This invention relates to semiconductor device packaging
and, particularly, to flip chip packages.
[0003] Flip chip packages include an integrated circuit chip
connected to a package substrate by way of interconnect bumps which
are mounted on the integrated circuit chip in arrangement
corresponding to the arrangement to metal contact pads on
substrate. During package assembly the chip and substrate are
opposed with the corresponding bumps and pads aligned, and then the
chip and substrate are brought together under conditions that
promote the bonding of the bumps on the metal pads.
[0004] Flip chip devices are conventionally encapsulated to improve
the reliability of the interconnections between the chip and the
substrate. Ordinarily the encapsulation is carried out using one of
two approaches.
[0005] In the first approach, commonly known as "under filling",
encapsulation is carried out following formation of the
interconnections between the chip and substrate, by dispensing the
encapsulating resin into the gap between the chip in the substrate
near an outer edge of the chip, and then allowing the resin to move
into the gap between the chip and the substrate by capillary
action. This approach carries a high processing cost, because the
under filling process is time-consuming and high throughput cannot
be achieved. Moreover, a significant space must be provided between
adjacent devices to accommodate the dispensed resin bead at the
edge of each chip this requirement for extra space between adjacent
devices limits of substrate utilization in high-density
applications.
[0006] In a second approach, a quantity of encapsulating resin is
applied to the surface of substrate prior to assembly of the
package. Then, as the chip and substrate are brought together in
the assembly process, any encapsulating resin that overlies the
pads is displaced by pressure of the bumps against the pads during
the attachment process. This technique is susceptible to bleed-out
of the resin laterally away from the chip edge as well as
vertically along the sidewalls of the chip. Bleed-out away from the
chip edge requires extra space between adjacent devices, limiting
substrate utilization; and vertical bleed-out can result in resin
reaching the backside of the chip and, in some instances,
contamination of the bonding tool which is used to manipulate the
die. Bleed-out is disruptive of the manufacturing process and is
therefore undesirable. Moreover, a thermal excursion required to
attach a device can cause partial curing of the applied resin on
adjacent sites, thereby adversely affecting the quality of the
inner connections on adjacent devices. Moreover, there is a
practical lower limit on the thinness to which resin material can
be applied by dispensing onto a surface or by screen printing, and
that limit is generally greater (in some instances two or three
times greater: about 100 microns for dispensing; about 50 microns
for screen printing) than the bump standoff height (typically, for
example, about 50-75 microns before bonding; and as little as about
25-30 microns, for example, after bonding) that is preferred in
some small scale flip chip packages.
[0007] Both of these approaches entail a dedicated unit process for
application of the resin material, usually requiring dedicated
equipment for the unit process and adding to both the labor costs
and capital depreciation cost of the overall process.
SUMMARY
[0008] The invention provides an improved method for encapsulating
flip chip interconnects. According to the method, a limited
quantity of encapsulating resin is applied to the interconnect side
of the chip, and thereafter the chip and substrate are opposed with
the corresponding bumps and pads aligned, and then the chip and
substrate are brought together under conditions that promote the
bonding of the bumps on the metal pads. The resin may be applied to
the interconnect side of the chip in any of a variety of ways. I
have found, however, that a defined quantity of resin can
conveniently and reliably be applied selectively to the chip by
dipping the interconnect side of the chip in a pool of the resin to
a predetermined depth, and then withdrawing the chip from the resin
pool. A quantity of resin, precisely defined by the predetermined
depth to which the chip was dipped in the resin pool, remains on
the dipped portion of the chip as the chip is withdrawn from the
resin pool and brought to the substrate for assembly. Most
conveniently and reliably, the pool of resin is provided to a
shallow depth in a reservoir, and the chip is dipped into the pool
of resin in the reservoir so that the bumps contact the bottom of
the reservoir. The predetermined shallow depth of the resin pool
thereby determines the quantity of resin that remains on the dipped
portion of the chip as the chip is withdrawn from the pool.
[0009] Accordingly, in one general aspect the invention features a
method for encapsulating flip chip interconnects, by applying a
limited quantity of encapsulating resin to the interconnect side of
an integrated circuit chip, and thereafter bringing the chip
together with a substrate under conditions that promote the bonding
of bumps on the interconnect side of the chip with bonding pads on
the substrate.
[0010] In some embodiments, the step of applying resin to the chip
includes dipping the interconnect side of the chip to a
predetermined depth in a pool of resin, and then withdrawing the
chip from the resin pool. In some embodiments the predetermined
depth to which the chip is dipped in the pool approximates the
standoff height between the bump surfaces and the chip surface, so
that the surface of the resin pool contacts the chip surface, with
result that when the chip is withdrawn from the resin pool some
quantity of resin may remain on the chip surface as well as on
features that standoff from the chip surface. Or, the predetermined
depth to which the chip is dipped in the pool is somewhat less than
the standoff height, so that the chip surface does not contact the
resin pool, with the result that when the chip is withdrawn from
the resin pool some quantity of resin remains only on features that
standoff from the chip surface, such as the bumps or a portion of
the bumps.
[0011] In some embodiments the step of applying resin to the chip
includes providing a reservoir having a bottom, providing a pool of
resin in the reservoir to a shallow depth over the reservoir
bottom, dipping the chip into the resin pool so that the bumps
contact the reservoir bottom, and then withdrawing the chip from
the resin pool. In some such embodiments, the shallow depth of the
pool over the reservoir bottom approximates the standoff height
between the bumps surfaces and the chip surface, or is somewhat
less than the standoff height.
[0012] In another general aspect the invention features apparatus
for applying a precise volume of encapsulating resin to a chip,
including a reservoir having a bottom, and means for dispensing a
pool of encapsulating resin to a predetermined depth over the
reservoir bottom. In some embodiments the reservoir is at least
deep enough to accommodate a pool having a predetermined depth that
approximates a bump standoff height on the chip. In some
embodiments the means for dispensing the resin pool includes means
for dispensing a measured volume of resin into the reservoir. In
some embodiments the means for dispensing the resin pool includes
means for dispensing an excess of resin into the reservoir, and
means such as a doctor for removing the excess; in such embodiments
the predetermined depth of the pool is established by the depth of
the reservoir itself.
[0013] An advantage of the method of the invention is that the
resin pattern is self-aligned to the chip, so that there is no
requirement according to the invention for alignment of the
dispense pattern with the flip chip footprint pattern on the
substrate. Moreover the resin is applied according to the invention
preferentially to the portions of the interconnect side of the chip
on which application of resin is most particularly desired, that
is, on hand in the vicinity of the bumps.
[0014] The resin reservoir is readily integrated with existing chip
attachment equipment, so that there is no need for specialized or
dedicated equipment or process steps for applying resin according
to the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIGS. 1-5 are a diagrammatic sketches in a partially
sectional view illustrating stages in an embodiment of the method
of the invention.
DETAILED DESCRIPTION
[0016] The invention will now be described in further detail by
reference to the drawings, which illustrate an embodiment of the
invention. The drawings are diagrammatic, showing features of the
invention and their relation to other features and structures, and
are not made to scale. For improved clarity of presentation, in the
FIGs. illustrating stages in the method of the invention, elements
corresponding to elements shown in other drawings are not all
particularly renumbered, although they are all readily identifiable
in all the FIGs.
[0017] Turning now to FIG. 1, there is shown generally at 20 a
reservoir formed in a support 22 and generally at 10 an integrated
circuit chip being held by a conventional tool 12. The reservoir 28
is defined by a reservoir bottom 24 and sides 26. The reservoir
depth is indicated at 27, and the reservoir is here shown filled
nearly to its full depth with encapsulation resin forming a resin
pool 30. The integrated circuit chip 10 includes a semiconductor
die 18 having interconnect bumps 16 attached to interconnect sites
(not shown in the FIGs.) in a chip surface 17. The bump standoff
height is indicated at 15. The chip surface 17 and the interconnect
bumps 16 together with other features not shown in the FIGs.
constitute an interconnect side 14 of the chip. In FIG. 1, the tool
12 is poised to move toward the reservoir 20 (as shown by the arrow
11 in FIG. 2) to dip the interconnect side 14 of the chip into the
resin pool 30.
[0018] FIG. 2 shows the chip 10 being dipped into the resin pool
30. The bumps 16 have been brought into contact with the reservoir
bottom 28, so that the pool depth defines the depth to which the
interconnect side of the chip is dipped into the pool. In FIGS. 1
and 2 the pool depth is shown as being slightly less than the
reservoir depth 27, and pool depth is also shown as being somewhat
less than the bump standoff height 15. As a consequence, in the
example shown here, the surface 32 of the resin pool does not come
into contact with the chip surface 17 and, accordingly, resin would
be expected to remain on only the bumps when the chip is withdrawn
from the pool.
[0019] FIG. 3 shows a chip 10 that has been withdrawn from a resin
pool. Evidently, the interconnect side of the chip shown in FIG. 3
was dipped to a greater depth in a resin pool than is shown in FIG.
2, inasmuch as in FIG. 3 the resin mass 34 is shown as being
carried not only on the bumps 16 but also on the surface 17 of the
semiconductor die. As will be appreciated, the quantity of resin in
a resin mass carried by the chip after the chip is withdrawn from
the resin pool will depend not only upon the extent of contact to
the chip with the resin in the pool, but also upon surface
characteristics (for example, wettability by the resin) of the
various features on the chip and upon characteristics (for example,
viscosity) of the resin itself. A desired predetermined depth to
which a particular chip should be dipped in a particular resin
composition, to result in a particular desired encapsulation form,
can readily be determined without undue experimentation. FIG. 3
also shows a package substrate 40 having metal interconnect pads 42
in an arrangement complementary to the arrangement of the bumps on
the chip, and the tool 12 is holding the chip in apposition to the
substrate with the corresponding bumps and pads aligned. The tool
is poised in FIG. 3 to bring the chip and substrate together as
shown for example in FIG. 4.
[0020] In FIG. 4 the resin mass 36 is shown having been compressed
between the chip in the substrate, and displaced by the various
features on the interconnect sides of the chip and of the
substrate; to form a desired "fillet" 37, at the margins of the gap
between the die and substrate, without excessive bleed out. The
tool 12 is then released from the die, and encapsulating resin is
cured to form a completed encapsulation 38 of the package 50 as
shown in FIG. 5. Some deformation of the bumps during the
attachment operation can be expected, resulting in a reduction of
the standoff height. This can further compress the resin and force
it into asperities formed by the circuit pattern on the substrate
surface as well as by features on the interconnect side of the
chip, resulting in improved encapsulation integrity.
[0021] Other embodiments are within the following claims.
* * * * *