U.S. patent application number 11/978149 was filed with the patent office on 2008-06-05 for silicon chip of monolithic construction for integration in a pc-based computing system and having multiple gpu-driven pipeline cores supporting multiple modes of parallelization dynamically controlled while running a graphics application.
Invention is credited to Reuven Bakalash, Efi Fogel, Offir Remez.
Application Number | 20080129743 11/978149 |
Document ID | / |
Family ID | 37108069 |
Filed Date | 2008-06-05 |
United States Patent
Application |
20080129743 |
Kind Code |
A1 |
Bakalash; Reuven ; et
al. |
June 5, 2008 |
Silicon chip of monolithic construction for integration in a
PC-based computing system and having multiple GPU-driven pipeline
cores supporting multiple modes of parallelization dynamically
controlled while running a graphics application
Abstract
A silicon chip of monolithic construction and software
multi-pipe drivers for integration in a PC-based computing system
and parallelizing multiple GPU-driven pipeline cores supporting
multiple modes of parallelization dynamically controlled while
running a graphics application. The PC-based computing system
includes system memory for storing software graphics applications,
software drivers and graphics libraries, and an operating system
(OS), stored in the system memory, and a central processing unit
(CPU), for executing the OS, graphics applications, drivers and
graphics libraries. The silicon chip includes a routing unit and a
control unit. The routing unit (i) routes the stream of geometrical
data and graphic commands from the graphics application to one or
more of the GPU-driven pipeline cores, and (ii) routes pixel data
output from one or more of GPU-driven pipeline cores during the
composition of frames of pixel data corresponding to final images
for display on the display surface. The control unit accepts
commands from the software multi-pipe drivers, and controls
components within the silicon chip, including the routing unit. In
the illustrative embodiment, the profiling unit profiles the
performance of the GPU-driven pipeline cores and feeds back
performance data to the software multi-pipe drivers, for
dynamically determining and controlling the mode of parallelization
during the generation of each frame of pixel data, while running a
graphics application.
Inventors: |
Bakalash; Reuven; (Shdema,
IL) ; Remez; Offir; (Hod HaSharon, IL) ;
Fogel; Efi; (Tel Aviv, IL) |
Correspondence
Address: |
Thomas J. Perkowski, Esq., P.C.
1266 East Main Street
Stamford
CT
06902
US
|
Family ID: |
37108069 |
Appl. No.: |
11/978149 |
Filed: |
October 26, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11340402 |
Jan 25, 2006 |
|
|
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11978149 |
|
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|
60647146 |
Jan 25, 2005 |
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Current U.S.
Class: |
345/502 |
Current CPC
Class: |
G09G 5/363 20130101;
G06F 9/505 20130101; G06F 3/14 20130101; G06F 9/5083 20130101; G09G
2300/0426 20130101; G06T 15/005 20130101; G06F 9/3885 20130101;
G06T 2210/52 20130101; G09G 2360/06 20130101; G09G 2310/0224
20130101; G06T 1/20 20130101; G06F 3/1423 20130101 |
Class at
Publication: |
345/502 |
International
Class: |
G06F 15/16 20060101
G06F015/16 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 28, 2004 |
IL |
PCT/IL2004/000079 |
Aug 19, 2004 |
WO |
WO 2004/070652 A2 |
Nov 19, 2004 |
IL |
PCT/IL2004/001069 |
Jun 2, 2005 |
WO |
WO 2005/050557 A2 |
Claims
1. A silicon chip of monolithic construction and software
multi-pipe drivers for integration in a PC-based computing system
and parallelizing multiple GPU-driven pipeline cores supporting
multiple modes of parallelization dynamically controlled while
running a graphics application, wherein said PC-based computing
system includes (i) system memory for storing software graphics
applications, software drivers and graphics libraries, (ii) an
operating system (OS), stored in said system memory, (iii) one or
more graphics applications, stored in said system memory, for
generating a stream of geometrical data and graphics commands
supporting the representation of one or more 3D objects in a scene
having 3D geometrical characteristics and the viewing of images of
said one or more 3D objects in said scene during an interactive
process carried out between said PC-based computing system and a
user thereof, (iv) one or more graphic libraries, stored in said
system memory, for storing data used to implement said stream of
geometrical data and graphics commands, (v) a central processing
unit (CPU) for executing said OS, said graphics applications, said
drivers and said graphics libraries, (vi) a CPU bus, (vii) an
CPU/memory interface module, and (viii) a display surface for
displaying said images by graphically displaying frames of pixel
data; wherein said silicon chip comprises: a routing unit; a
control unit; and a plurality of GPU-driven pipeline cores arranged
in a parallel architecture and operating according to one or more
parallelization modes of operation, determined during the
generation of each said frame of pixel data, so that said
GPU-driven pipeline cores process data in a parallel manner;
wherein said software multi-pipe drivers are stored in said system
memory; wherein said one or more parallelization modes of operation
include a time division mode, an image division mode, and an object
division; wherein said routing unit (i) routes the stream of
geometrical data and graphic commands from said graphics
application to one or more of said GPU-driven pipeline cores, and
(ii) routes pixel data output from one or more of said GPU-driven
pipeline cores during the composition of each frames of pixel data
corresponding to a final image, for display on said display
surface; wherein said control unit accepts commands from said
software multi-pipe drivers, and controls components within said
silicon chip, including said routing unit; wherein said software
multi-pipe drivers perform the following functions: (i) controlling
the operation of said silicon chip, (ii) interacting with said OS
and said graphic libraries, (ii) dynamically determining and
controlling said parallelization mode during the generation of each
said frame of pixel data during the running of said graphics
application, and (iii) forwarding said stream of geometrical data
and graphic commands, or a portion thereof, over said CPU bus to
each said GPU-driven pipeline core; and wherein, for each image of
said 3D object to be generated and displayed on said display
surface, the following operations are performed: (i) said silicon
chip uses said routing unit to distribute said stream of
geometrical data and graphic commands, or a portion thereof, to
said GPU-driven pipeline cores, (ii) one or more of said GPU-driven
pipeline cores process said stream of geometrical data and graphic
commands, or a portion thereof, during the generation of each said
frame, while operating in said parallelization mode, so as to
generate pixel data corresponding to at least a portion of said
image, and (iii) said silicon chip uses said routing unit to route
said pixel data output from one or more of said GPU-driven pipeline
cores and compose a frame of pixel data, representative of the
image of said 3D object, for display on said display surface.
2. The silicon chip of claim 1, which further comprises a profiling
unit for profiling the performance of said GPU-driven pipeline
cores and feeding back said performance data to said software
multi-pipe drivers.
3. The silicon chip of claim 1, which further comprises a memory
unit for storing intermediate processing results from one or more
of said multiple GPU-driven pipeline cores, and data required for
composition and transferring frames of pixel data for display.
4. The silicon chip of claim 1, wherein said CPU/memory interface
module is an I/O chip or chipset.
5. The silicon chip of claim 1, wherein each said GPU-driven
pipeline core has a frame buffer (FB) for storing a fragment of
pixel data.
6. The silicon chip of claim 1, wherein said geometrical data
comprises a set of scene polygons, textures and vertex objects.
7. The silicon chip of claim 1, wherein said graphics commands
includes commands selected from the group consisting of display
lists and display vertex arrays.
8. The silicon chip of claim 1, wherein said graphic libraries are
selected from the group consisting of OpenGL and DirectX.
9. The silicon chip of claim 1, wherein said software multi-pipe
drivers coordinate the operation of said GPU-driven pipeline cores
so generate a continuous sequence of frames of pixel data for
displaying a sequence of images of said 3D object on said display
surface.
10. The silicon chip of claim 1, wherein each pixel associated with
a frame of pixel data includes attributes selected from the group
consisting of color, alpha, position, depth, and stencil.
11. The silicon chip of claim 1, wherein when said parallelization
mode of operation is said time division mode, each said GPU renders
a different frame of pixel data for display on said display surface
at a different moment of time.
12. The silicon chip of claim 1, wherein when said parallelization
mode of operation is said image division mode, each GPU renders a
subset of the pixels used to compose each frame of pixel data to be
displayed on said display surface.
13. The silicon chip of claim 1, wherein when said parallelization
mode of operation is said object division mode, the 3D object which
is to be displayed as an image consisting of a frame of pixels, is
decomposed into said stream of geometrical data and graphic
commands which are distributed to said GPU-driven pipeline cores
for rendering the frames of pixel data compositing the images to be
displayed on said display surface.
14. The silicon chip of claim 13, wherein each said 3D object is
decomposable into a plurality of polygons, and wherein said
geometrical data comprises the vertices of said polygons.
15. The silicon chip of claim 1, wherein said software multi-pipe
drivers further comprise one or more of the following software
modules installed in said system memory: (1) a GPU drivers module
for allowing said GPU-driven pipeline cores to interact with said
OS and said graphic libraries; (2) a distributed graphic functions
control module for performing functions associated with carrying on
said parallelization modes according to a parallelization policy
management; (3) a state monitoring driver module for continuously
analyzing substantially all incoming commands, including state
commands, transferring certain state commands and some of the data
all of said GPU-driven pipeline cores so as to preserve the valid
state across said GPU-driven graphic pipeline cores; (4) an
application profiling and analysis driver module for performing
real-time continuous monitoring of application parameters in said
PC-based computing system, identifying problem areas likely to
cause data bottlenecks; (5) parallelism policy management driver
module for determining, on a per-frame basis, the parallelization
mode of said GPU-driven pipeline cores, using the results of said
application profiling and analysis driver module, and for such
determination to be carried out by said control unit.
16. The silicon chip of claim 15, wherein said application
profiling and analysis driver modules uses inputs from (i) the
registers of said multiple GPU-driven pipeline cores, and (ii)
registers of said control unit, and graphic API commands.
17. The silicon chip of claim 1, wherein when said parallelization
mode of operation is said object division mode of parallel
operation, wherein the 3D object which is to be displayed as an
image consisting of a frame of pixels, is decomposed into said
stream of geometrical data and graphic commands which are
distributed to said GPU-driven pipeline cores for rendering the
frames of pixel data compositing the images to be displayed on said
display surface.
18. The silicon chip of claim 1, wherein said dynamically
determining and controlling said parallelization mode during any
particular frame of pixel data generation and display is based on
factors including the time required to render previous frames of
pixel data and bottlenecks exhibited in vertex processing and pixel
processing during the rendering of said previous frames of pixel
data.
19. The silicon chip of claim 1, wherein said parallelization mode
operation is based on any combination of said object division mode,
said image division mode and said time division mode.
20. The silicon chip claim 1, wherein during said dynamically
determining and controlling said parallelization mode, said
software multi-pipe drivers analyze collected parameters including
data selected from the group consisting of: memory speed, memory
usage in bytes, total pixels rendered, geometric data entering
rendering, frame rate, workload of each pipeline core, load balance
among graphic pipelines, volumes of transferred data, textures
count, and depth complexity.
21. The silicon chip of claim 1, wherein the number of said
GPU-driven pipeline cores has no architectural limit.
22. The silicon chip of claim 1, wherein said GPU-driven pipeline
cores are organized in different parallelization modes for solving
performance bottlenecks.
23. The silicon chip of claim 1, wherein at least one said
GPU-driven pipeline core is realized on said silicon chip, along
with said routing unit and said control unit.
24. The silicon chip of claim 1, in combination with a graphics
card on which said silicon chip is mounted.
25. The silicon chip of claim 1, having a multi-processor
system-on-a-chip (MP-SOC) architecture.
Description
RELATED CASES
[0001] This Application is a Continuation of U.S. application Ser.
No. 11/340,402 filed Jan. 25, 2006; which is a Continuation-in-Part
of provisional Application No. 60/647,146 filed Jan. 25, 2005;
International Application No. PCT/IL2004/000079 filed Jan. 28,
2004, published as WIPO Publication No. WO 2004/070652 A2 on Aug.
19, 2004; and International Application No. PCT/IL2004/001069 filed
Nov. 19, 2004, published as WIPO Publication No. WO 2005/050557 A2
on Jun. 2, 2005, and entered in the U.S. National Stage on May 17,
2006 as U.S. application Ser. No. 10/579,682, and based on U.S.
provisional Application Nos. 60/523,084 and 60/523,102, both filed
Nov. 19, 2003; each Application being commonly owned by Lucid
Information Technology Ltd, of Israel, and incorporated fully
herein.
BACKGROUND OF INVENTION
[0002] 1. Field of the Invention
[0003] Over the past few decades, much of the research and
development in the graphics architecture field has been concerned
the ways to improve the performance of three-dimensional (3D)
computer graphics rendering. Graphics architecture is driven by the
same advances in semiconductor technology that have driven
general-purpose computer architecture. Many of the same
acceleration techniques have been used in this field, including
pipelining and parallelism. The graphics rendering application,
however, imposes special demands and makes available new
opportunities. For example, since image display generally involves
a large number of repetitive calculations, it can more easily
exploit massive parallelism than can general-purpose
computations.
[0004] In high-performance graphics systems, the number of
computations highly exceeds the capabilities of a single processing
unit, so parallel systems have become the rule of graphics
architectures. A very high-level of parallelism is applied today in
silicon-based graphics processing units (GPU), to perform graphics
computations.
[0005] Typically these computations are performed by graphics
pipeline, supported by video memory, which are part of a graphic
system. FIG. 1A shows a block diagram of a conventional graphic
system as part of PC architecture, comprising of CPU (111), system
memory (112), I/O chipset (113), high speed CPU-GPU bus (114) (e.g.
PCI express 16x), video (graphic) card (115) based on a single GPU,
and display (116). The single GPU graphic pipeline, as shown in
FIG. 1B, decomposes into two major parts: a geometry subsystem for
processing 3D graphics primitives (e.g. polygons) and a pixel
subsystem for computing pixel values. These two parts are
consistently designed for increased parallelism.
[0006] In the geometry subsystem, the graphics databases are
regular, typically consisting of a large number of primitives that
receive nearly identical processing; therefore the natural
concurrency is to partition the data into separate streams and to
process them independently. In the pixel subsystem, image
parallelism has long been an attractive approach for high-speed
rasterization architectures, since pixels can be generated in
parallel in many ways. An example of a highly parallel Graphic
Processing Unit chip (GPU) in prior art is depicted in FIG. 2A
(taken from 3D Architecture White Paper, by ATI). The geometry
subsystem consists of six (6) parallel pipes while the pixel
subsystem has sixteen (16) parallel pipes.
[0007] However, as shown in FIG. 2B, the "converge stage" 221
between these two subsystems is very problematic as it must handle
the full data stream bandwidth. In the pixel subsystem, the
multiple streams of transformed and clipped primitives must be
directed to the processors doing rasterization. This can require
sorting primitives based on spatial information while different
processors are assigned to different screen regions. A second
difficulty in the parallel pixel stage is that ordering of data may
change as those data pass through parallel processors. For example,
one processor may transform two small primitives before another
processor transforms a single, large one. Certain global commands,
such as commands to update one window instead of another, or to
switch between double buffers, require that data be synchronized
before and after command. This converge stage between the geometry
and pixel stages, restricts the parallelism in a single GPU.
[0008] A typical technology increasing the level of parallelism
employs multiple GPU-cards, or multiple GPU chips on a card, where
the rendering performance is additionally improved, beyond the
converge limitation in a single core GPU. This technique is
practiced today by several academic researches (e.g. Chromium
parallel graphics system by Stanford University) and commercial
products (e.g. SLI--a dual GPU system by Nvidia, Crossfire--a dual
GPU by ATI). FIG. 3 shows a commercial dual GPU system, Asus
A8N-SLI, based on Nvidia SLI technology.
[0009] Parallelization is capable of increasing performance by
releasing bottlenecks in graphic systems. FIG. 2C indicates typical
bottlenecks in a graphic pipeline that breaks-down into segmented
stages of bus transfer, geometric processing and fragment fill
bound processing. A given pipeline is only as strong as the weakest
link of one of the above stages, thus the main bottleneck
determines overall throughput. As indicated in FIG. 2C, pipeline
bottlenecks stem from: (231) geometry, texture, animation and meta
data transfer, (232) geometry data memory limits, (233) texture
data memory limits, (234) geometry transformations, and (235)
fragment rendering.
[0010] There are different ways to parallelize the GPUs, such as:
time-division (each GPU renders the next successive frame);
image-division (each GPU renders a subset of the pixels of each
frame); and object-division (each GPU renders a subset of the whole
data, including geometry and textures), and derivatives and
combinations of thereof. Although promising, this approach of
parallelizing cluster of GPU chips suffers from some inherent
problems, such as: restricted bandwidth of inter-GPU communication;
mechanical complexity (e.g. size, power, and heat); redundancy of
components; and high cost.
[0011] Thus, there is a great need in the art for an improved
method of and apparatus for high-speed graphics processing and
display, which avoids the shortcomings and drawbacks of such prior
art apparatus and methodologies.
OBJECTS AND SUMMARY OF THE PRESENT INVENTION
[0012] Accordingly, a primary object of the present invention is to
provide a novel method of and apparatus for high-speed graphics
processing and display, which avoid the shortcomings and drawbacks
of prior art apparatus and methodologies.
[0013] Another object of the present invention is to provide a
novel graphics processing and display system having multiple
graphics cores with unlimited graphics parallelism, getting around
the inherent converge bottleneck of a single GPU system.
[0014] Another object of the present invention is to provide a
novel graphics processing and display system which ensures the best
graphics performance, eliminating the shortages of a multi-chip
system, the restricted bandwidth of inter-GPU communication,
mechanical complexity (size, power, and heat), redundancy of
components, and high cost.
[0015] Another object of the present invention is to provide a
novel graphics processing and display system that has an amplified
graphics processing and display power by parallelizing multiple
graphic cores in a single silicon chip.
[0016] Another object of the present invention is to provide a
novel graphics processing and display system that is realized on a
silicon chip having a non-restricted number of multiple graphic
cores.
[0017] Another object of the present invention is to provide a
novel graphics processing and display system that is realized on a
silicon chip which utilizes a cluster of multiple graphic
cores.
[0018] Another object of the present invention is to provide a
novel graphics processing and display system that is realized on a
silicon chip having multiple graphic cores or pipes (i.e. a
multiple-pipe system-on-chip, or MP-SOC) and providing
architectural flexibility to achieve the advanced parallel graphics
display performance.
[0019] Another object of the present invention is to provide a
novel graphics processing and display system that is realized on a
silicon chip having multiple graphic cores, and adaptively
supporting different modes of parallelism within both its geometry
and pixel processing subsystems.
[0020] Another object of the present invention is to provide a
novel graphics processing and display system that is realized on a
silicon chip having multiple GPU cores, and providing adaptivity
for highly advanced graphics processing and display
performance.
[0021] Another object of the present invention is to provide a
novel graphics processing and display system and method, wherein
the graphic pipeline bottlenecks of vertex (i.e. 3D polygon
geometry) processing and fragment processing are transparently and
intelligently resolved.
[0022] Another object of the present invention to provide a method
and system for an intelligent decomposition of data and graphic
commands, preserving the basic features of graphic libraries as
state machines and tightly sticking to the graphic standard.
[0023] Another object of the present invention to provide a new PCI
graphics card supporting a graphics processing and display system
realized on a silicon chip having multiple graphic cores, and
providing architectural flexibility to achieve the best parallel
performance.
[0024] Another object of the present invention to provide a
computing system having improved graphics processing and display
capabilities, employing a graphics card having a silicon chip with
multiple graphic cores, and providing architectural flexibility to
achieve the best parallel performance.
[0025] Another object of the present invention to provide such a
computing system having improved graphics processing and display
performance required by applications including, video-gaming,
virtual reality, scientific visualization, and other interactive
application requiring or demanding photo-realistic graphics display
capabilities.
[0026] These and other objects and advantages of the present
invention will become apparent hereinafter.
BRIEF DESCRIPTION OF DRAWINGS OF THE PRESENT INVENTION
[0027] For a more complete understanding of how to practice the
Objects of the Present Invention, the following Detailed
Description of the Illustrative Embodiments can be read in
conjunction with the accompanying Drawings, briefly described
below, wherein:
[0028] FIG. 1A is a schematic representation of a prior art,
standard PC architecture, in which its conventional single GPU
graphic card is shown circled;
[0029] FIG. 1B is a simplified block diagram of a prior art
conventional graphics system employing a single GPU, having
geometry and pixel processing subsystems, wherein the data converge
stream therebetween presents a serious system bottleneck that
significantly limits performance;
[0030] FIG. 2A is a schematic diagram illustrating high parallelism
in a typical prior art ATI X800 Graphic Processing Unit chip (GPU),
wherein the geometry subsystem consists of 6 parallel pipes and the
pixel subsystem consists of 16 parallel pipes;
[0031] FIG. 2B is a schematic diagram of the internal portion of a
prior art graphic processing unit (GPU) chip (e.g. ATI X800)
illustrating the bottlenecking converge stage (setup engine)
between geometric and pixel parallel engines therein;
[0032] FIG. 2C is a schematic representation of a conventional
graphics pipeline, illustrating the data bottleneck problem
existing therein;
[0033] FIG. 3 is a photograph of a prior art dual GPU-driven video
graphics card;
[0034] FIG. 4A is a schematic system block diagram representation
of a computing system employing a printed circuit graphics card
employing the multiple-pipe system-on-chip (MP-SOC) device in
accordance with the principles of the present invention, wherein
the system block diagram shows the CPU, I/O chipset, system memory,
graphic card based on MP-SOC, and display screen(s);
[0035] FIG. 4B is schematic representation of the physical
implementation of the MP-SOC of the present invention, mounted on a
printed circuit (PC) video graphics board;
[0036] FIG. 4C is a photograph of a standard PCI express graphics
slot on a motherboard to which MP-SOC-based PC graphics board of
the present invention is interconnected;
[0037] FIG. 4D is a schematic representation of an exemplary MP-SOC
silicon-layout including four GPU-driven pipeline cores according
to the principles of the present invention;
[0038] FIG. 4E is a schematic representation of an exemplary
packaging of the MP-SOC chip of the present invention;
[0039] FIG. 5 is a schematic block diagram of the MP-SOC
architecture, according to the illustrative embodiment of the
present invention;
[0040] FIG. 6 is the software block diagram of MP-SOC based
computing system, according to the illustrative embodiment of the
present invention;
[0041] FIG. 7A is a schematic block diagram further illustrating
the modules that comprise the multi-pipe software drivers of MP-SOC
based system of the illustrative embodiment of the present
invention;
[0042] FIG. 7B is a flow chart illustrating the steps carried out
by the mechanism that runs the three parallelization modes (i.e.
Object Division, Image Division and Time Division) within the
MP-SOC-based devices and systems of the present invention;
[0043] FIG. 8 is a schematic representation illustrating the
object-division configuration of the MP-SOC system of the present
invention;
[0044] FIG. 9 is a schematic representation illustrating the
image-division configuration of the MP-SOC system of the present
invention;
[0045] FIG. 10 is a schematic representation illustrating the
time-division configuration of the MP-SOC system of the present
invention;
[0046] FIG. 11 is a flowchart illustrating the process for
distributing polygons between multiple GPU-driven pipeline cores
along the MP-SOC-based system of the present invention; and
[0047] FIG. 12 shows an example of eight (8) GPU-driven pipeline
cores arranged as a combination of parallel modes, in accordance
with the principles of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0048] The techniques taught in Applicant's prior PCT application
No. PCT/IL04/001069, published as WIPO Publication No. WO
2005/050557 A2, incorporated herein by reference, teaches the use
of a graphics scalable Hub architecture, comprised of Hardware Hub
and Software Hub Driver, which serves to glue together (i.e.
functioning in parallel) off-the-shelf GPU chips for the purpose of
providing a high performance and scalable visualization solution,
object division decomposition algorithm, employing multiple
parallel modes and combination thereof, and adaptive parallel mode
management. Also, PCT Application No. PCT/IL2004/000079, published
as WIPO Publication No. WO 2004/070652 A2, incorporated herein by
reference, teaches the use of compositing image mechanism based on
associative decision making, to provide fast and non-expensive
re-compositing of frame buffers as part of Object Division
parallelism.
[0049] The approaches taught in Applicant's PCT Applications
identified above have numerous advantages and benefits, namely the
ability to construct powerful parallel systems by use of
off-the-shelf GPUs, transparently to existing applications.
However, in many applications, it will be desirable to provide such
benefits in conventional graphics systems, using an alternative
approach, namely: by providing PCs with a graphics processing and
display architecture employing powerful graphics processing and
display system realized on monolithic silicon chips, for the
purpose of delivering high performance, high frame-rate stability
of graphic solutions at relatively low-cost, and transparency to
existing graphics applications.
[0050] The benefits of this novel alternative approach include
VLSI-based miniaturization of multi-GPU clusters, high bandwidth of
inter-GPU communication, lower power and heat dissipation, no
redundancy of components, and low cost. Details on practicing this
alternative approach will now be described below.
[0051] In general, the present invention disclosed herein teaches
an improved way of and a means for parallelizing graphics functions
on a semiconductor level, as a multiple graphic pipeline
architecture realized on a single chip, preferably of monolithic
construction. For convenience of expression, such a device is
termed herein as a "multi-pipe system on chip" or "MP-SOC". This
system "on a silicon chip" comprises a cluster of GPU-driven
pipeline cores organized in flexible topology, allowing different
parallelization schemes. Theoretically, the number of pipeline
cores is unlimited, restricted only by silicon area considerations.
The MP-SOC is driven by software driver modes, which re resident to
the host CPU. The variety of parallelization schemes enables
performance optimization. These schemes are time, image and object
division, and derivatives of thereof.
[0052] The illustrative embodiment of the present invention enjoys
the advantages of a multi GPU chip, namely: bypassing the converge
limitation of a single GPU, while at the same time it gets rid of
the inherent problems of a multi-GPU system, such as restricted
bandwidth of inter-GPU communication, mechanical complexity (size,
power, and heat), redundancy of components, and high cost.
[0053] As shown in FIG. 4A, the physical graphic system of the
present embodiment comprises of a conventional motherboard (418)
and MP-SOC based graphic card (415). The motherboard carries the
usual set of components, which are CPU (411), system memory (412),
I/O chipset (413), and other non-graphic components as well (see
FIG. 1A for the complete set of components residing on a PC
motherboard). The printed circuit graphic card based on the MP-SOC
chip 416) connects to the motherboard via a PCI express 16x lanes
connector (414). The card has also an output to at least one screen
(416). The MP-SOC graphic card replaces the conventional single-GPU
graphic card on the motherboard. The way the MP-SOC graphic card
integrates in a conventional PC system becomes apparent from
comparing FIG. 4A with FIG. 1A By simply replacing the single-GPU
graphic card (circled in FIG. 1A) with the MP-SOC based card of the
present invention, and replacing its drivers with the multi-pipe
soft drivers on the host CPU (419), the system of invention is
realized with all of the advantages and benefits described herein.
This modification is completely transparent to the user and
application, apart from the improved performance.
[0054] FIG. 4B shows a possible physical implementation of the
present invention. A standard form PC card (421) on which the
MP-SOC (422) is mounted, connects to the motherboard (426) of the
host computing system, via PCI express 16x lanes connector (423).
The display screen is connected via standard DVI connector (424).
Since the multiple pipelines on MP-SOC are anticipated to consume
high power, for which the standard supply via PCI express connector
is not adequate, an auxiliary power is supplied to the card via
dedicated power cable (425).
[0055] FIG. 4C shows the PCI express connector (431) on a
motherboard to which a MP-SOC based card connects. It should be
emphasized that the standard physical implementation of MP-SOC on a
PC card makes it an easy and natural replacement of the prior art
GPU-driven video graphics cards.
[0056] FIGS. 4D and 4E describe an artist's concept of the MP-SOC
chip to further illustrate a physical implementation of the
semiconductor device. FIG. 4D shows a possible MP-SOC silicon
layout. In this example there are 4 off-the-shelf cores of graphic
pipelines. The number of cores can be scaled to any number, pending
silicon area restrictions. The detailed discussion on the MP-SOC
functional units is given below. FIG. 4E shows possible packaging
and appearance of the MP-SOC chip. As mentioned before, this chip,
along with other peripheral components (e.g. memory chips, bus
chips, etc.) intends to be mounted on a standard sized PCB (printed
circuit board) and used as a sole graphic card in a PC system,
replacing prior art video graphics cards. Production of MP-SOC
based cards can be carried out by graphic card manufacturers (e.g.
AsusTech, Gigabyte).
[0057] As presented in FIG. 5, the multi-pipe-SOC architecture
consists of the following components: [0058] Routing center which
is located on the CPU bus (e.g. PCI express of 16 lanes). It
distributes the graphics data stream, coming from CPU among graphic
pipeline cores, and then collects the rendered results (frame
buffers) from cores, to the compositing unit. The way data is
distributed is dictated by the control unit, depending on current
parallelization mode. [0059] Compositing unit re-composes the
partial frame buffers according to the ongoing parallelization
mode. [0060] Control unit is under control of the CPU-resident soft
multi-pipe driver. It is responsible for configuration and
functioning of the entire MP-SOC system according to the
parallelization mode. [0061] Processing element (PE) unit with
internal or external memory, and optional cache memory. The PE can
be any kind of processor-on-chip according to architectural needs.
Besides serving the PE, the cache and memory can be used to cache
graphics data common to all pipeline cores, such as textures,
vertex objects, etc. [0062] Multiple GPU-driven pipeline cores.
These cores may, but need not to be of proprietary designed. They
can be originally designed as a regular single core GPU. [0063]
Profiling functions unit. This unit delivers to the multi-pipe
driver a benchmarking data such as memory speed, memory usage in
bytes, total pixels rendered, geometric data entering rendering,
frame rate, workload of each pipeline core, load balance among
pipeline cores, volumes of transferred data, textures count, and
depth complexity. [0064] Display interface, capable of running
single or multiple screens.
[0065] As shown in FIG. 6, the software of the system comprises the
graphic application, graphics library (e.g. graphic standards
OpenGL or DirectX), and proprietary soft driver (multi-pipe
driver). The generic graphics application needs no modifications or
special porting efforts to run on the MP-SOC.
[0066] FIG. 7 shows a functional block diagram presenting the main
tasks of the multi-pipe driver, according to an embodiment the
present invention. The multi-pipe driver carries on at least the
following actions: [0067] Generic GPU drivers. Perform all the
functions of a generic GPU driver associated with interaction with
the Operation System, graphic library (e.g. OpenGL or DirectX), and
controlling the GPUs. [0068] Distributed graphic functions control.
This module performs all functions associated with carrying on the
different parallelization modes according to parallelization policy
management. In each mode, the data is differently distributed and
re-composed among pipelines, as will be described in greater detail
hereinafter. [0069] State monitoring. The graphic libraries (e.g.
OpenGL and DirectX) are state machines. Parallelization must
preserve cohesive state across the graphic system. It is done by
continuous analysis of all incoming commands, while the state
commands and some of the data must be multiplicated to all
pipelines in order to preserve the valid state across the graphic
pipelines. A specific problem is posed by the class called Blocking
operations such as Flush, Swap, Alpha blending, which affect the
entire graphic system, setting the system to blocking mode.
Blocking operations are exceptional in that they require a composed
valid FB data, thus in the parallel setting of the present
invention, they have an effect on all pipeline cores. A more
detailed description of handling Blocking operations will be given
hereinafter. [0070] Application profiling and analysis module. This
module performs real-time profiling and analysis of the running
application. It continuously monitors of application parameters in
the system, such as memory speed, memory usage in bytes, total
pixels rendered, geometric data entering rendering, frame rate,
workload of each pipeline core, load balance among graphic
pipelines, volumes of transferred data, textures count, and depth
complexity, etc. The profiler module identifies problem areas
within the graphics system which cause bottlenecks. The profiler
module requires inputs from the registers of the multi-pipe cores,
registers of the MP-SOC control unit, and graphic API commands
(e.g. OpenGL, DirectX). [0071] Parallelism policy management makes
a decision on the parallel mode to be performed, on a per-frame
basis, based on the above profiling and analysis. The decision is
then carried out by means of the control unit in the MP-SOC. [0072]
A major feature of the present invention is its topological
flexibility which enables revamping of performance bottlenecks.
Such flexibility is gained by rearranging the cluster of graphics
pipelines by means of routing center and different merging schemes
at the compositing unit. Different parallelization schemes affect
different performance bottlenecks. Therefore bottlenecks,
identified by the profiling module, can be cured by utilizing the
corresponding parallelization scheme.
[0073] The flowchart of FIG. 7B describes the mechanism that runs
the three parallel modes: Object Division, Image Division and Time
Division. The mechanism combines the activity of soft driver
modules with MP-SOC units. The cycle of the flowchart is one frame.
The mode to begin with is the Object Division (OD), since it is the
preferred parallel mode, as it will be explained hereinafter. The
profiling and analysis of the application is constantly on, under
control of the soft Profile and Analysis module (S-PA). Every frame
the Parallel Policy Management (S-PPM) module checks for the
optimal mode, to choose from the three parallelization modes.
[0074] Let us assume that the Object Division (OD) path was taken.
The Distributed Graphic Functions Control (S-DGFC) module
configures the entire system for OD, characterized by distribution
of geometric data and the compositing algorithm in use. This
configuration is shown in FIG. 8, and described in detail later on.
The S-DGFC module decomposes the geometric data into partitions,
each sent by the Routing unit (C-RC) to different GPU-driven pipe
core (C-PC) for rendering. The rendered stream of data is monitored
by the State Monitoring (S-SM) module for blocking commands, as
shown in FIG. 11, and described in great detail hereinafter. When
the rendering is completed, all the Frame Buffers are moved by the
Control Unit (C-Ctrl) to Compositing Unit (C-CU) to composite all
buffers to a single one, based on depth test (as explained in
detail below). The final FB is moved to Display by Display
Interface Unit (C-DI). At the end of the frame the S-PA and S-PPM
modules test for the option of changing the parallel mode. If
decision was taken to stay with the same mode, a new OD frame
starts with another data partition. Otherwise, a new test for
optimal mode is performed by S-PA and S-PPM modules.
[0075] The left path in the flowchart is Image Division (ID)
operation. The ID configuration, as set by the S-DGFC, is also
shown in FIG. 9, and described later in greater detail. It is
characterized by broadcasting of the same data among all pipe
cores, and by image based compositing algorithm. The partitioning
of image among pipe cores is done by S-DGFC. The data is broadcast
by the Routing Center, and then rendered at pipe cores (C-PC),
while each one is designated another portion of image. Upon
accomplishing of rendering, the C-Ctrl moves the partial FBs to
compositing unit (C-CU) for reconstruction of the complete image.
Then C-DI moves the FB to Display. Finally the Change test is
performed by S-PS and S-PPM modules. Pending the result, a new
frame will continue the ID mode, or switch to another mode.
[0076] The Time Division mode alternates frames among the
GPU-driven pipe cores. It is set for alternation by the S-GDFC
module, while each core is designated a frame data by S-DGFC and
delivered by the C-RC unit. Each core (C-PC) generates a frame, in
a line. Then the C-Ctrl moves the matured FB via compositing unit
to the Display Interface, and out to the display. Actually, the
compositing unit in this mode acts just as a transit. Finally there
is a change-mode test by S-PA and S-PPM modules, same as in the
other modes before.
[0077] FIG. 8 describes the object-division parallelization scheme.
The soft driver, and specifically the Distributed Graphic Functions
Control module, breaks down the polygon data of a scene into N
partial streams (N--the number of participating pipeline cores).
The entire data is sent, by the GPU Drivers module, to the MP-SOC
Routing Center, which distributes the data to N pipeline cores for
rendering, according to the soft driver's partition, each of
approximately 1/N polygons. Rendering in the pipeline cores is done
under the monitoring of State Monitoring module of the soft driver
(FIG. 11 and detailed description below). The resultant full frame
buffers are gathered in the Compositing Unit. They are
depth-composed, pixel by pixel to find the final set of visible
pixels. At each x-y coordinate all hidden pixels are eliminated by
compositing mechanism. The final frame buffer is moved out to
display.
[0078] FIG. 9 describes the image-division parallelization scheme,
which is chosen by Parallelism Policy Management module, as a
result of profiling, analysis, and decision making in the Profiling
and Analysis module of the soft driver. Each pipeline core is
designated a unique 1/N part of the screen. The complete polygon
data is delivered to each of the pipeline cores via the GPU Driver
module and Routing Center. The parallel rendering in pipeline cores
results in partial frame buffer at each. The image segments are
moved to the Compositing Unit for 2D merging into a single image
and moved out to the display.
[0079] FIG. 10 describes the time-division parallelization scheme
which is chosen by Parallelism Policy Management module, as a
result of profiling, analysis, and decision making in the Profiling
and Analysis module of the soft driver. The Distributed Graphic
Functions Control module, through GPU Drivers module, divides the
frames into N cycles (N=number of cores) letting each core time
slot of N frames for rendering the entire polygon data. Therefore
the scene polygon data is distributed, via Router, to a different
pipeline core at a time Each core performs rendering during N
cycles, and outputs its full frame buffer to display, for a single
frame. The Compositing unit functions here as a simple switch,
alternating the access to the Display among all the pipeline
cores.
[0080] Different parallelization schemes resolve different
performance bottlenecks. Therefore bottlenecks must be identified
and then eliminated (or reduced) by applying the right scheme at
the right time.
[0081] As shown in FIG. 7B, the profiler identifies problem areas
within the graphics system which cause bottlenecks. It is
implemented in the Application Profiling and Analysis module of the
driver. The profiler module requires such inputs as usage of
graphic API commands (e.g. OpenGL, DirectX, other), memory speed,
memory usage in bytes, total pixels rendered, geometric data
entering rendering, frame rate, workload of each GPU, load balance
among GPUs, volumes of transferred data, textures count, and depth
complexity, etc. These data types are collected from the following
sources within the MP-SOC based graphics system: [0082] 1. The
profiling functions unit in MP-SOC [0083] 2. The driver [0084] 3.
The pipeline cores [0085] 4. Chipset Architecture Performance
(CHAP) Counters [0086] 5. Typically, the performance data is
retrieved on a frame time basis, however, the periodicity can also
be a configuration attribute of the profiler, or can be set based
on a detected configuration event which the profiler is designed to
detect before retrieving performance data.
[0087] The analysis, resulting in the selection of a preferred
parallel method is based on the assumption that in a well defined
case (described below), object-division method supersedes the other
division modes in that it reduces more bottlenecks. In contrast to
image-division, that reduces only the fragment/fill bound
processing at each pipeline core, the object-division relaxes
virtually all bottleneck across the pipeline: (i) the geometry
(i.e. polygons, lines, dots, etc) transform processing is offloaded
at each pipeline, handling only 1/N of polygons (N--number of
participating pipeline cores); (ii) fill bound processing is
reduced since less polygons are feeding the rasterizer, (iii) less
geometry memory is needed; (iv) less texture memory is needed.
[0088] Although the time-division method releases bottlenecks by
allowing to each pipeline core more time per frame generation,
however this method suffers from severe problems such as CPU
bottlenecks, the pipeline cores generated frame buffers that are
not available to each other, and there are frequent cases of
pipeline latency. Therefore this method is not suitable to all
applications. Consequently, due to its superiority as bottleneck
opener, object-division becomes the primary parallel mode.
[0089] The following object division algorithm distributes polygons
among the multiple graphic pipeline cores. Typical application
generates a stream of graphic calls that includes blocks of graphic
data; each block consists of a list of geometric operations, such
as single vertex operations or buffer based operations (vertex
array). Typically, the decomposition algorithm splits the data
between pipeline cores preserving the blocks as basic data units.
Geometric operations are attached to the block(s) of data,
instructing the way the data is handled. A block is directed to
designated GPU. However, there are operations belonging to the
group of Blocking Operations, such as Flush, Swap, Alpha blending,
which affect the entire graphic system, setting the system to
blocking mode. Blocking operations are exceptional in that they
require a composed valid FB data, thus in the parallel setting of
the present invention, they have an effect on all pipeline cores.
Therefore, whenever one of the Blocking operations is issued, all
the pipeline cores must be synchronized. Each frame has at least 2
blocking operations: Flush and Swap, which terminate the frame.
[0090] FIG. 11 presents a flowchart describing an algorithm for
distributing polygons among multiple GPU-driven pipeline cores,
according to an illustrative embodiment of the present invention.
The frame activity starts with distributing blocks of data among
GPUs. Each graphic operation is tested for blocking mode at step
1112. In a regular path (non-blocking path), data is redirected to
the designated pipeline core at step 1113. This loop is repeated
until a blocking operation is detected.
[0091] When the blocking operation is detected, all pipeline cores
must be synchronized at step 1114 by at least the following
sequence: [0092] performing a flush operation in order to terminate
rendering and clean up the internal pipeline (flushing) in pipeline
core; [0093] performing a composition in order to merge the
contents of all FBs into a single FB; and [0094] transmitting the
contents of said single FB back to all pipeline cores, in order to
create a common ground for continuation.
[0095] The Swap operation activates the double buffering mechanism,
swapping the back and front color buffers. If Swap is detected at
step 1115, it means that the composited frame must be terminated at
all pipeline cores, except pipeline 0. All pipeline cores have the
final composed contents of a FB designated to store said contents,
but only the one connected to the screen (pipeline 0) displays the
image at step 1116.
[0096] Another case is operations that are applied globally to the
scene and need to be broadcasted to all the pipeline cores. If one
of the other blocking operations is identified, such as Alpha
blending for transparency, then all pipeline cores are flushed as
before at step 1114, and merged into a common FB. This time the
Swap operation is not detected (step 1115), therefore all pipeline
cores have the same data, and as long as the blocking mode is on
(step 1117), all of them keep processing the same data (step 1118).
If the end of the block mode is detected at step 1117, pipeline
cores return working on designated data (step 1113).
[0097] The relative advantage of object-division depends very much
on depth complexity of the scene. Depth complexity is the number of
fragment replacements as a result of depth tests (the number of
polygons drawn on every pixel). In the ideal case of no fragment
replacement (e.g. all polygons of the scene are located on the same
depth level), the fill is reduced according to the reduced number
of polygons (as for 2 pipeline cores). However, when depth
complexity is getting high, the advantage of object-division drops
down, and in some cases the image-division may even perform better,
e.g. applications with small number of polygons and high volume of
textures.
[0098] In addition, the present invention introduces a dynamic
load-balancing technique that combines the object division method
with the image division and time division methods in image and time
domains, based on the load exhibits by previous processing stages.
Combining all the three parallel methods into a unified framework
dramatically increases the frame rate stability of the graphic
system.
[0099] FIG. 12 discloses a sample configuration of the system,
employing 8 pipeline cores, according to an embodiment of the
present invention. According to the above sample configuration, a
balanced graphic application is assumed. The pipeline cores are
divided into two groups for time division parallelism. Pipeline
cores indexed with 1, 2, 3, and 4 are configured to process even
frames and pipeline cores indexed with 5, 6, 7, and 8 are
configured to process odd frames. Within each group, two pipeline
core subgroups are set for image division: the pipeline cores with
the lower indexes (1,2 and 5,6 respectively) are configured to
process half of the screen, and the high-indexed pipeline cores
(3,4 and 7,8 respectively) are configured to process the other
half. Finally, for the object division, pipeline cores indexed with
1, 3, 5 and 7 are fed with half of the objects, and pipeline cores
indexed with 2, 4, 6 and 8 are fed with the other half of the
objects.
[0100] If at some point the system detects that the bottlenecks
exhibited in previous frames occur at the raster stage of the
pipeline, it means that fragment processing dominates the time it
takes to render the frames and that the configuration is
imbalanced. At that point the pipeline cores are reconfigured, so
that each pipeline core will render a quarter of the screen within
the respective frame. The original partition for time division,
between pipeline cores 1,2,3,4 and between 5,6,7,8 still holds, but
pipeline core 2 and pipeline core 5 are configured to render the
first quarter of screen in even and odd frames respectively.
Pipeline cores 1 and 6--render the second quarter, pipeline cores 4
and 7--the third quarter, and pipeline cores 3 and 8--the forth
quarter. No object division is implied.
[0101] In addition, if at some point the system detects that the
bottleneck exhibited in previous frames occurs at the geometry
stage of the pipe, the pipeline cores are reconfigured, so that
each pipeline core will process a quarter of the geometrical data
within the respective frame. That is, pipeline cores 3 and 5 are
configured to process the first quarter of the polygons in even and
odd frames respectively. Pipeline cores 1 and 7--render the second
quarter, pipeline cores 4 and 6--the third quarter and pipeline
cores 2 and 8--the forth quarter. No image division is implied.
[0102] It should be noted, that taking 8 pipeline cores is
sufficient in order to combine all three parallel modes, which are
time, image and object division modes, per frame. Taking the number
of pipeline cores larger than 8, also enables combining all 3
modes, but in a non-symmetric fashion. The flexibility also exists
in frame count in a time division cycle. In the above example, the
cluster of 8 pipeline cores was broken down into the two groups,
each group handling a frame. However, it is possible to extend the
number of frames in a time division mode to a sequence, which is
longer than 2 frames, for example 3 or 4 frames.
[0103] Taking a smaller number of pipeline cores still allows the
combination of the parallel modes, however the combination of two
modes only. For example, taking only 4 pipeline cores enables to
combine image and object division modes, without time division
mode. It is clearly understood from FIG. 12, while taking the group
of pipeline cores 1-4, which is the left cluster. Similarly, the
group of pipeline cores 1,2,5, and 6 which consist the upper
cluster, employs both object and time division modes. Finally, the
configuration of the group of pipeline cores 2,4,5, and 6, which is
the middle cluster, employs image and time division modes.
[0104] It should be noted, that similarly to the above embodiments,
any combination between the parallel modes can be scheduled to
evenly balance the graphic load.
[0105] It also should be noted, that according to the present
invention, the parallelization process between all pipeline cores
may be based on an object division mode or image division mode or
time division mode or any combination thereof in order to optimize
the processing performance of each frame.
[0106] The decision on parallel mode is done on a per-frame basis,
based on the above profiling and analysis. It is then carried out
by reconfiguration of the parallelization scheme, as described
above and shown in FIGS. 8, 9, 10 and 12.
[0107] The MP-SOC architecture described in great detail
hereinabove can be readily adapted for use in diverse kinds of
graphics processing and display systems. While the illustrative
embodiments of the present invention have been described in
connection with PC-type computing systems, it is understood that
the present invention can be use improve graphical performance in
diverse kinds of systems including mobile computing devices,
embedded systems, and as well as scientific and industrial
computing systems supporting graphic visualization of
photo-realistic quality.
[0108] It is understood that the graphics processing and display
technology described in the illustrative embodiments of the present
invention may be modified in a variety of ways which will become
readily apparent to those skilled in the art of having the benefit
of the novel teachings disclosed herein. All such modifications and
variations of the illustrative embodiments thereof shall be deemed
to be within the scope and spirit of the present invention as
defined by the Claims to Invention appended hereto.
* * * * *