U.S. patent application number 11/540346 was filed with the patent office on 2008-04-24 for multiplier product generation based on encoded data from addressable location.
This patent application is currently assigned to INTEL CORPORATION. Invention is credited to Steven K. Hsu, Ram Krishnamurthy, Sanu Mathew, Vishak Venkatraman.
Application Number | 20080098278 11/540346 |
Document ID | / |
Family ID | 39319489 |
Filed Date | 2008-04-24 |
United States Patent
Application |
20080098278 |
Kind Code |
A1 |
Mathew; Sanu ; et
al. |
April 24, 2008 |
Multiplier product generation based on encoded data from
addressable location
Abstract
For one disclosed embodiment, an apparatus comprises first
circuitry to output encoded data from an addressable location based
at least in part on an address corresponding to a first number,
wherein the encoded data is based at least in part on data that
corresponds to the first number and that is encoded for partial
product reduction, and second circuitry to generate a product based
at least in part on the encoded data and on data corresponding to a
second number. Other embodiments are also disclosed.
Inventors: |
Mathew; Sanu; (Hillsboro,
OR) ; Venkatraman; Vishak; (Sunnyvale, CA) ;
Hsu; Steven K.; (Lake Oswego, OR) ; Krishnamurthy;
Ram; (Portland, OR) |
Correspondence
Address: |
INTEL CORPORATION;c/o INTELLEVATE, LLC
P.O. BOX 52050
MINNEAPOLIS
MN
55402
US
|
Assignee: |
INTEL CORPORATION
|
Family ID: |
39319489 |
Appl. No.: |
11/540346 |
Filed: |
September 29, 2006 |
Current U.S.
Class: |
714/763 |
Current CPC
Class: |
G06F 7/5332 20130101;
G06F 7/74 20130101; G06F 7/5334 20130101; G06F 7/533 20130101; G11C
7/1006 20130101 |
Class at
Publication: |
714/763 |
International
Class: |
G11C 29/00 20060101
G11C029/00 |
Claims
1. An apparatus comprising: first circuitry to output encoded data
from an addressable location based at least in part on an address
corresponding to a first number, wherein the encoded data is based
at least in part on data that corresponds to the first number and
that is encoded for partial product reduction; and second circuitry
to generate a product based at least in part on the encoded data
and on data corresponding to a second number.
2. The apparatus of claim 1, wherein the first circuitry includes
memory to store encoded data corresponding to different
numbers.
3. The apparatus of claim 1, wherein the first circuitry includes
encoding circuitry to encode data corresponding to a number and to
output encoded data to an addressable location.
4. The apparatus of claim 3, wherein the encoding circuitry is to
use Booth or modified Booth encoding.
5. The apparatus of claim 3, wherein the encoding circuitry is to
use leading zeroes detection (LZD) or modified LZD.
6. The apparatus of claim 1, wherein the second circuitry includes
partial product generation circuitry to generate data corresponding
to different potential partial products for data corresponding to
the second number.
7. The apparatus of claim 1, wherein the second circuitry includes
selection circuitry to select a partial product based at least in
part on encoded data.
8. The apparatus of claim 1, wherein the second circuitry includes
partial product reduction circuitry.
9. The apparatus of claim 1, wherein the second circuitry includes
an adder.
10. The apparatus of claim 1, wherein the first number is a
multiplier and the second number is a multiplicand.
11. An apparatus comprising: means for outputting encoded data from
an addressable location based at least in part on an address
corresponding to a first number, wherein the encoded data is based
at least in part on data that corresponds to the first number and
that is encoded for partial product reduction; and means for
generating a product based at least in part on the encoded data and
on data corresponding to a second number.
12. The apparatus of claim 11, wherein the means for outputting
encoded data includes means for storing encoded data corresponding
to different numbers.
13. The apparatus of claim 11, wherein the means for outputting
encoded data includes means for encoding data corresponding to a
number.
14. A method comprising: outputting encoded data from an
addressable location based at least in part on an address
corresponding to a first number, wherein the encoded data is based
at least in part on data that corresponds to the first number and
that is encoded for partial product reduction; and generating a
product based at least in part on the encoded data and on data
corresponding to a second number.
15. The method of claim 14, wherein the outputting comprises
reading encoded data from a memory based at least in part on the
address corresponding to the first number.
16. The method of claim 14, comprising encoding data corresponding
to a number.
17. The method of claim 14, wherein the encoding includes using
Booth or modified Booth encoding.
18. A system comprising: one or more energy cells; and a processor
coupled to receive power from one or more energy cells, the
processor having first circuitry to output encoded data from an
addressable location based at least in part on an address
corresponding to a first number, wherein the encoded data is based
at least in part on data that corresponds to the first number and
that is encoded for partial product reduction, and second circuitry
to generate a product based at least in part on the encoded data
and on data corresponding to a second number.
19. The system of claim 18, wherein the first circuitry includes
memory to store encoded data corresponding to different
numbers.
20. The system of claim 18, wherein the first circuitry includes
encoding circuitry to encode data corresponding to a number and to
output encoded data to an addressable location.
Description
FIELD
[0001] Embodiments described herein generally relate to
multipliers.
BACKGROUND
[0002] A processor can have a multiplier circuit to help speed the
generation of products of numbers. A processor can use a multiplier
circuit, for example, to help speed performance of digital signal
processing (DSP) applications such as, for example, finite impulse
response (FIR) filters, infinite impulse response (IIR) filters,
discrete cosine transforms (DCTs), and/or fast Fourier transforms
(FFTs). A processor can have parallel clusters of multiplier,
multiply-add, and/or multiply-accumulate circuits to help speed
performance of complex filter operations, for example.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Embodiments are illustrated by way of example and not
limitation in the figures of the accompanying drawings, in which
like references indicate similar elements and in which:
[0004] FIG. 1 illustrates, for one embodiment, a block diagram of
circuitry to generate a product based at least in part on encoded
data from an addressable location;
[0005] FIG. 2 illustrates, for one embodiment, a flow diagram to
generate a product based at least in part on encoded data from an
addressable location;
[0006] FIG. 3 illustrates, for one embodiment, a block diagram of
circuitry to output encoded data from an addressable location;
[0007] FIG. 4 illustrates, for one embodiment, a block diagram of
circuitry to generate a product based at least in part on encoded
data corresponding to a first number and data corresponding to a
second number;
[0008] FIG. 5 illustrates, for one embodiment, a block diagram of
circuitry to encode data and store encoded data at an addressable
location;
[0009] FIG. 6 illustrates, for one embodiment, a flow diagram to
output encoded data;
[0010] FIG. 7 illustrates, for one embodiment, encoding circuitry
for the block diagram of FIG. 5;
[0011] FIG. 8 illustrates, for one embodiment, circuitry to perform
modified leading zeroes detection (LZD) for the block diagram of
FIG. 7; and
[0012] FIG. 9 illustrates, for one embodiment, a block diagram of
an example system comprising a processor having circuitry to
generate a product based at least in part on encoded data from an
addressable location.
[0013] The figures of the drawings are not necessarily drawn to
scale.
DETAILED DESCRIPTION
[0014] The following detailed description sets forth example
embodiments of apparatuses, methods, and systems relating to
multiplier product generation based on encoded data from
addressable location. Features, such as structure(s), function(s),
and/or characteristic(s) for example, are described with reference
to one embodiment as a matter of convenience; various embodiments
may be implemented with any suitable one or more described
features.
[0015] FIG. 1 illustrates circuitry 100 to generate a product based
at least in part on encoded data from an addressable location.
Circuitry 100 for one embodiment, as illustrated in FIG. 1, may
include circuitry 110 to output encoded data 111 from an
addressable location based at least in part on an address 101
corresponding to a first number and circuitry 140 to generate a
product 103 based at least in part on encoded data 111 and on data
102 corresponding to a second number. Encoded data 111 for one
embodiment may be based at least in part on data that corresponds
to the first number and that is encoded for partial product
reduction. Circuitry 140 for one embodiment may generate a product
of the first number and the second number. For one embodiment, the
first number may be a multiplier and the second number may be a
multiplicand. For another embodiment, the first number may be a
multiplicand and the second number may be a multiplier.
[0016] Circuitry 110 for one embodiment may be used to output
encoded data 111 from an addressable location based at least in
part on an address 101 corresponding to the first number to help
reduce or avoid having to encode the same data repeatedly for
partial product reduction. Circuitry 110 for one embodiment may be
used to output encoded data to help speed performance of product
generation. Circuitry 110 for one embodiment may be used to output
encoded data to help reduce power consumption and/or heat
dissipation. Circuitry 110 for one embodiment may be used to help
speed performance and/or to help reduce power consumption and/or
heat dissipation particularly where circuitry 110 is used to output
encoded data 111 for a multiplier that is a constant and that is to
be repeatedly multiplied with different multiplicands.
[0017] FIG. 2 illustrates, for one embodiment, a flow diagram 200
to generate a product based at least in part on encoded data from
an addressable location. For block 202 of FIG. 2, circuitry 110 may
output encoded data 111 from an addressable location based at least
in part on address 101 corresponding to the first number. For block
204, circuitry 140 may generate product 103 based at least in part
on encoded data 111 and on data 102 corresponding to the second
number.
[0018] Encoded data 111 may correspond to a first number of any
suitable bit-length, may be based at least in part on data that is
encoded for partial product reduction in any suitable manner, and
may have any suitable size. Encoded data 111 for one embodiment may
correspond, for example, to a 16-bit first number. Encoded data 111
for one embodiment may include any suitable number of sets of any
suitable number of select bits for a first number of any suitable
bit-length.
[0019] Encoded data 111 for one embodiment may be based at least in
part on data that is encoded using Booth encoding or modified Booth
encoding, such as radix-4 Booth (or modified Booth) encoding for
example. Encoded data 111 for one embodiment may be the encoded
data resulting from Booth encoding or modified Booth encoding of
data corresponding to the first number. Encoded data 111 for one
embodiment may be 48 bits in length, that is eight sets of six
select bits, for a 16-bit number encoded using radix-4 Booth (or
modified Booth) encoding.
[0020] Encoded data 111 for one embodiment may be encoded data
resulting from further encoding of already encoded data. Such
further encoding for one embodiment may be used, for example, to
help compress encoded data. Encoded data 111 for one embodiment may
be the encoded data resulting from further encoding of already
encoded data using leading zeroes detection (LZD) or modified LZD.
Encoded data 111 for one embodiment may be encoded data resulting
from Booth encoding or modified Booth encoding of data
corresponding to the first number and further encoding of such
encoded data using LZD or modified LZD. For one embodiment where
encoded data has eight sets of six select bits where each set has
only one bit that is different from the other bits in the set, such
as only one logic one bit in the set for example, LZD or modified
LZD encoding may be used to encode the eight sets of six select
bits into eight sets of three encoded select bits for a total of 24
bits for encoded data 111.
[0021] Circuitry 110 may be coupled to receive address 101 of any
suitable bit-length from any suitable source. Circuitry 110 for one
embodiment, as illustrated in FIG. 1, may be coupled to receive
address 101 from control circuitry 130. Control circuitry 130 may
comprise any suitable circuitry to control output of address 101 to
circuitry 110 in any suitable manner. Control circuitry 130 for one
embodiment may store address 101 in one or more registers. Control
circuitry 130 for one embodiment may output address 101 to
circuitry 110 in response to data corresponding to the first
number. Control circuitry 130 for one embodiment may convert data
corresponding to the first number to address 101.
[0022] Circuitry 140 may be coupled to receive data 102 of any
suitable bit-length from any suitable source. Circuitry 140 for one
embodiment, as illustrated in FIG. 1, may be coupled to receive
data 102 from control circuitry 130. Control circuitry 130 may
comprise any suitable circuitry to control output of data 102 to
circuitry 140 in any suitable manner. Control circuitry 130 for one
embodiment may store data 102 in one or more registers.
[0023] Control circuitry 130 for one embodiment may output data 102
to circuitry 140 as control circuitry 130 outputs address 101 to
circuitry 110. Control circuitry 130 for one embodiment may output
address 101 and data 102 so as to be available on the same clock
edge. Control circuitry 130 for one embodiment may include
programmable logic to output address 101 and/or data 102. Control
circuitry 130 for one embodiment may output address 101 and/or data
102 in response to an instruction in order to execute the
instruction.
[0024] Encoded Data Output Circuitry
[0025] Circuitry 110 may include any suitable circuitry to output
encoded data 111 from an addressable location in any suitable
manner.
[0026] Circuitry 110 for one embodiment, as illustrated in FIG. 3,
may include a memory 322 to store encoded data corresponding to
different numbers. Memory 322 may store any suitable amount of
encoded data for any suitable numbers of any suitable bit-length.
Memory 322 for one embodiment may be preloaded with encoded data
corresponding to different numbers. Memory 322 for one embodiment
may be loaded with encoded data corresponding to a number when that
number is first used for product generation. Circuitry 110 for one
embodiment may read encoded data from an addressable location in
memory 322 based on address 101 and output such read encoded data
to circuitry 140.
[0027] Memory 322 may be implemented using any suitable circuitry
to store any suitable capacity of encoded data. Memory 322 may
include circuitry for volatile memory and/or circuitry for
non-volatile memory. Memory 322 may include, by way of example and
not limitation, circuitry for a set of a plurality of registers,
circuitry for any suitable read-only memory (ROM), circuitry for
any suitable random access memory (RAM) such as a suitable static
RAM or a suitable dynamic RAM for example, and/or circuitry for any
suitable flash memory.
[0028] Circuitry 110 for one embodiment, as illustrated in FIG. 3,
may include an address decoder 324 coupled to receive and decode at
least a portion of a received address to read encoded data from
memory 322. Circuitry 110 for another embodiment may not include
address decoder 324 but rather may address memory 322 directly
using a received address.
[0029] Circuitry 110 for one embodiment, as illustrated in FIG. 3,
may include buffer circuitry 326 to output encoded data to
circuitry 140. Buffer circuitry 326 may include any suitable
circuitry coupled to receive encoded data from memory 322 and to
store and/or output encoded data in any suitable manner. Buffer
circuitry 326 for one embodiment may successively output portions
of encoded data corresponding to a first number to circuitry 140.
Buffer circuitry 326 for one embodiment may output all encoded data
corresponding to a first number at once to circuitry 140.
[0030] Product Generation Circuitry
[0031] Circuitry 140 may include any suitable circuitry to generate
product 103 of any suitable bit- length in any suitable manner
based at least in part on encoded data 111 of any suitable
bit-length and on data 102 of any suitable bit-length.
[0032] Circuitry 140 for one embodiment, as illustrated in FIG. 4,
may include partial product generation circuitry 452 and selection
circuitry 454.
[0033] Partial product generation circuitry 452 for one embodiment
may generate data corresponding to different potential partial
products for data 102 corresponding to the second number. Partial
product generation circuitry 452 may include any suitable circuitry
to generate any suitable data of any suitable bit-length in any
suitable manner for data 102 of any suitable bit-length. Partial
product generation circuitry 452 for one embodiment may generate
data corresponding to potential partial products with sign
extension.
[0034] Partial product generation circuitry 452 for one embodiment
may generate data corresponding to one or more potential partial
products based at least in part on data 102. Partial product
generation circuitry 452 for one embodiment may be coupled to
receive data 102. Partial product generation circuitry 452 for one
embodiment may generate data corresponding to potential partial
products in accordance with Booth (or modified Booth) encoding.
[0035] Partial product generation circuitry 452 for one embodiment
may generate, for example, data corresponding to all logical zeros,
data corresponding to all logical ones, data corresponding to the
second number, data corresponding to two times the second number,
data corresponding to the two's complement of the second number,
and/or data corresponding to the two's complement of the product of
two times the second number. Partial product generation circuitry
452 for one embodiment may generate, for example, 17-bit potential
partial products in accordance with Booth (or modified Booth)
encoding with sign extension for a 16-bit second number, for
example.
[0036] Selection circuitry 454 for one embodiment may be coupled to
select a potential partial product from partial product generation
circuitry 452. Selection circuitry 454 for one embodiment may
select a potential partial product based at least in part on
encoded data 111 output from circuitry 110. Selection circuitry 454
for one embodiment may select a potential partial product based on
a set of select bits of encoded data 111 output from circuitry 110.
Selection circuitry 454 for one embodiment, as illustrated in FIG.
4, may be coupled to receive encoded data 111 from circuitry 110.
Selection circuitry 454 may include any suitable circuitry to
select a potential partial product from partial product generation
circuitry 452 in any suitable manner. For one embodiment where
partial product generation circuitry 452 may generate and output a
plurality of potential partial products at one time, selection
circuitry 454 for one embodiment may select from such output
potential partial products. Selection circuitry 454 for one
embodiment may include suitable multiplexing circuitry.
[0037] Partial product generation circuitry 452 for one embodiment
may generate and output at one time six potential partial products
for data 102: data corresponding to all logical zeros, data
corresponding to all logical ones, data corresponding to the second
number, data corresponding to two times the second number, data
corresponding to the two's complement of the second number, and
data corresponding to the two's complement of the product of two
times the second number. Selection circuitry 454 for one embodiment
may select one such output potential partial product based on
encoded data 111. Encoded data 111 for one embodiment may include a
set of six select bits one of which is different from the others to
select one of six potential partial products. Encoded data 111 for
one embodiment may include a set of three select bits to select one
of six potential partial products.
[0038] Circuitry 140 for one embodiment, as illustrated in FIG. 4,
may include partial product reduction circuitry 456 and adder
458.
[0039] Partial product reduction circuitry 456 for one embodiment
may compress partial products. Partial product reduction circuitry
456 for one embodiment may be coupled to receive partial products
selected from selection circuitry 454. Partial product reduction
circuitry 456 may include any suitable circuitry to compress
partial products of any suitable bit-length in any suitable manner
to generate any suitable outputs of any suitable bit-length.
Partial product reduction circuitry 456 for one embodiment may
compress partial products to generate outputs in carry-save format.
For one embodiment where encoded data 111 for a first number
includes, for example, eight sets of select bits to select eight
partial products using selection circuitry 454, partial product
reduction circuitry 456 may compress eight partial products to
generate two outputs. Partial product reduction circuitry 456 for
one embodiment may compress, for example, eight 17-bit partial
products to generate, for example, two 32-bit outputs.
[0040] Adder 458 for one embodiment may add outputs from partial
product reduction circuitry 456 to generate product 103. Adder 458
for one embodiment may be coupled to receive outputs from partial
product reduction circuitry 456. Adder 458 may include any suitable
circuitry to add outputs of any suitable bit-length in any suitable
manner to generate product 103 in any suitable form of any suitable
bit-length. Adder 458 for one embodiment may be a carry propagate
adder. Adder 458 for one embodiment may add outputs to generate
product 103 in two's complement form. Adder 458 for one embodiment
may add, for example, 32-bit outputs from partial product reduction
circuitry 456 to generate, for example, a 32-bit product 103.
[0041] Data Encoding Circuitry
[0042] Circuitry 110 for one embodiment may include encoding
circuitry to encode data corresponding to a first number and to
store encoded data at an addressable location for future use.
Circuitry 110 for one embodiment may include any suitable encoding
circuitry to encode data in any suitable manner.
[0043] Circuitry 110 may be coupled to receive data corresponding
to a first number from any suitable source. Such data may have any
suitable bit-length. Circuitry 110 for one embodiment, as
illustrated in FIG. 5, may be coupled to receive data 501
corresponding to a first number from control circuitry 130. Control
circuitry 130 may comprise any suitable circuitry to control output
of data 501 to circuitry 110 in any suitable manner. Control
circuitry 130 for one embodiment may store data 501 in one or more
registers.
[0044] Control circuitry 130 for one embodiment may also output to
circuitry 110 an address 101 to address a location at which encoded
data corresponding to a first number may be stored. Control
circuitry 130 for one embodiment may output address 101 and data
501 so as to be available on the same clock edge. Control circuitry
130 for one embodiment may include programmable logic to output
address 101 and/or data 501. Control circuitry 130 for one
embodiment may output address 101 and/or data 501 in response to an
instruction in order to execute the instruction.
[0045] Circuitry 110 for one embodiment, as illustrated in FIG. 5,
may include encoding circuitry 560 coupled to receive data 501 to
encode data 501. Encoding circuitry 560 may include any suitable
circuitry to encode data 501 in any suitable manner and to output
encoded data to an addressable location. Circuitry 110 for one
embodiment, as illustrated in FIG. 5, may include memory 522, and
encoding circuitry 560 may be coupled to output encoded data to
memory 522 to store encoded data in memory 522. Memory 522 for one
embodiment may generally correspond to memory 322 of FIG. 3.
[0046] Circuitry 110 for one embodiment, as illustrated in FIG. 5,
may include an address decoder 524 coupled to receive and decode at
least a portion of a received address to write encoded data to
memory 522 and/or to read encoded data from memory 522. Circuitry
110 for another embodiment may not include address decoder 524 but
rather may address memory 522 directly using a received
address.
[0047] Circuitry 110 for one embodiment, as illustrated in FIG. 5,
may include buffer circuitry 526 to output encoded data to
circuitry 140. Buffer circuitry 526 may include any suitable
circuitry coupled to receive encoded data from memory 522 and to
store and/or output encoded data in any suitable manner. Buffer
circuitry 526 for one embodiment may also include any suitable
circuitry coupled to receive encoded data from encoding circuitry
560. Buffer circuitry 526 for one embodiment may successively
output portions of encoded data corresponding to a first number to
circuitry 140. Buffer circuitry 526 for one embodiment may output
all encoded data corresponding to a first number at once to
circuitry 140.
[0048] Control circuitry 130 for one embodiment may output both an
address 101 and data 501 corresponding to a first number for which
encoded data is not already stored at an addressable location for
output to circuitry 140. Control circuitry 130 for one embodiment
may then control circuitry 110 to encode data 501 and store
resulting encoded data at a location corresponding to address 101.
For subsequent uses of that same first number, control circuitry
130 for one embodiment may output address 101 corresponding to that
first number and control circuitry 110 to output the already
encoded data from the location corresponding to address 101. In
this manner, circuitry 110 for one embodiment may be used to help
reduce or avoid having to encode the same data repeatedly for
partial product reduction. Control circuitry 130 may include any
suitable circuitry to track whether or not encoded data
corresponding to a first number is already stored at an addressable
location for output to circuitry 140.
[0049] FIG. 6 illustrates, for one embodiment, a flow diagram 600
to output encoded data.
[0050] If, for block 602, control circuitry 130 identifies encoded
data corresponding to a first number is not already stored at an
addressable location for output to circuitry 140, control circuitry
130 for block 604 may output both an address and data corresponding
to the first number and for block 606 may control circuitry 110 to
encode such data and store resulting encoded data at a location
corresponding to the address. Circuitry 110 for block 608 may
output resulting encoded data either directly to circuitry 140 or
from the addressable location to circuitry 140.
[0051] If, for block 602, control circuitry 130 identifies encoded
data corresponding to a first number is already stored at an
addressable location for output to circuitry 140, control circuitry
130 for block 610 may output an address corresponding to the first
number and for block 612 control circuitry 110 to output to
circuitry 140 the already encoded data from the location
corresponding to the address.
[0052] Encoding circuitry 560 for one embodiment may include any
suitable circuitry to encode data 501 of any suitable bit-length
for partial product reduction in any suitable manner to generate
and output encoded data of any suitable size. Data 501 for one
embodiment may be 16 bits in length. Encoding circuitry 560 for one
embodiment may include any suitable circuitry to encode data 501 of
any suitable bit-length to generate and output encoded data that
includes any suitable number of sets of any suitable number of
select bits.
[0053] Encoding circuitry 560 for one embodiment, as illustrated in
FIG. 7, may include circuitry 762 coupled to receive data 501 of
any suitable bit-length to encode data 501 using Booth encoding or
modified Booth encoding, such as radix-4 Booth (or modified Booth)
encoding for example, to generate and output encoded data of any
suitable size. Circuitry 762 for one embodiment may use radix-4
Booth (or modified Booth) encoding to encode data 501 that is
16-bits in length to generate encoded data that is 48 bits in
length, that is eight sets of six select bits.
[0054] Encoding circuitry 560 for one embodiment, as illustrated in
FIG. 7, may optionally include circuitry 764 coupled to receive
encoded data of any suitable size from circuitry 762 to further
encode such encoded data in any suitable manner to generate and
output encoded data of any suitable size. Circuitry 764 for one
embodiment may include any suitable circuitry to help compress
encoded data. Circuitry 764 for one embodiment may encode already
encoded data using leading zeroes detection (LZD) or modified LZD.
Circuitry 764 for one embodiment may use LZD or modified LZD to
encode encoded data having eight sets of six select bits where each
set has only one bit that is different from the other bits in the
set, such as only one logic one bit in the set for example, to
generate eight sets of three encoded select bits for a total of 24
bits of encoded data.
[0055] Circuitry 764 for one embodiment may include circuitry 864
as illustrated in FIG. 8 to perform modified LZD to encode a set of
six select bits having only one logic one bit to generate a set of
three encoded select bits. As illustrated in FIG. 8, circuitry 864
may include any suitable circuitry to implement functionality of OR
gates 866, 867, and 868. OR gate 866 has as inputs the least
significant, third-least significant, and second-most significant
bits of a set of six select bits to output a least significant bit
of a set of three encoded select bits. OR gate 867 has as inputs
the third-least significant and third-most significant bits of the
set of six select bits to output a second-least significant bit of
the set of three encoded select bits. OR gate 868 has as inputs the
least significant and second-least significant bits of the set of
six select bits to output a most significant bit of the set of
three encoded select bits.
[0056] Encoding circuitry 560 for one embodiment may optionally not
include or use circuitry 764 but rather may output encoded data
directly from circuitry 762.
[0057] Circuitry 110 for one embodiment may be designed to output
already encoded data corresponding to a first number from an
addressable location faster relative to encoding data corresponding
to that same first number. Circuitry 110 for one embodiment may
then be used to help speed performance of product generation.
[0058] Circuitry 110 for one embodiment may be designed to output
already encoded data corresponding to a first number from an
addressable location with less power consumption and/or heat
dissipation relative to encoding data corresponding to that same
first number. Circuitry 110 for one embodiment may then be used to
help reduce power consumption and/or heat dissipation.
[0059] Example System
[0060] Circuitry 100 of FIG. 1 may be used to generate a product
based at least in part on encoded data from an addressable location
in any suitable environment and for any suitable purpose.
[0061] FIG. 9 illustrates an example system 900 comprising a
processor 910 having one or more multiplier circuits 912 having
circuitry 100 to generate a product based at least in part on
encoded data from an addressable location. Processor 910 for one
embodiment may use one or more multiplier circuits 912, for
example, to help perform digital signal processing (DSP)
applications such as, for example, finite impulse response (FIR)
filters, infinite impulse response (IIR) filters, discrete cosine
transforms (DCTs), and/or fast Fourier transforms (FFTs).
[0062] System 900 for another embodiment may include multiple
processors one or more of which may similarly have one or more
multiplier circuits.
[0063] Processor 910 for one embodiment may be coupled to receive
power from one or more power supplies 902. Power supply(ies) 902
for one embodiment may include one or more energy cells, such as a
battery and/or a fuel cell for example. Power supply(ies) 902 for
one embodiment may include an alternating current to direct current
(AC-DC) converter. Power supply(ies) 902 for one embodiment may
include a DC-DC converter.
[0064] System 900 for one embodiment may also include a chipset 920
coupled to processor 910, a basic input/output system (BIOS) memory
930 coupled to chipset 920, volatile memory 940 coupled to chipset
920, non-volatile memory and/or storage device(s) 950 coupled to
chipset 920, one or more input devices 960 coupled to chipset 920,
a display 970 coupled to chipset 920, one or more communications
interfaces 980 coupled to chipset 920, and/or one or more other
input/output (I/O) devices 990 coupled to chipset 920.
[0065] Chipset 920 for one embodiment may include any suitable
interface controllers to provide for any suitable communications
link to processor 910 and/or to any suitable device or component in
communication with chipset 920.
[0066] Chipset 920 for one embodiment may include a firmware
controller to provide an interface to BIOS memory 930. BIOS memory
930 may be used to store any suitable system and/or video BIOS
software for system 900. BIOS memory 930 may include any suitable
non-volatile memory, such as a suitable flash memory for example.
BIOS memory 930 for one embodiment may alternatively be included in
chipset 920.
[0067] Chipset 920 for one embodiment may include one or more
memory controllers to provide an interface to volatile memory 940.
Volatile memory 940 may be used to load and store data and/or
instructions, for example, for system 900. Volatile memory 940 may
include any suitable volatile memory, such as suitable dynamic
random access memory (DRAM) for example.
[0068] Chipset 920 for one embodiment may include a graphics
controller to provide an interface to display 970. Display 970 may
include any suitable display, such as a cathode ray tube (CRT) or a
liquid crystal display (LCD) for example. The graphics controller
for one embodiment may alternatively be external to chipset
920.
[0069] Chipset 920 for one embodiment may include one or more
input/output (I/O) controllers to provide an interface to
non-volatile memory and/or storage device(s) 950, input device(s)
960, communications interface(s) 980, and/or I/O devices 990.
[0070] Non-volatile memory and/or storage device(s) 950 may be used
to store data and/or instructions, for example. Non-volatile memory
and/or storage device(s) 950 may include any suitable non-volatile
memory, such as flash memory for example, and/or may include any
suitable non-volatile storage device(s), such as one or more hard
disk drives (HDDs), one or more compact disc (CD) drives, and/or
one or more digital versatile disc (DVD) drives for example.
[0071] Input device(s) 960 may include any suitable input
device(s), such as a keyboard, a mouse, and/or any other suitable
cursor control device.
[0072] Communications interface(s) 980 may provide an interface for
system 900 to communicate over one or more networks and/or with any
other suitable device. Communications interface(s) 980 may include
any suitable hardware and/or firmware. Communications interface(s)
980 for one embodiment may include, for example, a network adapter,
a wireless network adapter, a telephone modem, and/or a wireless
modem. For wireless communications, communications interface(s) 980
for one embodiment may use one or more antennas 982.
[0073] I/O device(s) 990 may include any suitable I/O device(s)
such as, for example, an audio device to help convert sound into
corresponding digital signals and/or to help convert digital
signals into corresponding sound, a camera, a camcorder, a printer,
and/or a scanner.
[0074] Although described as residing in chipset 920, one or more
controllers of chipset 920 may be integrated with processor 910,
allowing processor 910 to communicate with one or more devices or
components directly. As one example, one or more memory controllers
for one embodiment may be integrated with processor 910, allowing
processor 910 to communicate with volatile memory 940 directly.
[0075] In the foregoing description, example embodiments have been
described. Various modifications and changes may be made to such
embodiments without departing from the scope of the appended
claims. The description and drawings are, accordingly, to be
regarded in an illustrative rather than a restrictive sense.
* * * * *