U.S. patent application number 11/941718 was filed with the patent office on 2008-03-20 for modularized die stacking system and method.
This patent application is currently assigned to Staktek Group L.P.. Invention is credited to Phill Bradley, Jeff Buchle, James G. Cady, Curtis Hart, David L. Roper, James Douglas JR. Wehrly, James Wilder.
Application Number | 20080067662 11/941718 |
Document ID | / |
Family ID | 39187728 |
Filed Date | 2008-03-20 |
United States Patent
Application |
20080067662 |
Kind Code |
A1 |
Roper; David L. ; et
al. |
March 20, 2008 |
Modularized Die Stacking System and Method
Abstract
An IC die and a flexible circuit structure are integrated into a
lower stack element that can be stacked with either further
integrated lower stack element iterations or with pre-packaged ICs
in any of a variety of package types. A die is positioned above the
surface of portions of a pair of flex circuits. Connection is made
between the die and the flex circuitry. A protective layer is
formed to protect the flex-connected die and its connection to the
flex. Connective elements are placed along the flex circuitry to
create an array of module contacts along the second side of the
flex circuitry. The flex circuitry is positioned above the
body-protected die to create an integrated lower stack element. The
integrated lower stack element may be stacked either with
iterations of the integrated lower stack element or with a
pre-packaged IC to create a multi-element stacked circuit
module.
Inventors: |
Roper; David L.; (Austin,
TX) ; Hart; Curtis; (Round Rock, TX) ; Wilder;
James; (Austin, TX) ; Bradley; Phill;
(Pflugerville, TX) ; Cady; James G.; (Austin,
TX) ; Buchle; Jeff; (Austin, TX) ; Wehrly;
James Douglas JR.; (Austin, TX) |
Correspondence
Address: |
FISH & RICHARDSON P.C.
P.O BOX 1022
Minneapolis
MN
55440-1022
US
|
Assignee: |
Staktek Group L.P.
|
Family ID: |
39187728 |
Appl. No.: |
11/941718 |
Filed: |
November 16, 2007 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10435192 |
May 9, 2003 |
|
|
|
11941718 |
Nov 16, 2007 |
|
|
|
10005581 |
Oct 26, 2001 |
6576992 |
|
|
10435192 |
May 9, 2003 |
|
|
|
Current U.S.
Class: |
257/686 ;
174/254; 257/690; 257/E21.505; 257/E23.006; 257/E23.065;
257/E23.069; 257/E25.023; 438/109 |
Current CPC
Class: |
H05K 2201/056 20130101;
H01L 23/4985 20130101; H01L 2224/48227 20130101; H01L 2924/19107
20130101; H01L 2924/00014 20130101; H01L 2924/14 20130101; H01L
2924/00014 20130101; H01L 23/3128 20130101; H01L 2924/3011
20130101; H01L 2224/48228 20130101; H01L 2225/1058 20130101; H01L
2924/00014 20130101; H01L 23/5387 20130101; H01L 2224/05599
20130101; H01L 2224/16225 20130101; H01L 2924/181 20130101; H01L
2224/85399 20130101; H01L 2924/181 20130101; H05K 1/141 20130101;
H05K 2201/10734 20130101; H01L 2224/16237 20130101; H05K 1/147
20130101; H05K 1/189 20130101; H01L 2924/14 20130101; H01L
2924/01322 20130101; H01L 2224/32225 20130101; H01L 23/3114
20130101; H01L 23/49827 20130101; H01L 25/105 20130101; H05K 3/363
20130101; H05K 2201/10689 20130101; H01L 2224/73215 20130101; H01L
2224/45099 20130101; H01L 2224/4824 20130101; H01L 2924/00014
20130101; H01L 2224/4824 20130101; H01L 2224/73215 20130101; H01L
2924/00014 20130101; H01L 2924/00012 20130101; H01L 2224/32225
20130101; H01L 2924/207 20130101; H01L 2924/00 20130101; H01L
2224/45015 20130101; H01L 2224/32225 20130101; H01L 2924/00
20130101; H01L 2924/00 20130101; H01L 23/49816 20130101; H01L
2224/73215 20130101; H01L 2924/15311 20130101; H01L 2924/19041
20130101; H01L 2224/4824 20130101; H01L 2224/85399 20130101; H01L
2924/15311 20130101; H01L 24/48 20130101; H01L 2224/05599 20130101;
H01L 2224/45099 20130101 |
Class at
Publication: |
257/686 ;
174/254; 257/690; 438/109; 257/E21.505; 257/E23.006 |
International
Class: |
H01L 23/14 20060101
H01L023/14; H01L 21/58 20060101 H01L021/58; H05K 1/00 20060101
H05K001/00 |
Claims
1. A circuit module comprising: an upper IC element; an integrated
lower stack element comprising: an integrated circuit die; first
and second flex circuits, disposed adjacent to and connected with
the integrated circuit die to create a die-flex combination; and a
protective structure molded to the die-flex combination to create a
body having an upper surface above which are placed portions of the
first and second flex circuits; and the upper IC element and the
integrated lower stack element being in stacked conjunction with
the upper IC element being disposed above the integrated lower
stack element and the upper IC element and integrated lower stack
element being connected through the first and second flex
circuits.
2. The circuit module of claim 1 in which the first and second flex
circuits each have first and second conductive layers.
3. The circuit module of claim 2 in which the connection of the
upper IC element and integrated lower stack element through the
first and second flex circuits is implemented through
interconnections articulated at the first and second conductive
layers of the first and second flex circuits.
4. The circuit module of claim 2 in which at least one of the first
and second conductive layers of the first and second flex circuits
have demarked upper and lower flex contacts.
5. An integrated lower stack element comprising: an integrated
circuit die; first and second flex circuits, disposed adjacent to
and connected with the integrated circuit die to create a die-flex
combination; and a protective structure molded to the die-flex
combination to create a body having an upper surface above which
are placed portions of the first and second flex circuits.
6. The integrated lower stack element of claim 5 in which the first
and second flex circuits are connected with the integrated circuit
die through wire bonds.
7. The integrated lower stack element of claim 5 in which the first
and second flex circuits are connected with the integrated circuit
die through flip-chip connections.
8. The integrated lower stack element of claim 5 further comprising
a set of module contacts disposed along the first and second flex
circuits.
9. The integrated lower stack element of claim 5 in which the first
and second flex circuits each have first and second conductive
layers.
10. A circuit module comprising: (a) an integrated lower stack
element comprising; an integrated circuit die having a plurality of
die connective sites; a flexible circuit having first and second
conductive layers, the flexible circuit being disposed in part
beneath and affixed to and connected with the integrated circuit
die to form a die-flex combination; and a protective structure set
about the die-flex combination to cover at least a portion of the
die and at least a portion of the flexible circuit and create a
body having an upper surface above which are placed portions of the
flexible circuit; and (b) an upper IC element having a plurality of
upper IC contacts, the upper IC element being disposed in stacked
conjunction with the integrated lower stack element, the upper IC
element and integrated lower stack element being connected through
the flexible circuit.
11. The circuit module of claim 10 in which a data signal
connection between the upper IC element and the integrated lower
stack element is implemented at the second conductive layer of the
flex circuit.
12. The circuit module of claim 10 in which a data signal
connection between the upper IC element and the integrated lower
stack element is implemented at the first conductive layer of the
flex circuit.
13. The circuit module of claim 10 in which: a data set of the
plurality of upper IC contacts expresses an n-bit datapath; a data
set of the plurality of die connective sites expresses an n-bit
datapath; and a set of module contacts expresses a 2n-bit datapath
that combines the n-bit datapath of the data set of the plurality
of upper IC contacts and the n-bit datapath of the data set of the
plurality of die connective sites.
14. The circuit module of claim 10 in which the second conductive
layer comprises at least one demarked voltage plane and a voltage
set of upper flex contacts and a voltage set of lower flex contacts
that connect voltage conductive die connective sites and voltage
conductive upper IC contacts to one of the at least one voltage
planes.
15. A flex circuit connecting an upper IC element and an integrated
circuit die in a circuit module, the flex circuit comprising: first
and second outer layers; and first and second conductive layers,
between which there is an intermediate layer, the first and second
conductive layers and the intermediate layer being interior to the
first and second outer layers, the second conductive layer having
demarked first and second flex contacts, the first flex contacts
being accessible through first windows through the second outer
layer and the second flex contacts being accessible through second
windows through the first outer layer, the first conductive layer,
and the intermediate layer, the first flex contacts in electrical
connection with the upper IC element and the second flex contacts
in electrical connection with the integrated circuit die; wherein
the flex circuit is disposed in part beneath and is combined with
the integrated circuit die to form a die-flex combination and
wherein a protective structure is set about the die-flex
combination to cover at least a portion of the die and at least a
portion of the flex circuit, the protective structure having an
upper surface above which are placed portions of the flex
circuit.
16. The flex circuit of claim 15 in which the second flex contacts
are accessible through module windows through the second outer
layer.
17. The flex circuit of claim 15 in which the first and second
conductive layers are metal.
18. The flex circuit of claim 15 in which selected ones of the
first flex contacts are connected to selected ones of the second
flex contacts.
19. The flex circuit of claim 15 in which selected ones of the
first flex contacts and selected ones of the second flex contacts
are connected to the first conductive layer.
20. The flex circuit of claim 17 in which the metal of the first
and second conductive layers is alloy 110.
21. The flex circuit of claim 18 in which the connected selected
ones of the first and second flex contacts are connected with
traces.
22. The flex circuit of claim 15 in which selected ones of the
first flex contacts and selected ones of the second flex contacts
are connected to the first conductive layer with vias.
23. A circuit module that employs the flex circuit of claim 15 to
connect selected die contacts of an integrated circuit die to
selected contacts of an upper IC element.
24. A circuit module comprising: a first flex circuit devised in
accordance with claim 15; a second flex circuit devised in
accordance with claim 15; an integrated circuit die having a
plurality of die connective sites, a set of the plurality of die
connective sites of the integrated circuit die being in electrical
communication with the first flex contacts of each of the first and
second flex circuits; an upper IC element having a plurality of
upper IC contacts, a set of the plurality of upper IC contacts of
the upper IC element being in electrical communication with the
second flex contacts of each of the first and second flex circuits;
and a set of module contacts in electrical communication with the
second flex contacts.
25. The circuit module of claim 24 in which the first and second
flex circuits are connected through an inter-flex circuit
connective.
26. A circuit module comprising: a first flex circuit devised in
accordance with claim 15; a second flex circuit devised in
accordance with claim 15; an integrated circuit having a plurality
of die connective sites, a set of the plurality of die connective
sites, the die contacts of the integrated being in electrical
communication with the second flex contacts of each of the first
and second flex circuits; an upper IC element having a plurality of
upper IC contacts, a set of the plurality of upper IC contacts of
the upper IC element being in electrical communication with the
first flex contacts of each of the first and second flex circuits;
and a set of module contacts in electrical communication with the
first flex contacts.
27. The circuit module of claims 24 or 26 in which for the first
and second flex circuits, the first conductive layer conveys
ground, and the second conductive layer conveys voltage in a
voltage plane and the intermediate layer is insulative to create a
distributed capacitor in the first and second flex circuits.
28. A circuit module comprising: a first CSP having first and
second lateral sides and upper and lower major surfaces and a set
of CSP contacts along the lower major surface; an integrated
circuit die having a set of die connective sites connected to a
pair of flex circuits; each of which pair of flex circuits having a
first conductive layer and a second conductive layer, both said
conductive layers being interior to first and second outer layers,
and demarcated at the second conductive layer of each flex circuit
there being upper and lower flex contacts, the upper flex contacts
being connected to the set of CSP contacts of the first CSP and the
lower flex contacts being connected to the die connective sites of
the integrated circuit die and a set of module contacts.
29. The circuit module of claim 28 in which: a chip-enable module
contact is connected to an enable lower flex contact that is
connected to a chip select CSP contact of the first CSP.
30. The circuit module of claim 29 in which the connection between
the enable lower flex contact and the chip select CSP contact of
the first CSP is through an enable connection at the first
conductive layer.
31. The circuit module of claim 28 in which a body having first and
second lateral sides and an upper major surface is set about the
integrated circuit die and a first one of the flex circuit pair is
partially wrapped about the first lateral side of said body and a
second one of the flex circuit pair is partially wrapped about the
second lateral side of said body to dispose the upper flex contacts
above the upper major surface of said body and beneath the lower
major surface of the first CSP.
32. The circuit module of claim 31 in which the first CSP expresses
an n-bit datapath and the integrated circuit die expresses an n-bit
datapath, each of the flex circuits of the flex circuit pair having
supplemental lower flex contacts which, in combination with the
lower flex contacts, provide connection for the set of module
contacts and a set of supplemental module contacts to express a
2n-bit module datapath that combines the n-bit datapath expressed
by the first CSP and the n-bit datapath expressed by the integrated
circuit die.
33. A circuit module comprising: a first CSP having first and
second major surfaces with a plurality of CSP contacts along the
first major surface; an integrated lower stack element in
accordance with claim 5, the first CSP being disposed above the
integrated lower stack element; each of the pair of flex circuits
of the integrated lower stack element having an outer layer and an
inner layer and first and second conductive layers between which
conductive layers there is an intermediate layer, the second
conductive layer having demarked a plurality of upper and lower
flex contacts and a voltage plane, a first set of said plurality of
upper and lower flex contacts being connected to the voltage plane,
a second set of said plurality of upper and lower flex contacts
being connected to the first conductive layer, and a third set of
said plurality of upper and lower flex contacts being comprised of
selected ones of upper flex contacts that are connected to
corresponding selected ones of lower flex contacts, the plurality
of CSP contacts of the first CSP being in contact with the upper
flex contacts; and a set of module contacts in contact with the
lower flex contacts.
34. The circuit module of claim 33 in which the first CSP and the
integrated circuit die of the integrated lower stack element are
memory circuits.
35. The circuit module of claim 33 in which the second set of said
plurality of upper and lower flex contacts is connected to the
first conductive layer with vias that pass through the intermediate
layer.
36. The circuit module of claim 35 in which the second set of said
plurality of upper and lower flex contacts is comprised of upper
flex contacts connected to the first conductive layer with on-pad
vias.
37. The circuit module of claim 35 in which the second set of said
plurality of upper and lower flex contacts is comprised of lower
flex contacts connected to the first conductive layer with off-pad
vias.
38. The circuit module of claim 1 mounted on a board.
39. The circuit module of claims 33 or 34 in which between the
first CSP and the integrated lower stack element there is a
thermally conductive layer.
40. A method for assembling a circuit module, the method comprising
the steps of: acquiring an integrated circuit die; acquiring a flex
circuit devised in accordance with claim 15; disposing an adhesive
on a selected area of the first outer surface of the flex circuit;
adhering the flex circuit to the integrated circuit die; forming a
connection between the flex circuit and the integrated circuit die;
protecting the integrated circuit die and the connection formed
between the flex circuit and the integrated circuit die with a
protective layer to form a body; disposing a portion of the flex
circuit above the body; acquiring a CSP; connecting the CSP to the
flex circuit.
Description
RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 10/435,192, filed May 9, 2003, which is a continuation-in-part
of U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001, now
U.S. Pat. No. 6,576,992, both of which are hereby incorporated by
reference for all purposes.
TECHNICAL FIELD
[0002] The present invention relates to aggregating integrated
circuits and, in particular, to stacking integrated circuits.
BACKGROUND OF THE INVENTION
[0003] A variety of techniques are used to stack integrated
circuits. Some methods require special packages, while other
techniques stack conventional packages and still others stack
multiple die within a single package. In some stacks, the leads of
the packaged integrated circuits are used to create a stack, while
in other systems, added structures such as rails provide all or
part of the interconnection between packages. In still other
techniques, flexible conductors with certain characteristics are
used to selectively interconnect packaged integrated circuits. In
yet other methods, one IC is connected to another within a single
plastic body from which leads or contacts emerge.
[0004] The predominant package configuration employed during the
past decade has encapsulated an integrated circuit (IC) in a
plastic surround typically having a rectangular configuration. The
enveloped integrated circuit is connected to the application
environment through leads emergent from the edge periphery of the
plastic encapsulation. Such "leaded packages" have been the
constituent elements most commonly employed by techniques for
stacking packaged integrated circuits.
[0005] Leaded packages play an important role in electronics, but
efforts to miniaturize electronic components and assemblies have
driven development of technologies that preserve circuit board
surface area. Because leaded packages have leads emergent from
peripheral sides of the package, leaded packages occupy more than a
minimal amount of circuit board surface area. Consequently,
alternatives to leaded packages have recently gained market
share.
[0006] One family of alternative packages is identified generally
by the term "chip scale packaging" or CSP. CSP refers generally to
packages that provide connection to an integrated circuit through a
set of contacts (often embodied as "bumps" or "balls") arrayed
across a major surface of the package. Instead of leads emergent
from a peripheral side of the package, contacts are placed on a
major surface and typically emerge from the planar bottom surface
of the package.
[0007] The goal of CSP is to occupy as little area as possible and,
preferably, approximately the area of the encapsulated IC.
Therefore, CSP leads or contacts do not typically extend beyond the
outline perimeter of the package. The absence of "leads" on package
sides renders most stacking techniques devised for leaded packages
inapplicable for CSP stacking.
[0008] CSP has enabled reductions in size and weight parameters for
many applications. For example, micro ball grid array for flash and
SRAM and wirebond on tape or rigid laminate CSPs for SRAM or EEPROM
have been employed in a variety of applications. CSP is a broad
category including a variety of packages from near chip scale to
die-sized packages such as the die sized ball grid array (DSBGA)
recently described in proposed JEDEC standard 95-1 for DSBGA. To
meet the continuing demands for cost and form factor reduction with
increasing memory capacities, CSP technologies that aggregate
integrated circuits in CSP technology have recently been developed.
For example, Sharp, Hitachi, Mitsubishi and Intel support what are
called the S-CSP specifications for flash and SRAM applications.
Those S-CSP specifications describe, however, stacking multiple die
within a single chip scale package and do not describe stacking
integrated circuits that are individually modularized in plastic,
either as BGA's or other common CSP packages. Stacking integrated
circuits within a single package requires specialized technology
that includes reformulation of package internals and significant
expense with possible supply chain vulnerabilities.
[0009] There are several known techniques for stacking packages
articulated in chip scale technology. For example, the assignee of
the present invention has developed previous systems for
aggregating micro-BGA packages in space saving topologies. The
assignee of the present invention has systems for stacking BGA
packages on a DIMM in a RAMBUS environment.
[0010] In U.S. Pat. No. 6,205,654 B1 owned by the assignee of the
present invention, a system for stacking ball grid array packages
that employs lead carriers to extend connectable points out from
the packages is described. Other known techniques add structures to
a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM
with angular placement of the packages. Such techniques provide
alternatives, but require topologies of added cost and
complexity.
[0011] U.S. Pat. No. 6,262,895 B1 to Forthun (the "Forthun patent")
purports to disclose a technique for stacking chip scale packaged
ICs. The Forthun patent discloses a "package" that exhibits a flex
circuit wrapped partially about a CSP. The flex circuit is said to
have pad arrays on upper and lower surfaces of the flex.
[0012] The flex circuit of the Forthun "package" has a pad array on
its upper surface and a pad array centrally located upon its lower
surface. On the lower surface of the flex there are third and
fourth arrays on opposite sides from the central lower surface pad
array. To create the package of Forthun, a CSP contacts the pad
array located on the upper surface of the flex circuit. As
described in the Forthun patent, the contacts on the lower surface
of the CSP are pushed through "slits" in the upper surface pads and
advanced through the flex to protrude from the pads of the lower
surface array and, therefore, the bottom surface of the package.
Thus, the contacts of the CSP serve as the contacts for the
package. The sides of the flex are partially wrapped about the CSP
to adjacently place the third and fourth pad arrays above the upper
major surface of the CSP to create from the combination of the
third and fourth pad arrays, a fifth pad array for connection to
another such package. Thus, as described in the Forthun disclosure,
a stacked module of CSPs created with the described packages will
exhibit a flex circuit wrapped about each CSP in the module.
[0013] The previous known methods for stacking CSPs apparently have
various deficiencies including complex structural arrangements and
thermal or high frequency performance issues. To increase
dissipation of heat generated by constituent CSPs, the thermal
gradient between the lower CSP and upper CSP in a CSP stack or
module should be minimized. Prior art solutions to CSP stacking do
not, however, address thermal gradient minimization in disclosed
constructions.
[0014] In other applications, module height concerns impact the
utility of known solutions in integrated circuit aggregation. In
some stacking solutions, the bad die problem is significant.
Indigenous as well as processing-acquired defects can lead to
unacceptably high failure rates for stacks created by aggregating
IC elements before testing the constituent members of the assembly.
For example, where stacking techniques employ one or more
unpackaged die, there is typically not an opportunity for adequate
preassembly test before the constituent ICs of the assembly are
aggregated. Then, testing typically reveals bad stacks, it does not
prevent their assembly and consequent waste of resources.
[0015] What is needed, therefore, is a technique and system for
stacking integrated circuits using a technology that provides a
thermally efficient, reliable structure that performs well at
higher frequencies, but does not add excessive height to the stack
yet allows pre-stacking test of constituent stack elements with
production at reasonable cost with readily understood and managed
materials and methods.
SUMMARY OF THE INVENTION
[0016] The present invention integrates an IC die and a flexible
circuit structure into an integrated lower stack element that can
be stacked with either further integrated lower stack element
iterations or with pre-packaged ICs in any of a variety of package
types. The present invention can be used to advantage where size
minimization, thermal efficiency and or test before stacking are
significant concerns. The present invention may be employed to
stack similar or dissimilar integrated circuits and may be used to
create modularized systems.
[0017] In the present invention, an IC die is integrated with flex
circuitry to create an integrated lower stack element. In a
preferred embodiment, a die is positioned above the surface of
portions of a pair of flex circuits. Connection is made between the
die and the flex circuitry. A protective layer such as a molded
plastic, for example, is formed to create a body that protects the
flex-connected die and its connection to the flex. Connective
elements are placed along the flex circuits to create an array of
module contacts along the second side of the flex circuitry.
Portions of the pair of flex circuits are positioned above the body
to create an integrated lower stack element. The integrated lower
stack element may be stacked either with further iterations of the
integrated lower stack element or with pre-packaged ICS to create a
multi-element stacked circuit module. The present invention may be
employed to advantage in numerous configurations and combinations
in modules provided for high-density memories or high capacity
computing.
SUMMARY OF THE DRAWINGS
[0018] FIG. 1 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present
invention.
[0019] FIG. 2 depicts an exemplar connection of an integrated
circuit die to one of two flex circuits in a preferred embodiment
of the present invention.
[0020] FIG. 3 depicts an elevation view of an integrated lower
stack element in accordance with a preferred embodiment of the
present invention.
[0021] FIG. 4 depicts an exemplar integration of a die in a
flip-chip configuration with flex circuitry in accordance with a
preferred embodiment of the present invention.
[0022] FIG. 5 depicts an exemplar construction details of an
integrated lower stack element in accordance with a preferred
embodiment of the present invention.
[0023] FIG. 6 depicts an exemplar construction details of an
integrated lower stack element in accordance with another preferred
embodiment of the present invention.
[0024] FIG. 7 depicts an exemplar conductive layer in a preferred
flex circuitry employed in a preferred embodiment of the present
invention.
DESCRIPTION OF PREFERRED EMBODIMENTS
[0025] FIG. 1 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present invention.
Module 10 is comprised of integrated lower stack element 12 and
upper IC element 14.
[0026] Upper IC element 14 that is depicted in FIG. 1 may be any of
a variety of types and configurations of CSP such as, for example,
those that are die-sized, as well those that are near chip-scale as
well as the variety of ball grid array packages known in the art.
Typical CSPs, such as, for example, ball-grid-array ("BGA"),
micro-ball-grid array (".mu.BGA"), and fine-pitch ball grid array
("FBGA") packages have an array of connective contacts embodied,
for example, as leads, bumps, solder balls, or balls that extend
from a lower surface of a plastic casing in any of several patterns
and pitches. An external portion of the connective contacts is
often finished with a ball of solder. Collectively, these will be
known herein as chip scale packaged integrated circuits (CSPs) and
preferred embodiments will be described in terms of CSPs, but the
particular configurations used in the explanatory figures are not,
however, to be construed as limiting. For example, in the elevation
view of FIG. 1, upper IC element 14 is depicted as a CSP of a
particular profile known to those in the art, but it should be
understood that the figures are exemplary only. Upper IC element 14
need not be limited to traditional CSP packaging and as those of
skill recognize the opportunity, the present invention is adaptable
to future package configurations. The present invention is
advantageously employed with memory circuits but may be employed to
advantage with logic and computing circuits even where the
constituent elements of module 10 are dissimilar. Upper IC element
14 is shown with upper IC contacts 19.
[0027] Integrated lower stack element 12 is shown with die 16 and
connections 20 that connect die 16 to flex circuits 18. Protective
surround 22 is disposed to protect connections 20 and die 16. In a
preferred embodiment, protective surround 22 is a plastic surround.
As a protective surround 22 is formed about die 16, a body 23 is
formed having lateral sides 21 and an upper surface 25. Protective
body 23 will, in a preferred embodiment, surround portions of die
16 that would otherwise be exposed to potential environmental
damage.
[0028] FIG. 2 depicts an exemplar connection of an integrated
circuit die 16 to one of two flex circuits 18 in a preferred
embodiment of the present invention to create a die-flex
combination. As the present description continues, those of skill
will recognize that a die-flex combination in accordance with the
present invention may be devised in a variety of particular manners
including using one or two flex circuits to provide connection to
die 16, as well as using flex circuitry having one or more
conductive layers. Preferably, the flex circuitry will articulate
connective structures such as flex contacts and traces that will
later be described.
[0029] As shown in FIG. 2, die pads 24 on die 16 are connected to
flex attachments 26 of flex 18 by connections 20 which, in the
illustrated exemplar, are wire bonding connections. Die pads 24 are
just one type of die connective site that may be employed in the
present invention. Other die connective sites such as flip-chip,
tab and connective rings, balls, or pads may be employed. Die
connective sites may also be construed to include combinations of
such structures to provide a connective site for the die. Wire
bonding is well known in the art and those of skill will appreciate
that many other methods may be used to provide connections 20
between die 16 and the flex circuitry employed for the invention.
For example, tab or flip-chip or other attachment techniques known
in the art can be profitably used to implement connections 20.
Those of skill will also appreciate that die pads 24 of die 16 can
be arranged in a variety of configurations across the IC. As is
known in the art, through die pads 24, die 16 expresses data and
instructions as well as ground and voltage connections.
[0030] Flex 18 may be configured to interconnect to die 16 with
other connective configurations. For example, as a variant on the
flip-chip connectivity scheme, flex attachments 26 may be placed on
the side of flex circuits 18 opposite that shown in FIG. 2 to place
the flex attachments 26 immediately adjacent to the surface of die
16 to provide direct connection between die 16 and flex circuitry
18. It should also be understood that in the preferred embodiment
shown in FIG. 1, two flex circuits 18 are employed but
implementations of the invention can be devised using one flex
circuit 18.
[0031] FIG. 3 depicts an elevation view of an integrated lower
stack element 12 before its assembly into a module 10. Die 16 is
placed adjacent to flex circuits 18 and fixed in place with
adhesive 28. A variety of adhesive methods are known in the art
and, in a preferred embodiment, an adhesive is used that has
thermally conductive properties.
[0032] With reference to FIG. 4, in a preferred embodiment,
portions of flex circuits 18A and 18B are fixed to die 16 by
adhesive 28 which may be a liquid or tape adhesive or may be placed
in discrete locations across the package. When used, preferably,
adhesive 28 is thermally conductive. Adhesives that include a flux
are used to advantage in some steps of assembly of module 10. Layer
28 may also be a thermally conductive medium or body to encourage
heat flow.
[0033] As shown in this preferred embodiment, module contacts 30
are fixed along flex circuits 18A and 18B opposite the side of the
flex circuits nearest to which die 16 is adjacent. The shown
preferred module contacts 30 are familiar to those in the art and
may be comprised of eutectic, lead-free, solid copper, or other
conductive materials. Other contact implementing structures may be
used to create module contacts 30 as long as the conductive layer
or layers of the flex circuitry can be connected to module contacts
30 to allow conveyance of the signals conducted in flex circuits 18
to be transmitted to an environment external to integrated lower
stack element 12. Balls are well understood, but other techniques
and structures such as connective rings, built-up pads, or even
leads may be placed along flex circuits 18 to create module
contacts 30 to convey signals from module 10 to an external
environment. Any of the standard JEDEC patterns may be implemented
with module contacts 30 as well as custom arrays of module contacts
for specialized applications.
[0034] FIG. 4 depicts the integration of die 16 devised in a
flip-chip configuration with two flex circuits 18A and 18B in
accordance with a preferred embodiment of the present invention.
Those of skill will understand that the depiction of FIG. 4 is not
drawn to scale. Die 16 exhibits die pads 24 along a lower surface
of the die. Attached to die pads 24 are die connectors 32 which, in
the depicted embodiment, are flip-chip balls or connectors. As
shown, flex circuits 18A and 18B have module contacts 30.
[0035] Any flexible or conformable substrate with a conductive
pattern may be used as a flex circuit in the invention. The
preferred flex circuitry will employ more than one conductive
layer, but the invention may be implemented with flex circuitry
that has only a single conductive layer.
[0036] Even though single conductive layer flex circuitry may
readily be used in the invention, flex circuit 18 is preferably a
multi-layer flexible circuit structure that has at least two
conductive layers. This is particularly appropriate where
frequencies to be encountered are higher. Preferably, the
conductive layers are metal such as copper alloy 110 although any
conductive material may be employed in this role. The use of plural
conductive layers provides advantages such as the creation of a
distributed capacitance across module 10 intended to reduce noise
or bounce effects that can, particularly at higher frequencies,
degrade signal integrity, as those of skill in the art will
recognize.
[0037] The entire flex circuit may be flexible or, as those of
skill in the art will recognize, a PCB structure made flexible in
certain areas to allow conformability around body 23 and rigid in
other areas for planarity along surfaces may be employed as an
alternative flex circuitry in the present invention. For example,
structures known as rigid-flex may be employed.
[0038] Flex circuits 18A and 18B shown in FIG. 4 are comprised of
multiple layers. Depicted flex circuits 18A and 18B have a first
outer surface 36 and a second outer surface 38. The depicted
preferred flex circuits 18A and 18B have two conductive layers
interior to first and second outer surfaces 36 and 38. In the
depicted preferred embodiment, first conductive layer 40 and second
conductive layer 42 are interior to first and second outer surfaces
36 and 38, respectively. Intermediate support layer 44 lies between
first conductive layer 40 and second conductive layer 42. There may
be more than one intermediate layer, but an intermediate layer of
polyimide is preferred. Preferably, the intermediate layer provides
mechanical support for the flex circuitry.
[0039] It should be understood that in some embodiments of the
invention, there will be fewer layers employed in flex circuit 18.
For example, a flex circuit 18 may be devised for use in the
present invention that lacks first outer surface 36 and/or second
outer surface 38. In such a case, first conductive layer 40 will be
on the surface of the particular flex circuit 18. Where there is a
first outer surface, to make contact with first conductive layer 40
as shown in FIG. 4, die connectors 32 pass through windows 46 to
reach first conductive layer 40. Similarly, where there is a second
outer surface 38, module contacts 30 pass through windows 48 in
second outer surface 38 to reach second conductive layer 42.
[0040] In a preferred embodiment, first conductive layer 40 is
employed as a ground plane, while second conductive layer 42
provides the functions of being a signal conduction layer and a
voltage conduction layer. Thus, second conductive layer 42 is
employed to implement signal connections between integrated lower
stack element 12 and upper IC element 14, while first conductive
layer 40 is employed to implement ground connections between
integrated lower stack element 12 and upper IC element 14. Those of
skill will note that roles of the first and second conductive
layers may be reversed. This may be implemented by flex layer
design or by attendant use of interconnections. As is understood,
thermal management is typically related to conductive layer
materials and mass as well as the proximity between the die and the
conductive layer.
[0041] Selective connections between first and second conductive
layers 40 and 42 may be implemented with vias such as the via
indicated in FIG. 4 by reference 50. There are, however, many other
alternative methods to provide any needed connections between the
conductive layers. For example, appropriate connections may be
implemented by any of several well-known techniques such as plated
holes or solid lines or wires. Thus, the connections need not
literally be implemented with vias.
[0042] As will be illustrated in later figures, traces are
delineated in conductive layers to convey, where needed, signals
between selected module contacts 30 and particular die connectors
32 in the case of flip-chip style die 16 or between module contacts
30 and flex connectors 26 in the case where wire-bond connections
20 are implemented or between upper and lower flex contacts as will
be described herein. Those of skill will recognize that traces can
be implemented in a variety of configurations and manners and where
die connectors are positioned coincident with module contact
placement, trace use is minimized. For example, in some cases, if
the die connectors 32 (illustrated as flip-chip connectors) are
placed appropriately on die 16, a via 50 may be used to directly
connect a selected die connector 32 to a selected module contact 30
without intermediate lateral conveyance between the two through a
trace. Where a single conductive layer flex circuitry is employed
in an embodiment, there will be no need for a via if a die
connector 32 is positioned coincident with a module contact 30 to
implement connection through a lower flex contact 62 such as is
depicted in FIG. 5.
[0043] FIG. 5 illustrates an exemplar construction of an integrated
lower stack element 12 in accordance with an alternative preferred
embodiment of the present invention that employs flex circuitry
having a single conductive layer. As shown, die 16 is appended to
flex circuits 18A and 18B with adhesive 28. The depicted embodiment
also exhibits optional inter-flex connective 51 that passes through
the part of protective surround 22 that lies between flex circuit
18A and flex circuit 18B. The inter-flex connective may consist of
one or more wires or other connective structures such as may be
implemented in wire bond, lead frame or other form.
[0044] As those of skill will recognize, die 16 is connected to
flex circuits 18A and 18B through die pads 24 and die connectors
32. Flex circuits 18A and 18B are depicted with first and second
outer layers 36 and 38, respectively. Support layer 54 provides
structure for flex circuits 18A and 18B and conductive layer 52
provides conductivity between die connectors 32 and module contacts
30. Conductive layer 52 also provides conductivity between
integrated lower stack element 12 and added elements such as
another integrated lower stack element 12 or upper IC element 14
that may be aggregated to create module 10.
[0045] Those of skill will recognize that in the depicted
embodiment, conductive layer 52 is disposed closer to module
contacts 30 than is support layer 54. This relative placement is
preferred but not required. Such persons will also recognize that
support layer 54 provides a support function similar to that
provided by intermediate layer 44 in multi-layer flex circuitry
embodiments such as those earlier described herein.
[0046] Demarcation gap 56 depicted in FIG. 5 provides selective
isolation of lower flex contact 62 of conductive layer 52 from
areas of conductive layer 52 that may provide other functions or
other interconnections between different ones of die connectors 32
and module contacts 30 or other interconnections to other elements
of module 10. For example, in the embodiment of FIG. 5, flex
circuits 18A and 18B are shown as having one conductive layer
(i.e., layer 52). Therefore, in the depicted alternative
embodiment, that one conductive layer 52 is intended to provide
interconnectivity functions for module 10. Consequently, particular
interconnection features should be isolated from each other to
allow rational connections to be implemented in module 10 where
conductive layer structures are used. This is depicted by
demarcation gap 56, but those of skill will understand that
demarcation gap 56 is merely exemplary and assorted gaps and traces
may be used in conductive layer 52 just as they may (but need not
necessarily) be used in conductive layers in multi-conductive layer
flex embodiments to provide rational interconnectivity features for
module 10. However, as those of skill will recognize, the present
invention may be implemented with a flex circuitry that exhibits a
dedicated connective network of individual traces and/or
interconnections.
[0047] With continuing reference to FIG. 5, a signal may be
conveyed from die 16 through die pad 24 though die connector 32
through lower flex contact 62 at conductive layer 52 to module
contact 30. Such connection paths may convey voltage, ground or
data or instruction signal connections in and out of die 16.
[0048] In the depicted embodiment of FIG. 5, lower flex contacts 62
provide connection between die 16 and module contacts 30 as well as
participating in selected connections between die 16 and the
circuit of upper IC element 14. However, in addition, a set of flex
contacts such as those identified in later FIG. 7 as upper flex
contacts with respect to a second conductive layer 42 shown in FIG.
7, may, in the single conductive layer embodiment of FIG. 5,
participate in the connection between the circuit of upper IC
element 14 and the flex circuitry employed in the particular
embodiment.
[0049] FIG. 6 depicts an alternative preferred embodiment of the
present invention. In the embodiment as depicted in FIG. 6, die 16
is disposed above first outer surface 36 while die connective sites
which, in this instance, are die pads 24 are connected to lower
flex contacts 62 at the level of conductive layer 52 with wire bond
connections 20 through windows 46. Body 23 is formed about the
depicted die-flex combination and, in the preferred embodiment, is
formed employing protective surround 22. Module contacts 30 are
connected to the lower flex contacts 62 to express the appropriate
set of signals emanating from die 16. As those of skill will
understand as to the preferred embodiment of FIG. 6, when
integrated lower stack element 12 is incorporated into a module 10,
a set of upper contacts are articulated in the conductive layer 52
to provide connective facility for an upper IC element 14 or
another integrated lower stack element 12. Further, traces 64 may
be employed to provide connections between those upper flex
contacts and the lower flex contacts and appropriate module
contacts 30. Those of skill will recognize that in some instances,
there may be module contacts 30 that are connected only to an upper
element in a particular module 10.
[0050] FIG. 7 illustrates an exemplar second conductive layer 42 as
may be implemented in flex circuits 18A and 18B of a preferred
embodiment. Also shown is a depiction of die 16 and its underside
17. Identified in FIG. 7 are upper flex contacts 60 and lower flex
contacts 62 that are at the level of second conductive layer 42 of
flex circuits 18A and 18B. Upper flex contacts 60 and lower flex
contacts 62 are conductive material and, preferably, are solid
metal. Only some of upper flex contacts 60 and lower flex contacts
62 are identified with reference numerals in FIG. 7 to preserve
clarity of the view.
[0051] Each of flex circuits 18A and 18B in the depicted preferred
embodiment have both upper flex contacts 60 and lower flex contacts
62. Depending upon the contact pattern of die 16 and upper IC
element 14, some embodiments may exhibit only lower or only upper
flex contacts in flex circuits 18A or 18B.
[0052] In the preferred embodiment depicted in FIG. 7, lower flex
contacts 62 are employed with module contacts 30 to provide
connective facility for integrated lower stack element 12 in module
10. Thus, in a preferred embodiment, module contacts 30 are
connected to lower flex contacts 62 as shown in exemplar fashion in
FIG. 4 and in FIG. 5 in which figure a trace 64 is shown in the
connective path between via 50 and lower flex contact 62. However,
as those of skill will recognize, traces between selected upper and
lower flex contacts provide a connective path between upper IC
element 14 and integrated lower stack element 12 and/or directly to
module contacts 30.
[0053] As those of skill will recognize, interconnection of
respective contacts of upper IC element 14 and integrated lower
stack element 12 will also preferably provide a thermal path
between the two elements 12 and 14 to assist in moderation of
thermal gradients through module 10. Those of skill will notice
that between first and second conductive layers 40 and 42, there is
at least one intermediate layer 44 that, in a preferred embodiment,
is a polyimide. Placement of such an intermediate layer between
ground-conductive first conductive layer 40 and signal/voltage
conductive second conductive layer 42 provides, in the combination,
a distributed capacitance that assists in mitigation of ground
bounce phenomena to improve high frequency performance of module
10.
[0054] With continuing reference to FIG. 7, depicted are various
types of upper flex contacts 60, various types of lower flex
contacts 62, and traces 64. Lower flex contacts 62A are connected
to corresponding selected upper flex contacts 60A with signal
traces 64. To enhance the clarity of the view, only exemplar
individual flex contacts 62A and 60A and traces 64 are literally
identified in FIG. 7.
[0055] To improve high frequency performance, signal traces 64 may
be devised to exhibit path routes determined to provide
substantially equal signal lengths between corresponding flex
contacts 60A and 62A. For example, such relatively equal length
traces are illustrated in U.S. patent application Ser. No.
10/005,581 which is incorporated by reference into this
application.
[0056] As shown in the depicted preferred embodiment of FIG. 7,
traces 64 are separated from the larger surface area of second
conductive layer 42 that is identified as VDD plane 66. VDD plane
66 may be in one or more delineated sections but, preferably is
contiguous per flex circuit 18. Further, other embodiments may lack
VDD plane 66.
[0057] Lower flex contacts 62B and upper flex contacts 60B provide
connection to VDD plane 66. In a preferred embodiment, upper flex
contacts 60B and lower flex contacts 62B selectively connect upper
IC element 14 and integrated lower stack element 12, respectively,
to VDD plane 66.
[0058] Lower flex contacts 62 that are connected to first
conductive layer 40 by vias 50 are identified as lower flex
contacts 62C. To enhance the clarity of the view, only exemplar
individual lower flex contacts 62C are literally identified in FIG.
7. Upper flex contacts 60 that are connected to first conductive
layer 40 by vias 50 are identified as upper flex contacts 60C.
[0059] In some embodiments, as shown in incorporated U.S. patent
application Ser. No. 10/005,581, module 10 will exhibit an array of
module contacts 30 that has a greater number of contacts than the
constituent elements of module 10 individually exhibit. In such
embodiments, some of the module contacts 30 may contact lower flex
contacts 62 that do not make contact with one of the die contacts
24 of integrated lower stack element 12 but are connected to upper
IC contacts 19 of upper IC element 14. This allows module 10 to
express a wider datapath than that expressed by constituent
integrated lower stack element 12 or upper IC element 14.
[0060] A module contact 30 may also be in contact with a lower flex
contact 62 to provide a location through which different levels of
constituent elements of the module may be enabled when no unused
contacts are available or convenient for that purpose.
[0061] Those of skill will recognize that as flex circuitry 18 is
partially wrapped about lateral side 21 of integrated lower stack
element 12, first conductive layer 40 becomes, on the part of flex
18 disposed above upper surface 23 of integrated lower stack
element 12, the lower-most conductive layer of flex 18 from the
perspective of upper IC element 14. In the depicted embodiment,
those upper IC element contacts 19 of upper IC element 14 that
provide ground (VSS) connections are connected to the first
conductive layer 40. First conductive layer 40 lies beneath,
however, second conductive layer 42 in that part of flex 18 that is
wrapped above lower stack element 12. Consequently, in the depicted
preferred embodiment, those upper flex contacts 60 that are in
contact with ground-conveying upper IC element contacts 25 of upper
IC element 14 have vias that route through intermediate layer 44 to
reach first conductive layer 40. These vias may preferably be
"on-pad" or coincident with the flex contact 60 to which they are
connected.
[0062] As those of skill will recognize, there may be embodiments
of the present invention that may profitably employ off-pad vias
such as are described in previously cited U.S. application Ser. No.
10/005,581, filed Oct. 26, 2001, (the "'581 application) pending,
which is incorporated by reference herein.
[0063] Those of skill who refer to the '581 application will note
that the figures in that application will be instructive in
teaching details concerning a flex circuitry construction for
preferred embodiments of the present invention. Further, as those
of skill will recognize, the details on location and relationships
between upper and lower flex contacts as described in the '581
application are useful to preferred embodiments of the present
invention as modified to fit the particulars of the considered
embodiment. Further, alternative embodiments depicted in the '581
application are instructive in understanding alternatives available
for embodiments of the present invention. For example, the '581
application provides teachings that are descriptive of features
that may be employed to advantage in preferred embodiments in
accordance with the present invention where module 10 expresses a
datapath that is wider than that of the constituent circuits of
either integrated lower stack element 12 or upper IC element 14 or
where differential enablement of the respective elements of module
10 is desired as those skilled in the field will understand.
[0064] Although the present invention has been described in detail,
it will be apparent to those skilled in the art that the invention
may be embodied in a variety of specific forms and that various
changes, substitutions and alterations can be made without
departing from the spirit and scope of the invention. The described
embodiments are only illustrative and not restrictive and the scope
of the invention is, therefore, indicated by the following
claims.
* * * * *