U.S. patent application number 11/871504 was filed with the patent office on 2008-03-20 for ta-tan selective removal process for integrated device fabrication.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes, Robert Luke Wisnieff.
Application Number | 20080066860 11/871504 |
Document ID | / |
Family ID | 36913316 |
Filed Date | 2008-03-20 |
United States Patent
Application |
20080066860 |
Kind Code |
A1 |
Cotte; John Michael ; et
al. |
March 20, 2008 |
Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE
FABRICATION
Abstract
Disclosed are a method and a system for processing a
semiconductor structure of the type including a substrate, a
dielectric layer, and a TaN--Ta liner on the dielectric layer. The
method comprises the step of using XeF2 to remove at least a
portion of the TaN--Ta liner completely to the dielectric layer. In
the preferred embodiments, the present invention uses XeF2
selective gas phase etching as alternatives to Ta--TaN Chemical
Mechanical Polishing (CMP) as a basic "liner removal process" and
as a "selective cap plating base removal process." In this first
use, XeF2 is used to remove the metal liner, TaN--Ta, after copper
CMP. In the second use, the XeF2 etch is used to selectively remove
a plating base (TaN--Ta) that was used to form a metal cap layer
over the copper conductor.
Inventors: |
Cotte; John Michael; (New
Fairfield, CT) ; Hoivik; Nils Deneke; (Pleasantville,
NY) ; Jahnes; Christopher Vincent; (Upper Saddle
River, NJ) ; Wisnieff; Robert Luke; (Ridgefield,
CT) |
Correspondence
Address: |
SCULLY, SCOTT, MURPHY & PRESSER, P.C.
400 GARDEN CITY PLAZA
SUITE 300
GARDEN CITY
NY
11530
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
10504
|
Family ID: |
36913316 |
Appl. No.: |
11/871504 |
Filed: |
October 12, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11064561 |
Feb 24, 2005 |
|
|
|
11871504 |
Oct 12, 2007 |
|
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|
Current U.S.
Class: |
156/345.1 ;
257/E21.31; 257/E21.508; 257/E21.583 |
Current CPC
Class: |
H01L 2924/01029
20130101; H01L 2924/14 20130101; H01L 21/76849 20130101; H01L
2924/01078 20130101; H01L 23/53238 20130101; H01L 2924/01033
20130101; H01L 2924/19042 20130101; H01L 2924/01018 20130101; H01L
21/32135 20130101; H01L 2924/04953 20130101; H01L 2924/00 20130101;
H01L 2924/01073 20130101; H01L 21/76843 20130101; H01L 2924/01019
20130101; H01L 24/11 20130101; H01L 2224/13099 20130101; H01L
2924/14 20130101; H01L 2924/30105 20130101; H01L 2924/01002
20130101; H01L 21/76865 20130101; H01L 2924/01006 20130101; H01L
2924/01022 20130101; H01L 2924/01074 20130101; H01L 23/5227
20130101; H01L 21/7684 20130101; H01L 2924/01027 20130101; H01L
21/306 20130101; H01L 2924/01054 20130101; H01L 2924/01042
20130101 |
Class at
Publication: |
156/345.1 |
International
Class: |
C23F 1/00 20060101
C23F001/00 |
Claims
1-11. (canceled)
12. A system for processing a semiconductor structure of the type
including a substrate, a dielectric layer, and a TaN--Ta liner on
the dielectric layer, the system comprising: a source of XeF2 to
expose the TaN--Ta liner to XeF2 to remove at least a portion of
the TaN--Ta liner completely to the dielectric layer.
13. A system according to claim 12, wherein said XeF2 removes said
at least a portion of the TaN--Ta liner without appreciably
mechanically stressing or chemically altering said dielectric
material
14. A system according to claim 12, wherein the semi-conductor
structure further includes a copper layer extending above the
TaN--Ta liner, and wherein: the system further includes means for
removing the copper to a given level, lower than the top of the
TaN--Ta liner; and said XeF2 removes enough the TaN--Ta liner to
form a substantially planar top surface on the semiconductor
structure.
15. A system according to claim 12, wherein the dielectric material
forms a series of recesses, copper material is deposited in said
recesses to form a series of copper wire traces, and a metal cap is
formed on each of the copper wire traces, said metal caps defining
a top surface lower than the top surface of the TaN--Ta liner, and
wherein the XeF2 removes enough of the TaN--Ta liner to form a
substantially coplanar top surface on the semiconductor
structure.
16. A system according to claim 15, wherein the XeF2 removes the
TaN--Ta while substantially preserving the metal caps.
17. A system according to claim 12, wherein the semiconductor
structure includes a series of copper inductor coils extending to a
level higher than the TaN--Ta liner, and the semiconductor
structure forms a non-planar top surface, and wherein the XeF2
removes the TaN--Ta liner substantially completely from on top of
the dielectric material, between the copper inductor coils.
18-31. (canceled)
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention generally relates to integrated device
fabrication; and more specifically, the invention relates to
selective removal processes for integrated device fabrication. Even
more specifically, the invention relates to processes that may be
used effectively to remove selectively Ta--TaN layers or liners
during the fabrication of an integrated device and that are
compatible with low k dielectric materials.
[0003] 2. Background Art
[0004] Generally, in the fabrication of integrated devices, various
layers of materials, including copper and dielectric materials, are
formed and patterned or etched to produce the desired end product.
For example, Back-End-Of-Line (BEOL) interconnects are commonly
fabricated using a combination of sequential layering and
patterning of metal and dielectric films to produce an integrated
multilevel wiring architecture for various semiconductor
devices.
[0005] Advanced semiconductor devices typically require integrated
interconnects with more inputs and outputs, greater current
capacity, less signal delay and improved electrical noise
characteristics. To this extent, BEOL interconnects have advanced
by shrinking the cross-section of the wiring, increasing the levels
of wiring, using better conductivity metals, and also reducing the
intralevel capacitance by using low dielectric constant (low k)
materials.
[0006] Of particular relevance is the implementation of low k
materials in the BEOL structure. These materials have been
extremely challenging to implement because they are mechanically
weak and chemically sensitive to many of the processes used to
integrate BEOL structures. Of particular concern is direct chemical
mechanical polishing (CMP) of low k dielectrics, as is commonly
required for copper damascene in silicon dioxide. Mechanical
damage, water penetration and slurry incorporation can all cause
permanent damage to the low k dielectric. Furthermore, some
dielectric materials are used in BEOL devices as integration or
reliability enhancement layers and are detrimental to maintaining a
low k BEOL structure. It is therefore necessary to discover new
processes and integration techniques that are compatible with low k
materials to facilitate integration of low k materials into BEOL
structures.
SUMMARY OF THE INVENTION
[0007] An object of this invention is to improve processes for
fabricating integrated devices.
[0008] Another object of this invention is to provide improved
processes and integration techniques that are compatible with low k
dielectric materials to facilitate integration of low k materials
into BEOL structures.
[0009] A further object of the present invention is to use XeF2
selective gas phase etching as alternatives to Ta--TaN chemical
mechanical polishing in the fabrication of integrated circuit
devices.
[0010] These and other objectives are attained with a method and
system for processing a semiconductor structure of the type
including a substrate, a dielectric layer, and a TaN--Ta liner on
the dielectric layer. The method comprises the step of using XeF2
to remove at least a portion of the TaN--Ta liner completely to the
dielectric layer. In the preferred embodiments, the present
invention uses XeF2 selective gas phase etching as alternatives to
Ta--TaN Chemical Mechanical Polishing (CMP) as a basic "liner
removal process" and as a "selective cap conductive plating base
removal process."
[0011] In this first use, XeF2 is used to remove the metal liner,
TaN--Ta, after copper CMP to minimize mechanical stressing of the
low k material and chemical alteration of the low k dielectric
material, and to improve planarity after CMP. In the second use,
the XeF2 etch is used to selectively remove a plating base
(TaN--Ta) that was used to form a metal cap layer over the copper
conductor. In this use, the metal cap allows the elimination of a
high k dielectric cap normally required to prevent diffusion of
copper into the interconnect dielectric.
[0012] Further benefits and advantages of the invention will become
apparent from a consideration of the following detailed
description, given with reference to the accompanying drawings,
which specify and show preferred embodiments of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIGS. 1A-1C show a current fabrication process for a BEOL
interconnect structure.
[0014] FIGS. 2A-2C illustrate a first embodiment of this invention,
in which XeF2 is used to remove a TaN--Ta liner.
[0015] FIG. 3 is a table showing various measurements of several
materials subjected to XeF2 exposure.
[0016] FIGS. 4A and 4B show a second embodiment of the invention,
in which XeF2 is used to remove a TaN--Ta plating base/liner.
[0017] FIGS. 5A-5H illustrate a third embodiment of the invention,
in which XeF2 is used to remove a TaN--Ta liner formed in the
process of making copper coils on a semiconductor device.
[0018] FIG. 6 shows a device that may be used to expose a
semiconductor structure to XeF2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] The present invention, generally, relates to methods and
systems for processing semiconductor devices. More specifically,
the invention relates to processes for removing or etching metals
or metal layers, such as Ta--TaN, and that are compatible with
low-k dielectric materials. This, in turn, allows or facilitates
the use of low k dielectric materials for various applications in
semiconductor devices, in which applications it has heretofore been
difficult to use such dielectric materials.
[0020] The challenges and difficulties of using these low-k
dielectric materials in semiconductor devices are illustrated in
FIGS. 1A-1C. With reference to these Figures, copper wire traces 12
are formed in a dielectric 14 using copper damascene CMP. To
maintain planarity, it is ideal if the CMP process is highly
selective in all phases of the CMP. It first needs to polish the
copper with high selectivity to the TaN--Ta liner 16.
[0021] Following the copper CMP, the liner 16 is then polished, and
this polish must be selective to both copper and the dielectric.
This process has been shown to work well for conventional
dielectric materials such as SiO2; however, when low k films are
used, severe dielectric loss, mechanical degradation, and in some
cases chemical modification of the low k material commonly
occur.
[0022] Shown in FIGS. 2A to 2C is a novel integration process that
uses a copper CMP followed by the XeF2 TaN--Ta removal. The XeF2
liner removal process minimizes mechanical degradation of the
structure, minimizes chemical modification of the structure, and
minimizes the loss of the low-k dielectric 14. As can be seen, the
XeF2 process results in preserving all the low-k dielectric, FIG.
2C, while the all CMP process of FIG. 1C has some dielectric
loss.
[0023] To evaluate this application of XeF2, we have tested the
compatibility of a range of materials to excessively long XeF2
exposures (thousands of seconds as compared to tens of seconds
required). Materials such as SiO2, SiN, low k Si--C--O--H based
materials, TaN--Ta and copper were tested and relevant measurements
were performed to examine changes in these films. This data is
shown in table 1 of FIG. 3.
[0024] In a second embodiment, illustrated in FIGS. 4A and 4B, the
XeF2 etch is used to remove a plating base required for selective
metal cap 42 formation over the copper conductor 12. This process
has been tested to show that only the plating base is etched and
the metal cap 42 and surrounding dielectric 14 are preserved. Long
XeF2 etch tests with cobalt based cap layers showed only a 7% sheet
resistance increase which could be due to some impurity
incorporation on the surface or a 7% thickness loss.
[0025] Furthermore, we have also tested the compatibility of XeF2
with copper and found that no etching occurs.
[0026] In a third embodiment, the XeF2 etch is used to remove the
plating base/liner for a non-planar structure fabricated by through
mask plating or by the combination of damascene and through mask
plating. A high performance thick copper inductor is a typical
example of a device that could be fabricated in this manner.
[0027] FIGS. 5A-5H depict the combined process flow that results in
a non-planar structure, which renders plating base/liner removal by
CMP impossible. In accordance with the third embodiment of the
invention, the selective removal of the TaN/Ta plating base/liner
can be done either directly after resist strip or following
selective passivation of the exposed copper.
[0028] FIG. 5A shows a starting structure BEOL interconnect on a
semiconductor device. More specifically, FIG. 5A shows a substrate
52 with semiconductor devices, dielectric material 54 on that
substrate, and copper regions 56 embedded in the dielectric.
TaN--Ta liners 60 separate these copper regions from the dielectric
materials.
[0029] As indicated in FIG. 5B, a nitride cap 62 is formed over
copper regions 56 and substrate 52, and additional dielectric
material 64 is deposited on cap 62. Then, a first pattern 70 is
etched partially into dielectric material 64.
[0030] Then, with reference to FIG. 5C, a second pattern 72 is
etched through portions of dielectric material 64, exposing
selected areas of the dielectric 64 and of the copper regions 56.
As shown in FIG. 5D, liner 74 and copper seed layer 76 are
deposited over the patterned dielectric 64. Liner 74 is a TaN/Ta
material. Next, portions, or the high points, of the copper seed 76
are removed, producing the structure shown in FIG. 5E, where
specified portions of the TaN/Ta 76 are exposed. Then, as shown in
FIG. 5F, a polymer mold 80, which covers the exposed TaN/Ta
portions, is formed or placed on the structure. This mold 80
includes cavities or recesses 82, and, with reference to FIGS. 5F
and 5G, an electroplating process is used to form copper extensions
84.
[0031] The polymer mold 80 is then removed, resulting in the
structure of FIG. 5H. As can be seen, the top portions of this
structure has a non-planar shape, and this makes it difficult to
remove the exposed portions of the Ta/TaN liner 74 by means of a
chemical mechanical polish. However, in accordance with the present
invention, a XeF2 etch effectively removes those upper portions of
the exposed Ta/TaN liner 74 without chemically altering or
mechanically weakening dielectric layer, as shown in FIG. 5I.
[0032] Any suitable dielectric material may be used in the practice
of this invention. For instance, as mentioned above, the material
may be SiO2, SiN, or low k Si--C--O--H based materials. Also,
preferably, the dielectric material has a dielectric constant below
4, and, for example, this material may have a dielectric constant
between 1.2 and 4.
[0033] Any suitable procedure may be employed to use the XeF2 to
remove the Ta--TaN material from the semiconductor structure. For
example, with reference to FIG. 6, a dual chamber, dual pressure
device 90 may be used. Device 90 includes first and second chambers
92 and 94. Chamber 92 is at a low pressure such as, for instance,
0.5 to 2 or 3 Torr; and chamber 94 is at a lower pressure such as,
for example, 0-20 a few m Torr.
[0034] A solid source form of XeF2, represented at 96, is exposed
to the first chamber 92 through a valve 106; and the semiconductor
structure, represented at 98, that is to be subjected to the XeF2
is placed in the second chamber 94. Valves 102 and 104 between the
two chambers 92 and 94 are opened, and the XeF2 gas passes into the
second chamber 94, thereby exposing semiconductor structure 98 to
the XeF2. The semiconductor structure is exposed to the low
pressure XeF2 for a defined period of time, such as one to one
hundred seconds, and the XeF2 is then evacuated from chamber 94
through valve 110 into pump 100.
[0035] Chamber 94 may then be backfilled with nitrogen gas to help
clean the XeF2 off the semiconductor structure 98 and to help
ensure that the XeF2 is evacuated from chamber 94. Other gases may
be diluted to the XeF2 or used in the backfill process to improve
etch selectively or to help clean the semiconductor structure.
These gases can be introduced into either chamber through valves
102, 104, 112, 114, 116 and 118. For instance, gases may be used to
help displace water from the semiconductor structure. This backfill
process may last, for example, from one to 10-20 seconds, and may
be repeated. Additionally, substrate temperature control from
0.degree. C. to 400.degree. C. may be used to control chemical
reactions on substrate 98.
[0036] While it is apparent that the invention herein disclosed is
well calculated to fulfill the objects stated above, it will be
appreciated that numerous modifications and embodiments may be
devised by those skilled in the art, and it is intended that the
appended claims cover all such modifications and embodiments as
fall within the true spirit and scope of the present invention.
* * * * *