U.S. patent application number 11/876400 was filed with the patent office on 2008-02-28 for chip having timing analysis of paths performed within the chip during the design process.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Michael J. JR. Cadigan, James J. Curtin, Edward J. Hughes, Kevin M. Mcllvain, Jose L. Neves, Ray Raphy, Douglas S. Search.
Application Number | 20080052655 11/876400 |
Document ID | / |
Family ID | 39792941 |
Filed Date | 2008-02-28 |
United States Patent
Application |
20080052655 |
Kind Code |
A1 |
Curtin; James J. ; et
al. |
February 28, 2008 |
Chip Having Timing Analysis of Paths Performed Within the Chip
During the Design Process
Abstract
An integrated circuit chip is made using Genie, a described
computer chip design tool which can analyze the data contained
within an entire endpoint report, compute relationships between
paths based on shared segments, and display this information
graphically to the designer. Specifically, Genie groups failing
paths into Timing Islands. A timing island is a group of paths
which contain at least one shared segment. The most frequently
shared segment is sifted to the top of the priority list for each
island, and is labeled as the Hub. Thinking of timing islands as a
tree, the hub of the island would be the trunk. If you chop the
tree down by the trunk, all of the branches, limbs and twigs will
fall down too. This is analogous to fixing the timing failures in
the hub, and the fix trickling out to each of the segments that
dangle off the hub.
Inventors: |
Curtin; James J.; (Fishkill,
NY) ; Cadigan; Michael J. JR.; (Brewster, NY)
; Hughes; Edward J.; (Archbald, PA) ; Mcllvain;
Kevin M.; (Cold Spring, NY) ; Neves; Jose L.;
(Poughkeepsie, NY) ; Raphy; Ray; (Poughkeepsie,
NY) ; Search; Douglas S.; (Red Hook, NY) |
Correspondence
Address: |
INTERNATIONAL BUSINESS MACHINES CORPORATION
IPLAW DEPARTMENT
2455 SOUTH ROAD - MS P386
POUGHKEEPSIE
NY
12601
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
39792941 |
Appl. No.: |
11/876400 |
Filed: |
October 22, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11729784 |
Mar 30, 2007 |
|
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11876400 |
Oct 22, 2007 |
|
|
|
10890463 |
Jul 12, 2004 |
7120888 |
|
|
11729784 |
Mar 30, 2007 |
|
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Current U.S.
Class: |
716/114 ;
716/134; 716/139 |
Current CPC
Class: |
B62K 25/286 20130101;
G06F 30/3312 20200101; B62K 3/02 20130101 |
Class at
Publication: |
716/006 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Claims
1. A chip having timing analysis of paths performed within the chip
during the design process, comprising a substrate and a plurality
of paths formed thereon for providing an integrated circuit having
had many failing paths, and which has had a design correction made
by analysis and correction by commencing with an endpoint report,
and then performing data analysis for condensing many failing paths
into a concise format which identifies repetition/commonality
amongst those failing paths, and computing relationships between
paths analyzed based on shared segments of said identified
repetition/commonality, and while computing relationships grouping
failing paths into a group of paths which contain at least one
shared segment considered a timing island with timing paths,
wherein there are a plurality of shared segments and a most
frequently shared segment is sifted to a the top of a priority list
for each timing island, and is labeled as a hub, and display this
information displaying these relationships graphically to the a
designer.
2. A chip according to claim 1 wherein said design correction is
made by a tool for performing timing analysis of paths within chips
during the design process with steps comprising: commencing with an
endpoint report, performing data analysis for condensing many
thousands of failing paths into a concise format which identified
repetition/commonality among those failing paths, and computing
relationships between paths analyzed based on shared segments of
said identified repetition/commonality and while computing
relationships grouping failing paths into a group of paths which
contain at least one shared segment considered a timing island with
timing paths, wherein there are a plurality of shared segments and
a most frequently shared segment is sifted to a top of a priority
list for each timing island, and is labeled as a hub.
3. The chip according to claim 2 wherein said timing paths need
share only one segment when they are considered part of a same
timing island, and all timing path sequences are compared against
each other for finding exclusive timing islands.
4. The chip according to claim 3 wherein a common segment is a
shared segment of two sequences forming part of a same timing
island, and only a single common segment is used to determine
whether the paths of the common segment have similarity,
whereinafter the analysis is performed on a next sequence in the
endpoint report.
5. The chip according to claim 2 wherein if there are N failing
tests, in an instance where a first path in the endpoint report has
a similar segment to all of other paths, it is determined that
there would only be one island and the analysis is enabled to stop
after the first path has been compared to all paths in the report
for a Run time for this best case situation in O(N) runtime.
6. The chip according to claim 5 wherein when all paths are
exclusive and the analysis would have to compare all paths against
each other giving a worst case runtime O(N 2), this runtime is
reduced by instantiating a use of temporary bins to hold
intermediate results and said intermediate results are used to
gradually define timing islands to reduce a worst-case runtime to
O((N 2+N)/2) while a best case runtime time remains O(N).
7. The chip according to claim 2 wherein the tool further completes
a run writing out a timing island file of formatted contents of any
remaining bins for timing islands.
8. The chip according to claim 7 wherein said timing island file
will be read by a tool Graphical User Interface (GUI), which
displays timing island information, from which tool GUI users are
able to see each of independent timing islands.
9. The chip according to claim 8 wherein said tool further
comprises a GUI (Graphical User Interface) which allows users to
probe into each island to see segments with timing islands are
sorted by a worst slack within them, which prioritizes each timing
island by a severity of timing failures while segments within
timing islands are sorted by a number of paths they are repeated
in, identifying a hub at the top of the list and the "leaves" at
the bottom of the list, and allowing users to select timing islands
or segments, or any combination of the two, and display them
superimposed upon a placed design layout, as well as select a color
that the island is displayed in, and to draw the hub in a brighter
hue than the rest of the segments, enabling users to visually
identify hubs on the layout, and give insight how to fix the timing
failure within the hub.
10. The chip according to claim 2 wherein in addition to timing
island analysis, the tool further provides a slack analysis tool
allowing users to select one or more cells with a design tool and
vectors describing a slack pulling on the cell(s) to be displayed
enabling designers to use slack analysis capability to determine if
and how cells might be relocated within a placed design to cure
timing failures, and wherein the tool further provides a net weight
analysis by drawing vectors representing net weights pulling on the
selected cells.
11. The chip according to claim 2 further including a net weight
display tool allowing users to select one or more cells with a
design tool and drawing vectors representing net weights pulling on
selected cells to provide a designer some background information
for explaining why a cell was placed in a particular location.
12. The chip according to claim 2 further including slack analysis
and netweight tools for VLSI Integrated Model (VIM) modeling and
further including steps for examination of timing optimization
buffers for effectively comparing two VIM states, wherein a first
VIM state is a after timing optimization but pre-placement state,
and a second VIM state is a placement-optimized VIM state for
computing accurate slacks on a placed design allowing designers to
directly see how placement has affected their timing, and said tool
further comprises a buffer look-through for allowing for an
observation of logic connectivity before placement optimization
while observing this pre-placement optimized connectivity allowing
users to quickly understand important point connections within a
placement-optimized design.
13. The chip according to claim 2 wherein the tool after tracing
through said buffer look-through displays a single vector
representation of timing optimized VIM state connectivity within
placement optimized VIM state.
14. The chip according to claim 2 wherein said tool further
displays common cell island groups in which timing islands sharing
one or more common cells are linked together for display to permit
designers to see linked timing which links together all timing
islands that share at least one cell.
15. The chip according to claim 2 said tool further comprises an
incremental buffer strip and rebuild computation whereby when users
move cells, slack is computed by looking through buffers, and if
the buffers are still in the placement, which could possibly made
the slacks appear to get worse, the rebuild computation will detect
a movement, and will strip out and reinsert timing optimization
buffers in new locations reflecting new positions of the
cell(s).
16. The chip according to claim 2 wherein additional path
characteristics are displayed by coloring fixed cells blue and
enabling cells which have particular keywords and other special
attributes to be colored different shades or otherwise displayed
differently to a user.
17. The chip according to claim 2 wherein said tool further
enabling designers to use said grouping to discover dependencies
between cells of logic and further enabling designers to
parallelize timing optimization, and wherein the tool enables a
designer to isolate timing islands, and dispatch several machines
concurrently to attack each respective timing island to then pull
all of the designers parallel fixes back together, and to combine
results of said several machines in one final processing pass on a
single machine to discover any remaining problems or conflicts.
Description
[0001] This application is a continuation of U.S. Ser. No.
11/729784 which in turn is a continuation in part of U.S. Ser. No.
10/890463, filed Jul. 12, 2004, and entitled "Method, System and
Storage Medium for Determining Circuit Placement" by James Curtin
et al., and contains subject matter which is related to the subject
matter of the following co-pending applications, each of which is
assigned to the same assignee as this application, International
Business Machines Corporation of Armonk, N.Y. Each of the below
listed applications is hereby incorporated herein by reference in
its entirety:
[0002] U.S. Ser. No. 11/129,786 filed May 16, 2005 and entitled "A
method for netlist path characteristics extraction"
[0003] U.S. Ser. No. 11/129,785 filed May 16, 2005 and entitled
"Negative Slack Recoverability Factor--A net weight to enhance
timing closure behavior"
TRADEMARKS
[0004] IBM.RTM. is a registered trademark of International Business
Machines Corporation, Armonk, N.Y., U.S.A. and other names used
herein may be registered trademarks, trademarks or product names of
International Business Machines Corporation or other companies.
BACKGROUND OF THE INVENTION
[0005] 1. Field of the Invention
[0006] This invention relates to chip circuit design, and
particularly a chip made using a tool for integrated circuit
design, one which can analyze the data contained within an entire
endpoint report, compute relationships between paths based on
shared segments, and display this information graphically to the
designer.
[0007] 2. Description of Background
[0008] When performing timing analysis of paths within chips there
often are many hundreds or thousands of paths which fail to meet
timing requirements. Many of those failing paths can be related in
that a few common segments within them are causing timing failures,
and all the rest of the connections within the paths are very close
to or meet timing. Unfortunately, a tool does not exist which can
find the commonality in failing paths.
[0009] Commonly, these paths are reported to users in the form of
an Endpoint Report. The Endpoint report is a text based file which
contains detailed descriptions of timing test failures. Endpoint
reports are very lengthy and verbose, requiring users to scroll
horizontally and vertically. They do not group related paths nor
identify the overlapping segments within them. There is a lot of
information in an endpoint report; so much that often there is too
much information for an engineer to comprehend.
[0010] One known solution to the problem of having too much
information can be found in the Critical Path Chart. This is a
chart that graphically represents paths using multiple colors and
bars of different length representing logic and wire delay.
However, the critical path chart cannot find relationships between
failing paths. The graphical representation can hint at the
relationships, but the critical path chart does not definitively
describe the commonality between them.
[0011] A tool is needed which can condense many thousands of
failing paths into a concise format which identifies
repetition/commonality amongst those paths. Such a tool will save
design engineers a lot of time in fixing timing problems by
providing insight and priorities for fixing negative slack timing
test failures.
SUMMARY OF THE INVENTION
[0012] The shortcomings of the prior art are overcome and
additional advantages are provided by a chip made through the
provision of the tool we call Genie which is a tool which can
analyze the data contained within an entire endpoint report,
compute relationships between paths based on shared segments, and
display this information graphically to the designer. Specifically,
Genie groups failing paths into Timing Islands. A timing island is
a group of paths which contain at least one shared segment. The
most frequently shared segment is sifted to the top of the priority
list for each island, and is labeled as the Hub. Thinking of timing
islands as a tree, the hub of the island would be the trunk. If you
chop the tree down by the trunk, all of the branches, limbs and
twigs will fall down too. This is analogous to fixing the timing
failures in the hub, and the fix trickling out to each of the
segments that dangle off the hub.
[0013] Previously, using only endpoint reports or the critical path
chart, users would not be able to easily identify the hub, and
would spend days and weeks manually investigating individual paths.
Users would often cull only the worst 500 or so failing paths and
ignore the rest (perhaps thousands) because there was too much
information to handle.
[0014] Our system during setup allows the user to maker a choice
between late mode and early mode for the Endpoint report and the
tests they would like to run.
[0015] System and computer program products corresponding to the
above-summarized methods are also described and claimed herein.
[0016] Additional features and advantages are realized through the
techniques of the present invention. Other embodiments and aspects
of the invention are described in detail herein and are considered
a part of the claimed invention. For a better understanding of the
invention with advantages and features, refer to the description
and to the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The subject matter which is regarded as the invention is
particularly pointed out and distinctly claimed in the claims at
the conclusion of the specification. The foregoing and other
objects, features, and advantages of the invention are apparent
from the following detailed description taken in conjunction with
the accompanying drawings in which:
[0018] FIG. 1 illustrates one example of the application of the
preferred embodiment where a timing island is a group of failing
timing paths that contain at least one shared segment or hub.
[0019] FIG. 2 illustrates an example of a preferred timing path
flowchart for generating a timing island file which represents the
islands.
[0020] FIG. 3 illustrates a timing optimized VIM (VIM=VLSI
Integrated Model) and a placement optimized VIM.
[0021] FIG. 4 illustrated the interrelationship of timing islands
showing shared cells. A cell is a logic device or element such as a
latch, AND gate, SRAM, etc.
[0022] The detailed description explains the preferred embodiments
of the invention, together with advantages and features, by way of
example with reference to the drawings.
DETAILED DESCRIPTION OF THE INVENTION
[0023] When performing late mode timing analysis of paths within
chips, those paths which cannot meet timing are labeled as having a
negative slack- their signals propagate too slowly causing data to
arrive late. Often there are many hundreds or thousands of paths
which fail to meet timing requirements. Many of those failing paths
can be related in that a few common segments within them are
causing timing failures, and all of the rest of the connections
within the paths are very close to or meet timing. Unfortunately, a
tool does not exist which can find the commonality in failing
paths.
[0024] Commonly, these paths are reported to users in the form of
an Endpoint Report. The Endpoint report is a text based file which
contains detailed descriptions of timing test failures. Endpoint
reports are very lengthy and verbose, requiring users to scroll
horizontally and vertically. They do not group related paths nor
identify the overlapping segments within them. There is a lot of
information in an endpoint report; so much that often there is too
much information for an engineer to comprehend.
[0025] One known solution to the problem of having too much
information can be found in the Critical Path Chart. This is a
chart that graphically represents paths using multiple colors and
bars of different length representing logic and wire delay.
However, the critical path chart cannot find relationships between
failing paths. The graphical representation can hint at the
relationships, but the critical path chart does not definitively
describe the commonality between them.
[0026] A tool is needed which can condense many thousands of
failing paths into a concise format which identifies
repetition/commonality amongst those paths. Such a tool will save
design engineers a lot of time in fixing timing problems by
providing insight and priorities for fixing negative slack timing
test failures.
[0027] Genie is a tool which can analyze the data contained within
an entire endpoint report, compute relationships between paths
based on shared segments, and display this information graphically
to the designer. Specifically, Genie groups failing paths into
Timing Islands. A timing island is a group of paths which contain
at least one shared segment. The most frequently shared segment is
sifted to the top of the priority list for each island, and is
labeled as the Hub. Thinking of timing islands as a tree, the hub
of the island would be the trunk. If you chop the tree down by the
trunk, all of the branches, limbs and twigs will fall down too.
This is analogous to fixing the timing failures in the hub, and the
fix trickling out to each of the segments that dangle off the
hub.
[0028] Previously, using only endpoint reports or the critical path
chart, users would not be able to easily identify the hub, and
would spend days and weeks manually investigating individual paths.
Users would often cull only the worst 500 or so failing paths and
ignore the rest (perhaps thousands) because there was too much
information to handle.
[0029] A significant portion of Genie has already been implemented
as software that extends, and is being incorporated into, IBM EDA's
ChipBench suite, a preferred chip design tool, using Chipbench:
version 10.1 maint 66. First, Genie, as illustrated in FIG. 2,
generates a custom endpoint report: this contains only a subset of
information available in traditional endpoint reports. The custom
report is designed to be interpreted by a computer program, not a
human being, and is condensed to keep data processing and storage
requirements to a minimum.
[0030] Genie processes the custom endpoint report using an
abstraction of a DNA sequence alignment algorithm to group timing
paths into timing islands. Typically, DNA sequence alignment is
used to locate regions of similarity between a query sequence
(sequence of unknown function and structure) and other known DNA
sequences. These regions of similarity help reveal the homology,
genealogy, functionality and structure of the query sequence.
Likewise, similar methodology may be used to discover independent
timing problems in ASIC designs. Timing paths within an ASIC may be
represented as sequences of segments (a segment being a pin to pin
connection) instead of sequences of amino acids as with DNA. Like
the DNA sequences, the ASIC timing path sequences may be aligned
with each other to discover homogenous regions (partial path
equalities). The partial path equivalences, which are defined as
hubs, tend to be the most likely cause of timing problems and are
of high interest to the designer.
[0031] Aligning DNA sequences involves comparing the sequences to
find a series of characters or patterns that are in the same order
in both of the sequences. The two sequences can be written on a
page in two rows on top of one another. The objective will be to
find the alignment, where the greatest number of identical
characters, are in vertical register. Often this involves inserting
gaps and aligning mismatched characters. Table 1 shows a small
example. TABLE-US-00001 TABLE 1 (Human alignment of two sequences
which happen to be of unequal length) SEQ1 VESLCY SEQ2 VDSCY VESLCY
VDS-CY
[0032] As seen in Table 1 the two sequences are of unequal length
and required the insertion of a gap and left one pair of characters
(amino acids E and D) mismatched. This example is representative of
a simple DNA sequence alignment. [0033] However, DNA sequences are
lengthy and human alignment can be error prone and very time
consuming. This created a need to develop alignment algorithms that
would reduce time and error. Most alignment algorithms use various
forms of matrices. The first algorithm to use the matrix approach
was the Dot Matrix algorithm described by Gibbs and McIntyre (1970)
which is incorporated herein and is found as Gibbs & McIntyre,
1970 [0034] Gibbs, A. J. & McIntyre, G. A. (1970). [0035] The
Diagram Method for Comparing Sequences. Its Use with Amino Acid and
Nucleotide Sequences. [0036] Eur. J. Biochem. 16, 1-11.
[0037] This Dot Matrix algorithm has become a standard tool which
can quickly determine whether two sequences may have a possible
alignment. This algorithm sets up a comparison matrix to determine
the sequence similarities. Using the same small sequences as in
Table 1, an example of a Dot Matrix algorithm follows in Table 2:
TABLE-US-00002 TABLE 2 V E S L C Y V X D S X C X Y X
[0038] In accordance with the preferred process, first a matrix is
set up where each column of the matrix represents a letter of
sequence one and each row represents a character of sequence two.
Once the matrix is set up, each position of the matrix is marked
with an X if both the letter at the top of the column and the
beginning of the row are the same. Everywhere an X shows up there
is a similarity between the sequences. It is ideal to find long
diagonal strings of Xs (CiRi,Ci+1Ri+1 . . . Ci+kRi+k where i,k
integers>0 and C means column and R means row) as this indicates
a possible conserved region (regions of similar function or
structure). The longest diagonal in the example is found at C5R4
and continues through C6R5. The completed matrix infers the
following alignment illustrated by Table 3. TABLE-US-00003 TABLE 3
V_S_CY V_S CY
[0039] Each _ (underscored space) in the alignment represents a
character which was not aligned and each blank between characters
which is not underscored represents a gap. Using short sequences as
in the above example it is easy to determine what the alignment
should be and where the gaps should go.
[0040] The problem with this algorithm is the possibility of
character repetition in DNA sequences. Just as an example what if
the two sequences were VVVVVV and VVVVV. Applying the dot matrix
algorithm would cause every location in the matrix to be marked
with an X. This is both a downfall and advantage of the Dot Matrix
algorithm. Interpreting the resulting matrix may make for a
difficult alignment but at the same time, may indicate regions of
special interest in the DNA sequence. In order to alleviate the
alignment problems due to amino acid repetition the Dot Matrix
algorithm evolved into an algorithm which used a unary scoring
matrix. Instead of Xs each match was marked with a 1 and gap
penalties were also issued. Yet, unlike a DNA sequence, ASIC timing
paths are built of unique segments, where each segment is found
only once in the design. Therefore, repetition and substitution are
not issues with timing path alignment and an abstraction of the
basic Dot Matrix method will be sufficient to perform timing island
discovery.
[0041] The abstraction on the Dot Matrix algorithm and the concept
of timing islands are what make the Genie algorithm unique. In
order to properly explain the abstraction, the problem will be
restated.
[0042] Genie must process a custom report of failing timing paths
into a group of timing islands, where a timing island is a group of
failing timing paths that contain at least one shared segment (see
FIG. 1). So, the preferred embodiment employs key points for the
Genie implementation, these are: timing paths need share only one
segment to be part of the same island and all path sequences must
be compared against each other to properly find exclusive timing
islands. These are key differences to the Dot Matrix algorithm. The
Dot Matrix Algorithm is designed to fully compare two sequences to
find all like amino acid subsequences between two DNA sequences or
sometimes executed multiple times to compare a query sequence
against a large database of sequences.
[0043] The first point, that paths need only share one segment to
be members of the same island, may be implemented by modifying the
Dot-Matrix algorithm as follows. The example based on Table 2 may
be used again by replacing the DNA sequences with timing path
sequences (since the sequences in Table2 are composed of unique
elements, the same sequences may represent timing paths). Examining
the Table 2 shows a common segment in the comparison of C1R1. This
fits the definition of a timing island, thus the two sequences are
part of the same island. In addition this happens to be the best
case performance result since only one compare was needed to
determine whether the paths had similarity. The algorithm may stop
here and compare the query sequence to the next sequence in the
report. Ending the sequence alignment before a complete comparison
is part of the abstraction. The worst case performance scenario is
two paths that have no commonality. This would cause a full
comparison of all segments in each path.
[0044] The second point, that all paths must be compared to all
other paths may be interpreted as the following. If there are N
failing tests, the unmodified Dot Matrix Algorithm must be run N 2
times to ensure the resulting islands are exclusive. As the number
of failing paths increases the O(N 2) runtime would increase to
levels which may drastically affect usability. This situation has
been accounted for in the Genie algorithm. In a situation where the
first path in the report has a similar segment to all of the other
paths, there would only be one island. Ideally in this situation,
the program would stop after the first path has been compared to
all paths in the report. Run time for this best case situation is
in O(N) time.
[0045] In the situation where all paths are exclusive the algorithm
would have to compare all paths against each other giving the worst
case runtime O(N 2). This is also reduced in the Genie algorithm by
instantiating the use of temporary bins to hold intermediate
results. These intermediate results are used to gradually define
the islands. Placing the intermediate results into bins allows the
worst case runtime to be reduced from O(N 2) (all paths are
exclusive) to O((N 2+N)/2) and the best case time remains O(N). In
effect, the temporary bins help eliminate redundant segment
compares and still allows for exclusivity amongst timing islands.
FIG. 2 provides a detailed description of the complete Genie timing
island generation algorithm.
[0046] The Genie Algorithm finishes by writing out a timing island
file (formatted contents of the remaining bins). The timing island
file will be read by Genie's Graphical User Interface, which
displays the timing island information. From the Genie GUI, users
are able to see each of the independent timing islands. The GUI
allows users to probe into each island to see its comprising
segments. Islands are sorted by the worst slack within them, which
prioritizes each island by the severity of the timing failures.
Segments within islands are sorted by the number of paths they are
repeated in, identifying the hub at the top of the list and the
"leaves" at the bottom.
[0047] Users can select timing islands or segments, or any
combination of the two, and display them superimposed upon a placed
design layout. Genie allows users to select the color that the
island is displayed in, and will draw the hub in a brighter hue
than the rest of the segments. This will allow users to visually
identify hubs on the layout, and give insight how to fix the timing
failure within the hub.
[0048] Genie can color fixed (here, we mean immobile; constrained
by the placement) cells blue along paths it displays. The user can
enable and disable this feature easily within the Genie
program.
[0049] In addition to timing island analysis, Genie provides a
slack analysis tool and a net weight display tool. Users can select
one or more cells within ChipBench and Genie will display vectors
describing the slack pulling on the cell(s). Color is used to
represent the amount of slack--red for negative slack; and yellow,
orange, and blue for various amounts of positive slack. Genie looks
through timing optimization buffers when computing these slacks,
therefore the vectors actually point to the next connecting logic
device, not to a timing buffer. Designers can use the slack
analysis capability to determine if and how cells might be
relocated within a placed design to cure timing failures. Genie's
net weight display tool is similar to the slack analysis tool in
that it draws vectors representing the net weights pulling on
selected cells. This information will provide the designer some
background information, perhaps explaining why a cell was placed in
a particular location.
[0050] Looking through timing optimization buffers is a significant
feature of the slack analysis and net weight tools. By looking
through timing optimization buffers, Genie is essentially comparing
two VIM states--the VIM after timing optimization but
pre-placement, and the placement-optimized VIM--to compute accurate
slacks on a placed design. This capability allows designers to
directly see how placement has affected their timing. Buffer
look-through allows for the observation of the logic connectivity
before placement optimization. Observing this pre-placement
optimized connectivity allows users to quickly understand the
important point connections within the placement-optimized design.
For instance the designer should not care where the timing
optimization buffers are placed as long as the path meets it's
timing requirements. The FIG. 3 below shows an example of the same
path in two VIM states.
[0051] Genie solves the problem depicted in the above FIG. 3 by
tracing through the buffers and displaying a single vector from L1
to L2. This vector is the representation of the timing optimized
VIM connectivity within the placement optimized VIM.
[0052] Whereas all of the above features currently exist in Genie,
there are several other features which are included in our
preferred embodiment. The first is "common cell island groups", in
which timing islands sharing one or more common cells will be
linked together for display. This function would permit designers
to see timing problems stemming from, driving to, or passing
through common cells--a type of analysis that does not currently
exist. Also, "common cell island chains" link together all timing
groups that contain a common timing island, thus connecting the
islands into chains based on shared cells. Examples of both common
cell island groups and common cell island chains are depicted in
FIG. 4.
[0053] Next, "incremental buffer strip and rebuild" is a feature
which relates to the Genie slack analysis tool. When users move
cells, Genie computes slack by looking through the buffers.
However, the buffers are still in the placement, which could
possibly make the slacks appear to get worse. This new feature will
detect a movement, and will strip out and reinsert timing
optimization buffers in new locations reflecting the new position
of the cell(s). Lastly, Genie will show additional path
characteristics. Currently, Genie will color fixed cells blue; with
this new feature, cells which have particular syn_hide keywords and
other special attributes will be colored different shades or
otherwise displayed differently to the user. This information is
already available within ChipBench, but not in this format.
[0054] Applications in the synthesis process flow also exist for
Genie. For instance, designers can use the grouping capabilities to
discover dependencies between cells of logic. Finally, Genie can be
used to parallelize timing optimization. That is, a designer can
use Genie to isolate timing islands, and dispatch several machines
concurrently to attack each respective island. The designer can
then pull all of the parallel fixes back together in one final
processing pass on a single machine to discover any remaining
problems or conflicts.
[0055] The capabilities of the present invention can be implemented
in software, firmware, hardware or some combination thereof and
used to provide a service for use in chip design.
[0056] As one example, one or more aspects of the present invention
can be included in an tool of manufacture (e.g., one or more
computer program products) having, for instance, computer usable
media. The media has embodied therein, for instance, computer
readable program code means for providing and facilitating the
capabilities of the present invention. The article of manufacture
can be included as a part of a computer system or sold
separately.
[0057] Additionally, at least one program storage device readable
by a machine, tangibly embodying at least one program of
instructions executable by the machine to perform the capabilities
of the present invention can be provided.
[0058] The flow diagrams depicted herein are just examples. There
may be many variations to these diagrams or the steps (or
operations) described therein without departing from the spirit of
the invention. For instance, the steps may be performed in a
differing order, or steps may be added, deleted or modified. All of
these variations are considered a part of the claimed
invention.
[0059] While the preferred embodiment to the invention has been
described, it will be understood that those skilled in the art,
both now and in the future, may make various improvements and
enhancements which fall within the scope of the claims which
follow. These claims should be construed to maintain the proper
protection for the invention first described.
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