| Patent | Date |
|---|
Incremental parasitic extraction for coupled timing and power optimization
Grant 10,169,526 - Kalafala , et al. J | 2019-01-01 |
Simulation of modifications to microprocessor design
Grant 9,934,341 - Berry , et al. April 3, 2 | 2018-04-03 |
Simulation of modifications to microprocessor design
Grant 9,928,322 - Berry , et al. March 27, 2 | 2018-03-27 |
Incremental Parasitic Extraction For Coupled Timing And Power Optimization
App 20180068052 - Kalafala; Kerim ; et al. | 2018-03-08 |
Incremental parasitic extraction for coupled timing and power optimization
Grant 9,858,383 - Kalafala , et al. January 2, 2 | 2018-01-02 |
Control path power adjustment for chip design
Grant 9,734,270 - Berry , et al. August 15, 2 | 2017-08-15 |
Control path power adjustment for chip design
Grant 9,703,910 - Berry , et al. July 11, 2 | 2017-07-11 |
Incremental Parasitic Extraction For Coupled Timing And Power Optimization
App 20170177784 - Kalafala; Kerim ; et al. | 2017-06-22 |
Simulation Of Modifications To Microprocessor Design
App 20170132340 - Berry; Christopher J. ; et al. | 2017-05-11 |
Simulation Of Modifications To Microprocessor Design
App 20170132341 - Berry; Christopher J. ; et al. | 2017-05-11 |
Control Path Power Adjustment For Chip Design
App 20170011156 - Berry; Christopher J. ; et al. | 2017-01-12 |
Control Path Power Adjustment For Chip Design
App 20170011157 - Berry; Christopher J. ; et al. | 2017-01-12 |
Reducing repeater power
Grant 9,256,705 - Kartschoke , et al. February 9, 2 | 2016-02-09 |
Reducing repeater power
Grant 9,223,918 - Kartschoke , et al. December 29, 2 | 2015-12-29 |
Reducing Repeater Power
App 20140088948 - Kartschoke; Paul D. ; et al. | 2014-03-27 |
Reducing Repeater Power
App 20130275110 - Kartschoke; Paul D. ; et al. | 2013-10-17 |
Reduction of logic and delay through latch polarity inversion
Grant 8,108,821 - Chen , et al. January 31, 2 | 2012-01-31 |
Reduction Of Logic And Delay Through Latch Polarity Inversion
App 20110173584 - Chen; Jonathan Y. ; et al. | 2011-07-14 |
System and medium for placement which maintain optimized timing behavior, while improving wireability potential
Grant 7,921,398 - Curtin , et al. April 5, 2 | 2011-04-05 |
Clock distribution network wiring structure
Grant 7,831,946 - Dennis , et al. November 9, 2 | 2010-11-09 |
Chip having timing analysis of paths performed within the chip during the design process
Grant 7,823,108 - Curtin , et al. October 26, 2 | 2010-10-26 |
Method for eliminating negative slack in a netlist via transformation and slack categorization
Grant 7,810,062 - Curtin , et al. October 5, 2 | 2010-10-05 |
Method For Eliminating Negative Slack In A Netlist Via Transformation And Slack Categorization
App 20090070715 - Curtin; James J. ; et al. | 2009-03-12 |
Clock Distribution Network Wiring Structure
App 20090033398 - Dennis; Rick L. ; et al. | 2009-02-05 |
System and Medium for Placement Which Maintain Optimized Timing Behavior, While Improving Wireability Potential
App 20080163149 - Curtin; James J. ; et al. | 2008-07-03 |
Methods for placement which maintain optimized behavior, while improving wireability potential
Grant 7,376,924 - Curtin , et al. May 20, 2 | 2008-05-20 |
Genie: a method for classification and graphical display of negative slack timing test failures
Grant 7,356,793 - Curtin , et al. April 8, 2 | 2008-04-08 |
Chip Having Timing Analysis of Paths Performed Within the Chip During the Design Process
App 20080066036 - Curtin; James J. ; et al. | 2008-03-13 |
Chip Having Timing Analysis of Paths Performed Within the Chip During the Design Process
App 20080052655 - Curtin; James J. ; et al. | 2008-02-28 |
Genie: a method for classification and graphical display of negative slack timing test failures
App 20060010410 - Curtin; James J. ; et al. | 2006-01-12 |
Methods for placement which maintain optimized behavior, while improving wireability potential
App 20060010413 - Curtin; James J. ; et al. | 2006-01-12 |
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