U.S. patent application number 11/845707 was filed with the patent office on 2007-12-20 for semiconductor device having silicide thin film and method of forming the same.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Joon-Yong JOO, Sung-Bong KIM, Kwang-Ok KOH, Hyung-Shin KWON.
Application Number | 20070293030 11/845707 |
Document ID | / |
Family ID | 19707084 |
Filed Date | 2007-12-20 |
United States Patent
Application |
20070293030 |
Kind Code |
A1 |
KWON; Hyung-Shin ; et
al. |
December 20, 2007 |
SEMICONDUCTOR DEVICE HAVING SILICIDE THIN FILM AND METHOD OF
FORMING THE SAME
Abstract
The present invention provides a semiconductor device having a
silicide thin film and method of forming the same. A semiconductor
device comprises a gate insulation layer formed on an active region
of a semiconductor substrate. A gate electrode is formed on the
gate insulation layer. An impurity region is formed in the active
region adjacent the gate electrode. A silicide thin film such as a
cobalt silicide thin film is formed to a thickness of less than
approximately 200 .ANG. in the impurity region.
Inventors: |
KWON; Hyung-Shin;
(Kyunggi-do, KR) ; JOO; Joon-Yong; (Seoul, KR)
; KOH; Kwang-Ok; (Kyunggi-do, KR) ; KIM;
Sung-Bong; (Kyunggi-do, KR) |
Correspondence
Address: |
MARGER JOHNSON & MCCOLLOM, P.C.
210 SW MORRISON STREET, SUITE 400
PORTLAND
OR
97204
US
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
Gyeonggi-do
KR
|
Family ID: |
19707084 |
Appl. No.: |
11/845707 |
Filed: |
August 27, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10830390 |
Apr 21, 2004 |
|
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|
11845707 |
Aug 27, 2007 |
|
|
|
10100929 |
Mar 18, 2002 |
6767814 |
|
|
11845707 |
Aug 27, 2007 |
|
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|
Current U.S.
Class: |
438/592 ;
257/E21.438; 257/E21.439; 257/E21.444 |
Current CPC
Class: |
H01L 21/28052 20130101;
H01L 29/6653 20130101; H01L 29/665 20130101; H01L 21/28518
20130101; H01L 29/66507 20130101; H01L 29/66545 20130101 |
Class at
Publication: |
438/592 ;
257/E21.439 |
International
Class: |
H01L 21/3205 20060101
H01L021/3205 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 19, 2001 |
KR |
2001-14004 |
Claims
1. A method for forming a semiconductor device, comprising: forming
a gate insulation layer on a semiconductor substrate; forming a
gate electrode on the gate insulation layer; forming a
lightly-doped impurity region in the semiconductor substrate
adjacent to the sidewalls of the gate electrode; forming a first
spacer on the both sides of the gate electrode and on the
lightly-doped impurity region, wherein the first spacer is
L-shaped; forming a second spacer on the first spacer; forming a
heavily-doped impurity region in the semiconductor substrate
adjacent to the second spacer; forming a cobalt layer on gate
electrode, the first spacer, the second spacer and the
heavily-doped impurity region; performing a first heat treatment at
a first temperature to react a portion of the cobalt layer with the
semiconductor substrate, thereby forming a first-type metal
silicide layer; removing non-reacted portions of the cobalt layer;
forming a subsidiary layer on the gate electrode, the first spacer,
the second spacer and the first-type metal silicide layer; and
performing a second heat treatment at a second temperature thereby
transforming the first-type metal silicide layer into a second-type
metal silicide layer, wherein the second heat treatment is
performed such that, during the second heat treatment, a portion of
the subsidiary layer facing toward the second-type cobalt silicide
layer consumes oxygen contained in the first-type metal silicide
layer.
2. The method according to claim 1, further comprising forming a
capping layer on the cobalt layer.
3. The method according to claim 2, wherein the first heat
treatment is performed during the forming the capping layer.
4. The method according to claim 1, wherein the second temperature
is higher than the first temperature.
5. The method according to claim 4, wherein the first temperature
is 150.about.300.degree. C. and the second temperature greater than
700.degree. C.
6. The method according to claim 1, wherein the subsidiary layer
comprises silicon oxynitride.
7. The method according to claim 6, wherein the portion of the
subsidiary layer facing toward the second-type cobalt silicide
layer has a higher oxygen concentration than a portion of the
subsidiary layer facing away from the second-type cobalt silicide
layer after the second heat treatment.
8. The method according to claim 6, further comprising forming an
interlayer dielectric layer on the subsidiary layer, wherein the
interlayer dielectric layer has an etch selectivity with respect to
the subsidiary layer.
9. The method according to claim 1, further comprising, before
forming the cobalt layer, reducing a height of the first spacer and
the second spacer to expose an upper portion of the gate electrode.
Description
[0001] This application is a Divisional of U.S. patent application
Ser. No. 10/830,390, filed Apr. 21, 2004, now pending, which is a
Divisional of U.S. patent application Ser. No. 10/100,929, filed
Mar. 18, 2002, now issued U.S. Pat. No. 6,767,814, which claims the
benefit of priority from Korean Patent Application No. 2001-14004,
filed Mar. 19, 2001, all of which are herein incorporated by
reference in their entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device and
method of forming the same, and more particularly to a
semiconductor device having a silicide thin film and method of
forming the same.
[0004] 2. Description of the Related Art
[0005] Silicon generally has the properties of semiconductor, but
acts as a conductor when impurities are implanted into it, as is
the case when used in a semiconductor device. In addition, silicon
and metal can be easily transformed into a metal silicide having
high conductivity. Accordingly, in a highly-integrated
semiconductor device in which resistance increases as the width of
a conductive line such as a gate line and contact sizes are
reduced, metal silicide is often used to form a portion of a
contact interface or a signal line such as the gate line to enhance
the conductivity and the performance of the device.
[0006] Also, as semiconductor devices are scaled down, the junction
depths of source/drain regions are also reduced. To reduce the
contact resistance of the source/drain regions, metal silicide can
again be used. At this time, a layer of metal silicide is generally
formed to a thickness of several hundred angstroms (.ANG.).
However, for example, when the metal silicide layer having a
thickness of 300 .ANG. is formed on the source/drain regions having
a thin junction depth of 1000 .ANG., the metal silicide layer may
be directly connected to the substrate beyond the source/drain
regions. Consequently, various problems, such as a junction spiking
phenomenon generating a leakage current, can occur. This junction
spiking phenomenon is similar to the spiking problem in which the
signal current leaks into the substrate when aluminum contact plugs
are connected to the source/drain regions.
[0007] Cobalt or titanium (Ti) metals, having a low contact
interface resistance such as are commonly used to form the metal
silicide layer. With cobalt, however, the probability of
encountering the junction spiking phenomenon is increased. The
cobalt silicide layer is usually formed by coating a cobalt layer
on the exposed surface of a substrate through sputtering.
Sputtering is followed by a two-step heat treatment, in which a
first step takes place at temperatures of 500 to 600.degree. C. and
a second step takes place at more than 750.degree. C., or a
one-step heat treatment that takes place at a high temperature of
more than 750.degree. C. The heat treatment silicifies the cobalt
layer. After the heat treatment, non-reacted portions of the cobalt
layer are removed in a self-aligned manner by wet etching. Using
this technique, it is difficult to control a speed of forming the
cobalt silicide layer to form a thin layer. When the cobalt
silicide layer is formed, the polysilicon layer and the cobalt
layer are usually combined in a ratio of 360 .ANG. to 100 .ANG.. It
is further difficult to coat the cobalt layer uniformly at a
thickness of less than 80 .ANG. through sputtering and to re-form
it repeatedly. The reliability of fabrication process is therefore
deteriorated. Thus, forming the cobalt silicide layer of less than
300 .ANG., as well as preventing the junction spiking phenomenon in
the source/drain regions having the thin conjunction depth, is
difficult.
[0008] When the signal current leaks into the substrate without
being transmitted through channels, the consumption of the signal
current is increased and the operation speed of transistors slows.
Worst yet, the transistors may not operate properly. Particularly,
in a low power SRAM device, it is necessary to prevent the
generation of leakage current to obtain reliable operation of the
device.
[0009] To prevent the spiking phenomenon that results from using
the cobalt silicide layer, a titanium silicide layer (TiSi.sub.2)
in the source/drain regions can be formed using titanium to reduce
the spiking phenomenon. In this case, however, because titanium
exhibits an amount of resistance that depends on the line width,
the resistance is abruptly increased in most semiconductor devices
having a line width of less than 0.2 .mu.m. Also, the resistance
characteristics of the titanium may be degraded following heat
treatment.
SUMMARY OF THE INVENTION
[0010] According to an aspect of the present invention, a
semiconductor device comprises a gate insulation layer formed on an
active region of a semiconductor substrate. A gate electrode is
formed on the gate insulation layer. An impurity region such as a
source/drain region is formed in the active region adjacent the
gate electrode. A silicide thin film is formed to a thickness of
less than approximately 200 .ANG. in the impurity region.
[0011] According to another aspect of the present invention, there
is provided a method of forming a semiconductor device comprising
forming an isolation layer on a surface of a substrate to define an
active region, forming at least one gate electrode by sequentially
forming a gate insulation layer and a gate layer on the surface of
the substrate in the active region and patterning them to expose
source/drain regions, forming a metal layer such as a cobalt layer
on the surface of the substrate in the exposed source/drain region,
forming a low temperature type silicide thin film such as a cobalt
silicide thin film by performing a heat treatment at a low
temperature of 150 to 450.degree. C., preferably 300 to 400.degree.
C. to the substrate on which the cobalt layer is formed, removing
non-reacted portions of the cobalt layer from the substrate on
which the low temperature type cobalt silicide thin film is formed,
and forming a high temperature type metal silicide thin film such
as a high temperature type cobalt silicide thin film by performing
a heat treatment at a high temperature of more than 700.degree. C.,
preferably 850.degree. C. to the low temperature type silicide thin
film.
[0012] In the invention, because the heat treatment after forming
the cobalt layer is carried out at a low temperature, it is
desirable that the low temperature type cobalt silicide thin film
be formed in an in-situ method in a sputtering device after the
sputtering. Also, instead of the cobalt layer, a layer of metal
such as nickel, titanium and platinum can be used.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The foregoing and other objects, features and advantages of
the invention will become more apparent from the following detailed
description of preferred embodiments thereof made with reference to
the attached drawings, of which:
[0014] FIG. 1 and FIG. 7 are flow diagrams showing various stages
of processing steps for forming a semiconductor device in
accordance with an embodiment of the present invention.
[0015] FIG. 8 to FIG. 11 are flow diagrams showing various stages
of processing steps for forming a semiconductor device in
accordance with another embodiment of the present invention.
[0016] FIG. 13 to FIG. 19 are flow diagrams showing various stages
of processing steps for forming a semiconductor device in
accordance with yet another embodiment of the present
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0017] The present invention now will be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred embodiments of the invention are shown. Like numbers
refer to like elements throughout.
[0018] FIG. 1 to FIG. 7 are flow diagrams showing various stages of
processing steps for forming a semiconductor device in accordance
with an embodiment of the present invention.
[0019] Referring now to FIG. 1, an isolation trench 11 is formed on
a semiconductor substrate 10 to define an active region therein. A
gate insulation layer is then formed on the semiconductor substrate
10 in the active region by thermal oxidation. Then, a polysilicon
layer 13, a tungsten silicide layer 15, and a silicon oxynitride
layer for forming an anti-reflection layer 17 are sequentially
deposited to form a gate structure by chemical vapor deposition
(CVD). The anti-reflection layer 17 may be a middle temperature
oxide (MTO) layer, a high temperature oxide (HTO) layer or a
silicon nitride layer instead of the silicon oxynitride layer. The
anti-reflection layer 17 lessens the reactions between the layers
disposed thereunder and a cobalt layer during the following
process, such as forming the cobalt layer or performing a heat
treatment at low temperatures. The tungsten silicide layer 15
reduces the resistance to the signal transmission of the gate
lines. The tungsten silicide layer 15 can be formed to a thickness
of several hundred angstroms .ANG. because it is formed separately
from a cobalt silicide layer to be later formed in source/drain
regions.
[0020] Referring to FIG. 2, the gate layer 13, 15, 17 is patterned
to form a gate pattern. That is, a photo-resist pattern is formed
on the gate layer 13, 15, 17 using conventional techniques. Then,
the exposed gate layer is etched to form a gate pattern using the
photo-resist pattern as an etch mask. To form spacers, a MTO layer
21 and a silicon nitride layer 23 are formed on the resulting
structure including the gate pattern by conventional techniques
such as CVD.
[0021] Referring to FIG. 3, the MTO layer 21 and the silicon
nitride layer 23 are anisotropically etched. As a result,
insulation spacers 25 are formed on sidewalls of the gate pattern.
At this time, an inner layer of the insulation spacers 25 adjacent
to the gate pattern is the MTO layer and an outer layer thereof is
the silicon nitride layer. Then, an ion implantation process is
carried out using the gate pattern and the spacers 25 as a mask to
form source/drain regions 27, 29 in the substrate 10. To form
source/drain regions 27, 29 having lightly-doped drain (LDD)
structures, the substrate 10 is lightly doped before forming the
spacers 25 and heavily doped after forming the spacers 25. As
semiconductor devices become highly integrated, the width of the
active region defined by the isolation layer 11 and the width and
the junction depth of the source/drain regions 27, 29 are also
reduced. In this embodiment, the junction depth is within a range
of 1000 to 1300 .ANG..
[0022] Referring to FIG. 4, a cobalt layer 31 is coated on the
resulting structure including the gate pattern and the source/drain
regions 27, 29. The coating of the cobalt layer 31 is generally
carried out by conventional techniques such as sputtering. A heat
treatment is then carried out at a low temperature of 300.degree.
C. to form a cobalt silicide thin film or layer 33. Since the heat
treatment can be carried out at a temperature of 150 to 450.degree.
C., it is desirable that the heat treatment be carried out in situ,
i.e., using a resistance-heating type heater in a sputtering device
to form the cobalt layer 31 without transferring the substrate into
a separate furnace. Also, the speed of forming the cobalt silicide
thin film 33 is within a range of ten to several tens of angstroms
.ANG. per minute at a temperature of 300.degree. C. regardless of
the thickness of the coated cobalt layer 31, so that a process time
for forming the cobalt silicide thin film 33 having a thickness of
less than 200 .ANG. can be decided by several to several tens of
minutes depending on temperature conditions. Thus, because the
thickness of the cobalt layer 31 to be formed is not limited to a
certain range, the process condition can be modified. Accordingly,
the thickness of the cobalt silicide thin film 33 can be controlled
in a unit of 10 .ANG.. At this time, the formed cobalt silicide
thin film 33 is a low temperature type thin layer that has chemical
formulas of Co.sub.2Si and CoSi.
[0023] Alternatively, the cobalt silicide thin film 33 can be
formed by maintaining a temperature of a sputtering chamber at 200
to 500.degree. C. while sputtering cobalt. At this time, a separate
silicification treatment can be skipped. The thickness of the
cobalt silicide layer 33 is controlled according to a sputtering
time.
[0024] Also, when a Ti/Ti-nitride layer as a capping layer is
formed by a CVD process after coating the cobalt layer, the cobalt
silicide thin film 33 can be formed without a separate heat
treatment. That is, because the CVD process is carried out at a
process temperature of 300 to 700.degree. C., the separate
silicification process can be skipped.
[0025] Referring to FIG. 5, non-reacted portions of the cobalt
layer 31 are removed by wet etching from the substrate on which the
cobalt silicide thin film 33 is formed by the low temperature heat
treatment. Using wet etching is beneficial to remove the cobalt
layer 31 because it has high etch selectivity and damages the
substrate 10 very little. Consequently, only the cobalt silicide
thin film 33 having a thickness of less than 200 .ANG. remains on
the surface of the substrate 10 in the source/drain regions 27,
29.
[0026] Referring to FIG. 6, a silicon oxynitride layer as a
subsidiary layer 35 is formed to a thickness of several hundred
angstroms .ANG. on the substrate 10 in which the cobalt silicide
layer 33 is formed.
[0027] Referring to FIG. 7, a heat treatment is carried out at a
high temperature of more than 700.degree. C., for example
850.degree. C. on the substrate 10 over which the subsidiary layer
35 is formed. As a result, the cobalt silicide layer 33 is
transformed into a high temperature type cobalt silicide thin film
43 that has a chemical formula of CoSi.sub.2, which enhances its
conductivity.
[0028] Alternatively, after the non-reacted portions of the cobalt
layer 31 are removed, a thin cobalt oxide layer (not shown) can be
formed on a surface of the low temperature type cobalt silicide
thin film 33. When the silicon oxynitride layer 35 is formed on the
thin cobalt oxide layer and the high temperature heat treatment is
carried out, the thin cobalt oxide layer provides oxygen to the
silicon oxynitride layer 35 and becomes the cobalt silicide layer.
Also, the silicon oxynitride layer 35 can limit a value of the
contact interface resistance obtained through the high temperature
heat treatment to a stable and narrow range. Accordingly, although
the silicon oxynitride layer 35 has a low etch selectivity compared
with the silicon nitride layer, but it can act as an etch stop
layer while forming contact holes.
[0029] FIG. 8 through FIG. 11 are flow diagrams showing various
stages of the processing for forming a semiconductor device in
accordance with another embodiment of the present invention. In the
second embodiment, duplicate explanations are omitted for
brevity.
[0030] Referring to FIG. 8, an isolation trench 11 is formed on a
substrate 10 to define an active region. A gate insulation layer is
then formed on the active region by thermal oxidation. A gate layer
is formed by sequentially depositing a polysilicon layer 13 and a
silicon oxynitride layer as an anti-reflection layer 17 by
conventional techniques such as CVD.
[0031] Referring to FIG. 9, the gate layer 13, 17 is patterned to
form a gate pattern. To form spacers, a MTO layer 21 and a silicon
nitride layer 23 are formed on the gate pattern using conventional
techniques such as CVD.
[0032] Referring to FIG. 10, the MTO layer 21 and the silicon
nitride layer 23 are etched anisotropically. As a result,
insulation spacers 251 are formed on sidewalls of the gate pattern.
At this time, an inner layer of the insulation spacers 251 adjacent
to the gate pattern is the MTO layer and an outer layer thereof is
the silicon nitride layer. Also, the anisotropic etching for
forming the spacers 251 is excessively carried out, i.e.,
over-etched. Accordingly, the anti-reflection layer 17 is removed
and the height of the spacers 251 is reduced enough to expose an
upper surface and upper portions of sidewalls of the gate pattern.
Preferably, the sidewalls of the gate pattern are exposed as much
as to a depth of 400 to 500 .ANG. from the upper surface
thereof.
[0033] Then, an ion implantation process is carried out using the
gate pattern and the spacers 251 as a mask. Consequently,
source/drain regions 27, 29 are formed.
[0034] Referring to FIG. 11, a cobalt layer 31 is coated on the
surface of the substrate 10 in which the source/drain regions 27,
29 are formed. A heat treatment is then carried out at a low
temperature of 300.degree. C.
[0035] Because the upper surface and the upper portions of the side
walls of the gate pattern were exposed, a cobalt silicide thin film
331 covering an upper part of the gate pattern and the cobalt
silicide thin film 33 covering the source/drain regions 27, 29 can
be formed. Thus, without performing a separate process to form a
metal silicide layer on the gate layer, the cobalt silicide thin
film 331 can be formed during this process, thereby reducing the
resistance of the gate line.
[0036] The cobalt silicide layer 33 of the source/drain regions 27,
29 is formed to a thickness of 50 to 150 .ANG.. If the cobalt
silicide layer 33 is too thin, the contact interface resistance and
the resistance in the source/drain regions 27, 29 are increased,
and if it is too thick, a spiking phenomenon is increased.
Particularly, when the thickness of the cobalt silicide layer 33 is
less than 150 .ANG., the leakage current through connecting
surfaces is markedly reduced. At this time, since the polysilicon
layer 13 of the gate layer has a structure different from a single
crystalline silicon layer of the substrate 10, the cobalt silicide
layer 331 forming the upper part of the gate pattern can be formed
to a thickness of more than 200 .ANG.. If the cobalt silicide layer
331 forms the upper part of the gate pattern, increasing the
thickness of the cobalt silicide layer 331 is desirable because the
resistance of the gate line and the delay of resistance capacitance
(RC) can be reduced.
[0037] Referring to FIG. 12, non-reacted portions of the cobalt
layer 31 are removed by wet etching from the substrate 10 over
which the low temperature type cobalt silicide layers 33, 331 are
formed by a low temperature heat treatment. A silicon oxynitride
layer as a subsidiary layer 35 is then formed over the low
temperature type cobalt silicide layers 33, 331. Next, a heat
treatment is carried out at a high temperature of 850.degree. C. to
the substrate 10 over which the subsidiary layer 35 is formed. As a
result, the cobalt silicide layers 33, 331 are transformed into
high temperature type cobalt silicide thin films 43, 431, which
have a chemical formula of CoSi.sub.2 and a relatively high
conductivity.
[0038] FIG. 13 through FIG. 19 are flow diagrams showing the
various states of processing steps for forming a semiconductor
device in accordance with yet another embodiment of the present
invention.
[0039] Referring to FIG. 13, an isolation trench 11 is formed on a
semiconductor substrate 10 to define an active region therein. A
gate insulation layer is then formed on the active region by
thermal oxidation. Then, a gate layer is formed by sequentially
depositing a polysilicon layer 13, a silicon nitride layer 14 and a
silicon oxynitride layer as an anti-reflection layer 17. Referring
to FIG. 14, the gate layer 13, 14, 17 is patterned to form a gate
pattern. To form spacers, a MTO layer 21 and a silicon nitride
layer 23 are formed over the surface of the substrate 10 by
CVD.
[0040] Referring to FIG. 15, the MTO layer 21 and the silicon
nitride layer 23 are etched anisotropically. As a result,
insulation spacers 251 are formed on sidewalls of the gate pattern.
At this time, an anisotropic etching process to form the spacers
251 is excessively carried out in order to expose the polysilicon
layer 13 of the gate pattern. Accordingly, the spacers 251 that
expose an upper part of the gate pattern are formed. Then, an ion
implantation process is carried out using the gate pattern and the
spacers 251 as a mask. Consequently, source/drain regions 27, 29
are formed. Then, a cobalt layer 31 is coated on the source/drain
regions 27, 29 by conventional techniques such as sputtering.
[0041] Referring to FIG. 16, a heat treatment is carried out at a
low temperature of 300.degree. C. to the substrate 10 over which
the cobalt layer 31 is formed. As a result, a low temperature type
cobalt silicide thin film 33 is formed in the source/drain regions
27, 29. Non-reacted portions of the cobalt layer 31 is then removed
from the substrate 10 by wet etching.
[0042] Referring to FIG. 17, a silicon nitride layer as an etch
stop layer 351 is formed over the whole surface of the substrate 10
on which the low temperature type cobalt silicide layer 33 is
formed A silicon oxide layer as an interlver insulation layer 352
is formed on the etch stop layer 351. The interlayer insulation
layer 352 is then planarized using planarizing techniques such as
chemical-mechanical polishing (CMP). An upper part of the gate
pattern and the etch stop layer 351 may be exposed as shown. At
this time, in a cell area of the semiconductor device in which the
density of the gate line is high, the interlayer insulation layer
352 in the active region is lightly etched, while in a peripheral
area of the semiconductor device in which the density of the gate
line is low, it is widely and deeply etched. Accordingly, the
interlayer insulation layer 352 remain thick in the cell area and
thin in the peripheral area. Thus, steps may be formed between the
cell and peripheral areas.
[0043] Referring to FIG. 18, the etch stop layer 351, the
anti-reflection layer 17 and the silicon nitride layer 14 forming
the upper part of the gate pattern, which project above the
planarized interlayer insulation layer 352, are removed by etching,
e.g., anisotropic etching until the polysilicon layer 13 is
exposed. At this time, in the peripheral area that the interlayer
insulation layer 352 thinly remains, the substrate 10 in the active
region can be damaged due to the anisotropic etching. However,
because the cobalt silicide layer was formed, the damage to the
substrate 10 and increase in the resistance can be reduced by
increasing the etch selectivity of the etch stop layer 351, the
anti-reflection layer 17 and the silicon nitride layer 14 during
the anisotropic etching. Also, the cobalt silicide layer 33 can
decrease the contact interface resistance and the resistance in the
source/drain regions 27, 29.
[0044] Referring to FIG. 19, a metal layer 311 such as a cobalt
layer is formed on the polysilicon layer 13 of the gate pattern
exposed by the anisotropic etching and then a heat treatment is
carried out. At this time, the low temperature type cobalt silicide
thin film 33 is transformed into a high temperature type cobalt
silicide thin film 43 having a high conductivity by the high
temperature heat treatment, and the thick metal silicide layer 432
is formed in the upper part of the polysilicon layer 13 of the gate
pattern. Since there is no spiking problem, it is preferable to
form a thick metal silicide layer 432.
[0045] Next, non-reacted portions of the metal layer are removed
through the wet etching.
[0046] As apparent from the foregoing description, the invention
can form the cobalt silicide thin film, the thick cobalt silicide
layer or other metal silicide layer in the gate pattern depending
on the applications. Also, with an embodiment of the invention, the
cobalt silicide thin film of less than 200 .ANG. can be formed in
the source/drain region, which do not generate the spiking problem.
Consequently, according to the invention, a semiconductor device
that has superior properties and does not generate the process
defect can be obtained.
[0047] In the drawings and specification, there have been disclosed
typical preferred embodiments of the invention and, although
specific terms are employed, they are used in a generic and
descriptive sense only and not for purpose of limitation, the scope
of the invention being set forth in the following claims.
* * * * *