Kwon; Hyung-Shin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kwon; Hyung-Shin.The latest application filed is for "semiconductor memory device, method of testing the same and method of operating the same".

Company Profile

1.20.23

Kwon; Hyung-Shin - Seongnam-si KR
KWON; Hyung-Shin - Gyeonggi-do KR
Kwon; Hyung Shin - Hwaseong-si N/A KR
Kwon; Hyung-Shin - Kyunggi-do KR
Kwon; Hyung-Shin - Osan-si KR
Kwon; Hyung-shin - Kyungki-do KR
Kwon; Hyung-Shin - Seoul KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor memory device, method of testing the same and method of operating the same Grant 10,431,320 - Kwon , et al. O	2019-10-01
Semiconductor Memory Device, Method Of Testing The Same And Method Of Operating The Same App 20170110203 - KWON; HYUNG-SHIN ; et al.	2017-04-20
Multiple well bias memory Grant 9,053,963 - Lee , et al. June 9, 2	2015-06-09
Semiconductor Memory Device, Method Of Testing The Same And Method Of Operating The Same App 20140241076 - KWON; Hyung-Shin ; et al.	2014-08-28
Multiple Well Bias Memory App 20140092680 - LEE; Chung-ki ; et al.	2014-04-03
Semiconductor device, method of adjusting load capacitance for the same, and semiconductor system including the same Grant 8,619,484 - Lim , et al. December 31, 2	2013-12-31
Semiconductor devices and methods of manufacturing the same Grant 8,558,347 - Kwon , et al. October 15, 2	2013-10-15
Semiconductor Devices And Methods of Manufacturing The Same App 20130175667 - Kwon; Hyung-Shin ; et al.	2013-07-11
Methods of manufacturing semiconductor devices Grant 8,415,225 - Kwon , et al. April 9, 2	2013-04-09
Semiconductor Device, Method Of Adjusting Load Capacitance For The Same, And Semiconductor System Including The Same App 20120063251 - LIM; Jong Hyoung ; et al.	2012-03-15
Methods Of Manufacturing Semiconductor Devices App 20120052648 - Kwon; Hyung-Shin ; et al.	2012-03-01
Method of improving gate resistance in a memory array Grant 7,696,048 - Kwon , et al. April 13, 2	2010-04-13
Semiconductor device having silicide thin film and method of forming the same Grant 7,385,260 - Kwon , et al. June 10, 2	2008-06-10
Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses Grant 7,348,231 - Kwon , et al. March 25, 2	2008-03-25
Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof Grant 7,312,144 - Cho , et al. December 25, 2	2007-12-25
Semiconductor Device Having Silicide Thin Film And Method Of Forming The Same App 20070293030 - KWON; Hyung-Shin ; et al.	2007-12-20
Semiconductor Device Having Silicide Thin Film And Method Of Forming The Same App 20070290280 - KWON; Hyung-Shin ; et al.	2007-12-20
Semiconductor Device Having Gate Insulating Layers With Differing Thicknesses App 20070069282 - Kwon; Hyung Shin ; et al.	2007-03-29
Semiconductor Device With Improved Gate Resistance And Method Of Its Manufacture App 20070037336 - KWON; Hyung-Shin ; et al.	2007-02-15
Method of fabricating a semiconductor device having an elevated source/drain Grant 7,172,944 - Kwon February 6, 2	2007-02-06
Methods of fabricating semiconductor devices having gate insulating layers with differing thicknesses Grant 7,151,031 - Kwon , et al. December 19, 2	2006-12-19
Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses and related devices App 20060148153 - Kwon; Hyung-Shin ; et al.	2006-07-06
Semiconductor device having elevated source/drain and method of fabricating the same App 20060079060 - Kwon; Hyung-Shin	2006-04-13
Semiconductor device having elevated source/drain Grant 7,002,223 - Kwon February 21, 2	2006-02-21
Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof App 20050029664 - Cho, Won-Seok ; et al.	2005-02-10
Methods for fabricating metal silicide structures using an etch stopping capping layer Grant 6,815,275 - Kwon , et al. November 9, 2	2004-11-09
Unitary interconnection structures integral with a dielectric layer Grant 6,806,180 - Cho , et al. October 19, 2	2004-10-19
Semiconductor device having silicide thin film and method of forming the same App 20040198032 - Kwon, Hyung-Shin ; et al.	2004-10-07
Semiconductor device having gate insulating layers with differing thicknesses and methods of fabricating the same App 20040173854 - Kwon, Hyung-Shin ; et al.	2004-09-09
Semiconductor device having silicide thin film and method of forming the same Grant 6,767,814 - Kwon , et al. July 27, 2	2004-07-27
Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof App 20040018725 - Cho, Won-Seok ; et al.	2004-01-29
Method for fabricating a MOS transistor using a self-aligned silicide technique Grant 6,635,539 - Kwon , et al. October 21, 2	2003-10-21
Methods for fabricating metal silicide structures using an etch stopping capping layer App 20030092228 - Kwon, Hyung-Shin ; et al.	2003-05-15
Method of forming a spacer Grant 6,551,887 - Kwon , et al. April 22, 2	2003-04-22
Method Of Forming A Spacer App 20030045061 - Kwon, Hyung-Shin ; et al.	2003-03-06
Semiconductor device having elevated source/drain and method of fabricating the same App 20030025163 - Kwon, Hyung-Shin	2003-02-06
Method for fabricating a MOS transistor using a self-aligned silicide technique App 20020197805 - Kwon, Hyung-Shin ; et al.	2002-12-26
Semiconductor device having silicide thin film and method of forming the same App 20020130372 - Kwon, Hyung-Shin ; et al.	2002-09-19

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.