U.S. patent application number 11/836215 was filed with the patent office on 2007-11-29 for like integrated circuit devices with different depth.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Habib Hichri, Kimberly A. Larsen, Helen L. Maynard, Kevin S. Petrarca.
Application Number | 20070273004 11/836215 |
Document ID | / |
Family ID | 37055921 |
Filed Date | 2007-11-29 |
United States Patent
Application |
20070273004 |
Kind Code |
A1 |
Hichri; Habib ; et
al. |
November 29, 2007 |
LIKE INTEGRATED CIRCUIT DEVICES WITH DIFFERENT DEPTH
Abstract
The invention forms integrated circuit devices of similar
structure and dissimilar depth, such as interconnects and
inductors, simultaneously. The invention deposits a conformal
polymer over an area on a substrate with vias and an area without
vias. Simultaneously, cavities are formed in the areas with and
without vias. The depth of the cavities formed in the areas with
vias will extend deeper into the substrate than the cavities formed
in areas without vias. Such occurs because the polymer deposits
unevenly along the surface of the substrate and more specifically,
more thinly in areas with underlying depressions. Once filled with
a conductive material, cavities which extend more deeply into the
substrate, which were formed in areas with vias, become inductors,
and the cavities which extend less deeply into the substrate, which
were formed in areas without vias, become interconnects.
Inventors: |
Hichri; Habib;
(Poughkeepsie, NY) ; Larsen; Kimberly A.;
(Poughkeepsie, NY) ; Maynard; Helen L.; (Hopewell
Junction, NY) ; Petrarca; Kevin S.; (Newburgh,
NY) |
Correspondence
Address: |
INTERNATIONAL BUSINESS MACHINES CORPORATION;DEPT. 18G
BLDG. 300-482
2070 ROUTE 52
HOPEWELL JUNCTION
NY
12533
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
10504
|
Family ID: |
37055921 |
Appl. No.: |
11/836215 |
Filed: |
August 9, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11162766 |
Sep 22, 2005 |
7279426 |
|
|
11836215 |
Aug 9, 2007 |
|
|
|
Current U.S.
Class: |
257/531 ;
257/E21.022; 257/E21.233; 257/E21.259; 257/E23.142;
257/E29.001 |
Current CPC
Class: |
H01L 21/02282 20130101;
H01L 28/10 20130101; H01L 21/3083 20130101; H01L 23/5227 20130101;
H01L 21/76816 20130101; H01L 21/02118 20130101; H01L 2924/00
20130101; H01L 2924/0002 20130101; H01F 41/041 20130101; H01L
2924/0002 20130101; H01L 23/522 20130101; H01L 21/312 20130101 |
Class at
Publication: |
257/531 ;
257/E29.001 |
International
Class: |
H01L 29/00 20060101
H01L029/00 |
Claims
1-7. (canceled)
8. An integrated circuit, comprising: a substrate having an area
with a depression and an area absent said depression; a planarizing
polymer deposited over said area with said depression and said area
absent said depression, said polymer having a depth differential
between said area with said depression and said area absent said
depression, said polymer thicker in said area absent said
depression than said area with said depression; at least two
cavities formed through said polymer, one cavity formed in said
area with said depression and another cavity formed in said area
absent said depression, said cavity formed in said area with said
depression extends deeper into said substrate than said cavity
formed in said area absent said depression by said depth
differential of said polymer.
9. An integrated circuit as in claim 8, said depression is a
via.
10. An integrated circuit as in claim 8, said deposited polymer is
25.0-45.0% thinner over said area with said depression than said
area absent said depression.
11. An integrated circuit as in claim 8, further comprising: a
conductive material that fills said cavity formed in said area with
said depression and said cavity formed in said area absent said
depression.
12. An integrated circuit as in claim 11, said cavity filled with
conductive material in said area with said depression is an
inductor.
Description
[0001] This application claims the benefit of application Ser. No.
11/162,766 filed Sep. 22, 2005 under 35 U.S.C. .sctn.121.
FIELD OF THE INVENTION
[0002] The invention relates generally to semiconductor
manufacturing and more particularly to integrated circuit devices
with similar structure and dissimilar depth.
DESCRIPTION OF THE RELATED ART
[0003] In semiconductor manufacturing, integrated circuit devices
are formed in multiple process steps. Each eliminated process step
reduces manufacture time, saves costs, and expedites time to
market. Therefore, step reduction is an important asset in the
semiconductor industry.
[0004] Integrated circuit devices with similar structure and depth
in the same layer of the integrated circuit can be formed in one
step, which advantageously reduces manufacture steps. One problem
encountered in semiconductor manufacturing, however, is the
manufacture of integrated circuit devices of similar structure but
dissimilar depth. Currently, such structures are formed separately,
which increases manufacture time, cost, and delays time to
market.
[0005] Integrated circuit devices with similar structure but
dissimilar depth in the same layer of the integrated circuit cannot
be formed in one step with prior art methods. Such devices include
passive devices and interconnects. Passive devices, which are
frequently used in radio frequency devices, such as cell phones,
pagers, personal digital assistants, and global positioning
systems, are deeper than interconnects because with depth,
performance of the passive device improves. The performance of the
passive device improves because the cross sectional area of the
passive device increases, which in turn decreases resistance in the
passive device. By contrast, interconnect performance diminishes
with depth. The performance of an interconnect diminishes because
capacitance increases if the distance between other interconnects
in the same layer remains constant. Therefore, there remains a need
for the manufacture of integrated circuit devices of similar
structure but dissimilar depth, such as interconnects and
inductors, in one step.
[0006] What is needed in the art is an improved method for
manufacturing integrated circuit devices with similar structure and
dissimilar depth, such as interconnects and inductors, that does
not require separate process steps.
BRIEF SUMMARY OF THE INVENTION
[0007] The claimed invention is directed to a method for
simultaneously forming two cavities of different depth. The method
comprises the steps of depositing and forming. A planarizing
polymer is deposited on a semiconductor substrate over an area on
the substrate with a depression and an area on the substrate absent
the depression. The polymer has a depth differential between the
area with the depression and the area absent the depression. The
polymer is thicker in the area absent the depression than the area
with the depression. A cavity in the polymer is simultaneously
formed in the area absent the depression and in the area with the
depression for a predetermined amount of time. After the
predetermined amount of time, the cavity in the area with the
depression is deeper than the cavity in the area absent the
depression by substantially the depth differential of the
polymer.
[0008] The claimed invention is directed to an integrated circuit.
The integrated circuit comprises a substrate, a planarizing
polymer, and at least two cavities. The substrate has an area with
a depression and an area absent a depression. The planarizing
polymer is deposited over the area with the depression and the area
absent the depression. The polymer has a depth differential between
the area with the depression and the area absent the depression.
The polymer is thicker in the area absent the depression than the
area with the depression. At least two cavities are formed through
the polymer. One cavity is formed in the area with the depression
and another cavity is formed in the area absent the depression. The
cavity formed in the area with the depression extends deeper into
the substrate than the cavity formed in the area absent the
depression by the depth differential of the polymer.
[0009] The present invention manufactures integrated circuit
devices of similar structure and dissimilar depth in one process
step. The present invention requires no modification to existing
semiconductor manufacturing processes. Devices with similar
structure, but dissimilar depth may be created in one step.
Therefore, the present invention reduces manufacture time, saves
costs, and expedites time to market.
[0010] For at least the foregoing reasons, the invention improves
upon semiconductor manufacturing.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The features and the element characteristics of the
invention are set forth with particularity in the appended claims.
The figures are for illustrative purposes only and are not drawn to
scale. Furthermore, like numbers represent like features in the
drawings. The invention itself, however, both as to organization
and method of operation, may best be understood by reference to the
detailed description which follows, taken in conjunction with the
accompanying figures, in which:
[0012] FIGS. 1a-1c depict a method of an embodiment of the present
invention; and,
[0013] FIG. 2 depicts a method of an embodiment of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0014] The invention will now be described with reference to the
accompanying figures. In the figures, various aspects of the
structures have been shown and schematically represented in a
simplified manner to more clearly describe and illustrate the
invention.
[0015] By way of overview and introduction an embodiment of the
present invention comprises the steps of depositing a planarizing
polymer and forming a first and second cavity through the polymer.
A planarizing polymer is deposited over an area on a semiconductor
substrate that includes areas with and without depressions. The
polymer deposits unevenly on the surface of the substrate. More
specifically, the polymer deposits more thickly in the area without
depressions than the area with depressions. The difference between
the thickness of the polymer over the areas with depressions versus
the areas without depression will be referred to as the thickness
differential. At the same time, a first cavity is formed in the
area with depressions and a second cavity is formed in the area
without depressions. The cavities are formed under a timed etch,
such as reactive ion etch and or wet etch post litho exposure. The
formation of the cavity can be formed, but is not limited to,
reactive ion etch and it should be clear to any skilled in the art
that any other method could be considered. Therefore, with respect
to each other the cavities have the same depth. However, the cavity
formed in the area with the depression will extend deeper into the
substrate than the cavity formed in the area without the
depression. The cavity formed in the area with the depression will
extend deeper into the substrate by a depth equivalent to the
thickness differential of the polymer.
[0016] A further embodiment of the present invention comprises an
integrated circuit having a substrate, a planarizing polymer, and
at least two cavities. The substrate has an area with a depression
and an area absent the depression. The planarizing polymer is
deposited over the areas with and without the depression. However,
the polymer will have a thickness differential between the polymer
deposited on the area with the depression and the area without the
depression. At least two cavities are formed in the polymer. Once
cavity is formed in an area without depression and a second cavity
is formed in an area with depression. The cavities will be equally
deep with respect to each other, but the cavity formed over the
area with the depression will extend deeper into the substrate by a
depth roughly equivalent to the thickness differential. This
relatively equivalent depth can be adjusted by varying of the etch
chemistries and power used, this would be obvious to one that is
skilled in the art.
[0017] FIGS. 1a-c depict a method of an embodiment of the present
invention. FIG. 1a shows an integrated circuit with substrate 110
having areas with depressions 120 and areas without a depression
130. FIG. 1b depicts a substrate 110 with a planarizing polymer 140
deposited over the areas with and without depressions respectively.
As shown, the polymer 140 is thinner in areas over depressions 150.
Two cavities are formed through the planarizing polymer 140 in FIG.
1c. Cavities 170a,b are formed through the polymer in the area with
the depressions 120 and in the area without the depression 130. The
depth of the cavities 170a,b is unequal. As shown in FIG. 1c, the
cavity 170a, which is formed over the area with depressions, is
deeper than the cavity 170b, which is formed over the area without
depressions. The depth differential 180 is shown in FIG. 1c. The
cavities are simultaneously formed by lithography and reactive ion
etch. FIG. 1c depicts the photo resist 160 used in lithography and
reactive ion etch steps. Thereafter, the cavities are filled with a
conductive metal by physical vapor deposition, chemical vapor
deposition, sputtering, plating, or any combination of the same.
Once filled with conductive metal, the cavities 170a becomes an
inductor and cavity 170b becomes an interconnect. In so doing, such
embodiment of the present invention creates devices of similar
structure, simultaneously.
[0018] FIG. 2 depicts a method of an embodiment of the present
invention. FIG. 2 depicts the steps of depositing and forming. The
step of depositing a polymer 192 includes depositing a planarizing
polymer over a substrate that has areas with and without
depressions. The forming step 194 includes forming a cavity in the
polymer over an area without depressions and a cavity in the
polymer over an area with depressions, simultaneously, for a
predetermined amount of time. Because polymer is deposited
unevenly, and more specifically, thinner in areas with depressions,
the depth of the cavity, which is formed over an area with
depressions, extends deeper into the substrate than the depth of
the cavity formed over the area without depressions. An area with
depressions is an area with vias.
[0019] While not depicted in FIG. 2, once the two cavities are
formed, the final step towards creation of the integrated circuit
devices includes filling the cavities with conductive material.
Once filled, the cavity that extends less deeply into the substrate
becomes an interconnect and the cavity that extends more deeply
into the substrate becomes an inductor. It is well known that
resistance is inversely proportional to the cross sectional area of
a conductor. Therefore, inductor performance improves with an
increase to the cross sectional area of the conductive material,
which explains the necessity for a deeper extension of the cavity
into the substrate for the inductor as compared with the less deep
extension of the cavity into the substrate for the
interconnect.
[0020] The claimed invention capitalizes on the understanding that
the polymer deposits more thinly on the areas with depressions.
Cavities formed over areas with depressions will extend more deeply
into the underlying substrate. It is a desirable feature for some
devices, such as inductors, to extend more deeply into the
substrate, then other devices such as interconnects. The claimed
invention, in one step, enables the simultaneous creation of
interconnects and inductors, which have a similar shape, but
dissimilar depth into the substrate, by capitalization on the
understanding that a planarizing polymer is thinner when deposited
over an area with a depression.
[0021] The claimed invention was successfully implemented on a 300
mm wafer with embedded devices that varied in width from 0.09 to
1.0 micron. It was discovered that a thinner planarizing film was
created, if a planarizing polymer was deposited over areas with
depressions, such as vias. It was discovered that the planarizing
film over areas with depressions was between 25-40% thinner than
over areas without depressions. For example, if the planarizing
film had a target thickness of 3000 Angstroms over areas without
depressions, it was discovered that the planarizing film had a
thickness of 2250-1800 Angstroms over areas with depressions. It
was further discovered that areas with depressions could be
strategically placed in areas for subsequent placement of deep
structures, such as inductors. To create structures, such as
interconnects and inductors, the combination of lithography and
reactive ion etch ("RIE") is performed. RIE step must etch away
750-1200 Angstroms more planarizing film in areas without
depressions. Thus, the devices etched in areas with depressions
will be between 750-1200 Angstroms deeper than devices etched in
areas without depressions. Therefore, it was discovered that areas
with depressions could be strategically placed wherever deep
devices, such as inductors, would be subsequently required.
[0022] The planarizing film created in accordance with the
successful implementation of the claimed invention described above
was created as follows. A polymer was used that has conformal
properties at low spin speeds and planarizing properties at higher
spin speeds. An exemplary polymer includes, but is not limited to,
NFC 1400 from JSR. An exemplary low spin speed includes, but is not
limited to, 500-800 revolutions per minute (rpms), while an
exemplary high spin speed includes, but is not limited to, 900-2300
rpms. First, a solvent that is compatible with the polymer such as,
but not limited to PGMEA, was deposited on the semiconductor
substrate at a spin speed of 1000 rpms for less than 0.5 seconds.
Then the polymer was deposited on the solvent at a spin speed of
2500 rpms for approximately 2.50 seconds to disperse the solvent.
The spin speed was then reduced to 100 rpms for one second in an
effort to conserve the planarizing polymer. The thickness of the
polymer was then created by casting a spin speed of 900-2300 rpms
for 30.0 seconds. Finally, the planarizing polymer is cured at a
minimum temperature of 170.0.degree. C. in order to create a stable
film.
[0023] While the invention has been particularly described in
conjunction with a specific preferred embodiment and other
alternative embodiments, it is evident that numerous alternatives,
modifications and variations will be apparent to those skilled in
the art in light of the foregoing description. It is therefore
intended that the appended claims embrace all such alternatives,
modifications and variations as falling within the true scope and
spirit of the invention.
* * * * *