U.S. patent application number 11/436251 was filed with the patent office on 2007-11-22 for symmetrical mimcap capacitor design.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Choongyeun Cho, Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski.
Application Number | 20070267733 11/436251 |
Document ID | / |
Family ID | 38255410 |
Filed Date | 2007-11-22 |
United States Patent
Application |
20070267733 |
Kind Code |
A1 |
Cho; Choongyeun ; et
al. |
November 22, 2007 |
Symmetrical MIMCAP capacitor design
Abstract
Semiconductor chip capacitance circuits and methods are provided
comprising at least two capacitors mounted close to a substrate,
wherein each capacitor has a lateral lower conductive plate mounted
near enough to the substrate to have extrinsic capacitance greater
than an upper plate extrinsic capacitance. One half of lower plates
and one half of upper plates are connected to a first port, and a
remaining one half of upper plates and lower plates are connected
to a second port, the first and second port having about equal
extrinsic capacitance from the lower plates. In one aspect, the
substrate comprises a front-end-of-line capacitor defining a
substrate footprint, and the at least two capacitors are
back-end-of-line Metal-Insulator-Metal Capacitors disposed above
the footprint. In another aspect, the at least two capacitors are
at least four capacitors arrayed in a rectangular array generally
parallel to the substrate.
Inventors: |
Cho; Choongyeun; (Hopewell
Junction, NY) ; Kim; Jonghae; (Fishkill, NY) ;
Kim; Moon J.; (Wappingers Falls, NY) ; Plouchart;
Jean-Olivier; (New York, NY) ; Trzcinski; Robert
E.; (Rhinebeck, NY) |
Correspondence
Address: |
DRIGGS, HOGG & FRY CO. L.P.A.
38500 CHARDON ROAD
DEPT. IEN
WILLOUGHBY HILLS
OH
44094
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
38255410 |
Appl. No.: |
11/436251 |
Filed: |
May 18, 2006 |
Current U.S.
Class: |
257/684 ;
257/E27.048; 257/E29.345 |
Current CPC
Class: |
H01L 27/0805 20130101;
H01L 29/94 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; H01L 23/5223 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/684 |
International
Class: |
H01L 23/06 20060101
H01L023/06 |
Claims
1. A capacitance circuit assembly mounted on a semiconductor chip
comprising: a chip substrate; at least two capacitors mounted close
to the substrate; wherein each capacitor has first and second
conductive plates separated by a dielectric material; wherein each
second conductive plate is mounted flat near enough to said
substrate to have a second plate extrinsic capacitance with said
substrate greater than an extrinsic capacitance of each first
conductive plate; one half of said first plates and one half of
said second plates connected to a first port by a first port
circuitry, wherein the first port has a first port composite
extrinsic capacitance from the one half of said second plates; and
a remaining one half of said first plates and a remaining one half
of said second plates connected to a second port by a second port
circuitry, wherein the second port has a second port composite
extrinsic capacitance from the remaining one half of said second
plates, the second port composite extrinsic capacitance about equal
to the first port composite extrinsic capacitance.
2. The structure of claim 1 wherein the at least two capacitors are
Metal-Insulator-Metal Capacitors, and the capacitance circuit
assembly is located in a back-end-of-line semiconductor capacitor
circuit.
3. The structure of claim 2, wherein the substrate further
comprises a front-end-of-line capacitor with first and second
terminals, the front-end-of-line capacitor defining a substrate
footprint; wherein the first port is electrically connected to the
front-end-of-line capacitor structure first terminal and the second
port is electrically connected to the front-end-of-line capacitor
structure second terminal; and wherein the at least two capacitors
are disposed above the substrate within the front-end-of-line
capacitor footprint.
4. The structure of claim 3 wherein the at least two capacitors are
at least four capacitors.
5. The structure of claim 4 wherein the at least four capacitors
are arrayed in a rectangular array generally parallel to the
substrate.
6. The structure of claim 3, further comprising a Vertical Native
Capacitor disposed above the substrate within the front-end-of-line
capacitor footprint and having first and second terminals, and
wherein the first port is electrically connected to the Vertical
Native Capacitor first terminal and the second port is electrically
connected to the Vertical Native Capacitor second terminal.
7. The structure of claim 1 wherein each of the first and second
plates are formed of the same material.
8. The structure of claim 7 wherein the plates are a metal or
polysilicon.
9. The structure of claim 7 wherein the dielectric material has a
permeability value greater than about 4 (er >4).
10. A method for forming a semiconductor chip capacitance circuit,
comprising the steps of: forming a front end of line substrate
structure; mounting at least two capacitors close to the substrate,
wherein each capacitor has first and second conductive plates
separated by a dielectric material, and wherein each second
conductive plate is mounted flat near enough to said substrate to
have a second plate extrinsic capacitance with said substrate
greater than an extrinsic capacitance of each first conductive
plate; connecting one half of said first plates and one half of
said second plates to a first port by a first port circuitry,
wherein the first port has a first port composite extrinsic
capacitance from the one half of said second plates; and connecting
a remaining one half of said first plates and a remaining one half
of said second plates to a second port by a second port circuitry,
wherein the second port has a second port composite extrinsic
capacitance from the remaining one half of said second plates, the
second port composite extrinsic capacitance about equal to the
first port composite extrinsic capacitance.
11. The method of claim 10 wherein the at least two capacitors are
Metal-Insulator-Metal Capacitors, further comprising the step of
locating the at least two capacitors in a back-end-of-line
semiconductor capacitor circuit.
12. The method of claim 11, further comprising the steps of:
providing a front-end-of-line capacitor with first and second
terminals in the substrate; the front-end-of-line capacitor
defining a substrate footprint; connecting the first port
electrically to the front-end-of-line capacitor structure first
terminal; connecting the second port electrically to the
front-end-of-line capacitor structure second terminal; and
disposing the at least two capacitors above the substrate within
the front-end-of-line capacitor footprint.
13. The method of claim 12 wherein the at least two capacitors are
at least four capacitors.
14. The method of claim 13, further comprising the step of
disposing the at least four capacitors in a rectangular array
generally parallel to the substrate.
15. The method of claim 12, further comprising the steps of:
disposing a Vertical Native Capacitor above the substrate within
the front-end-of-line capacitor footprint, the Vertical Native
Capacitor having first and second terminals; connecting the first
port electrically to the Vertical Native Capacitor first terminal;
and connecting the second port electrically to the Vertical Native
Capacitor second terminal.
16. The method of claim 10 wherein each of the first and second
plates are formed of the same material.
17. The method of claim 16 wherein the plates are a metal or
polysilicon.
18. The method of claim 16 wherein the dielectric material has a
permeability value greater than about 4 (er >4).
19. A semiconductor circuit structure comprising: a chip substrate
comprising a front-end-of-line metal oxide silicon capacitor with
first and second terminals, the metal oxide silicon capacitor
defining a front-end-of-line capacitor footprint; at least two
back-end-of-line Metal-Insulator-Metal Capacitors electrically
connected to the front-end-of-line capacitor structure and mounted
close to the substrate and above the front-end-of-line capacitor
footprint, wherein Metal-Insulator-Metal bottom conductive plates
are mounted flat near enough to said substrate to have a bottom
plate extrinsic capacitances with said substrate greater than
Metal-Insulator-Metal top conductive plate extrinsic capacitances;
one half of said top plates and one half of said bottom plates
connected to a first port by a first port circuitry, wherein the
first port has a first port composite extrinsic capacitance from
the one half of said bottom plates; and a remaining one half of
said top plates and a remaining one half of said bottom plates
connected to a second port by a second port circuitry, wherein the
second port has a second port composite extrinsic capacitance from
the remaining one half of said bottom plates, the second port
composite extrinsic capacitance about equal to the first port
composite extrinsic capacitance.
Description
TECHNICAL FIELD
[0001] This invention relates generally to capacitors and, more
particularly, to the methods and systems for capacitor structures
with symmetrical polarity characteristics.
BACKGROUND ART
[0002] On-chip capacitors are critical components of integrated
circuits that are fabricated on silicon semiconductors. These
capacitors are used for a variety of purposes: illustrative
examples include bypass and capacitive matching as well as coupling
and decoupling. The design and implementation of capacitor
structures on silicon semiconductor chips may be dependent upon one
or more symmetrical structural, target circuit quality and low
parasitic resistance performance characteristics.
[0003] More particularly, capacitor structures may be categorized
as being formed in one of two regions: the Front End Of
(production) Line (FEOL), or the Back End Of the Line (BEOL). In
integrated-circuit fabrication lines, FEOL conventionally refers to
earlier process stages that directly modify the semiconductor
substrate or the immediate contacts to it; for example, dopant
diffusion and implantation, sputtering of gate films, oxidations,
and the patterning steps associated with these. In
contradistinction, the BEOL is metalization (PVD) for interconnects
and vias (vertical interconnects between planar interconnects) and
associated non-conducting depositions and growths (for example,
polymers, glasses, oxides, nitrides, and oxinitrides) for
electrical isolation, dielectrics (for capacitance), diffusion
barriers, and mechanical passivation (in particular, to prevent
failure of interconnects by electromigration and stress migration).
FEOL and BEOL are used in transferred sense to refer to the levels
of an IC fabricated in the corresponding stages. BEOL is the
metalization layers (say between four and ten) and associated
insulating layers, and FEOL everything below that--mostly
transistors.
[0004] It is known to use a metal oxide silicon (MOS) capacitor, or
MOSCAP, for semiconductor chip capacitor elements formed on the
chip substrate in the FEOL. However, MOSCAP capacitors generally
require large chip area footprints in integrated circuits (IC).
Accordingly, design requirements typically result in requiring
large semiconductor chip footprint areas or real estate for MOSCAP
capacitor structures relative to their circuit capacitance
properties, resulting in high production costs and reduced
semiconductor chip area availability for other circuit structures.
Moreover, current leakage during a semiconductor circuit's idle
mode is known to result in increased power consumption. Silicon
semiconductor chip capacitor structures thus usually require large
MOSCAP capacitor structures in order to avoid current leakage
problems.
[0005] As the production cost of an IC is generally proportional to
the real estate required, it is desired to reduce IC chip costs by
reducing the footprint required for a MOSCAP structure.
Accordingly, one possible technique for reducing FEOL MOSCAP
footprints is to form additional capacitor structures in the BEOL
in circuit communication with the FEOL MOSCAP, preferably
increasing the capacitance of the total FEOL/BEOL capacitor
structure while resulting in a relatively smaller FEOL MOSCAP
footprint.
[0006] Two types of capacitors commonly utilized in the BEOL are a
Metal-Insulator-Metal Capacitor (MIMCAP) 100 schematically
illustrated in FIG. 1 with respect to a chip substrate 114, and a
Vertical Native Capacitor (VNCAP) 200 schematically illustrated in
FIG. 2. (FEOL structures are omitted for simplicity of
illustration.) The MIMCAP 100 comprises a first plate 110 and a
second plate 112, each having a connector or port 116, 118,
respectively, with a dielectric material 120 placed between the
plates 110, 112 to complete the capacitive structure. The VNCAP 200
also comprises a first plate 210 and a second plate 212, each
having a connector or port 216, 218, respectively, with a
dielectric material 220 placed between the plates 210, 212 to
complete the capacitive structure. What is significant is that the
lateral arrangement of the MIMCAP 100 plates 110, 112 above the
substrate footprint 130 results in asymmetrical parasitic
capacitances of the respective plates 110, 112, whereas the
vertical arrangement of the generally parallel VNCAP 200 plates
210, 212, projecting parallel plate footprints 230, 232,
respectively, results in symmetrical parasitic plate 210, 212
capacitance properties.
[0007] The MIMCAP 100 and VNCAP 200 each offer distinctive circuit
behaviors and, in some BEOL applications, combinations of one or
more MIMCAP's 100 with one or more VNCAP's 200 may be preferred.
However, the asymmetrical parasitic capacitances of the MIMCAP 100
plates 110, 112 produce a polarity for the port terminals 116, 118.
In one respect, a circuit using port 116 as an input port and port
118 as an output port results in different equivalent circuit
behavior. In another respect, the polarity difference may render
the MIMCAP 100 a unidirectional device. And incorrect polarity
usage may cause circuit performance degradation. Accounting for
such polarity issues results in circuit design inefficiencies as
additional design time must be expended to distinguish between
input and output polarities.
[0008] In many instances, multiple MIMCAPS capacitors are required
on a single chip substrate, with each having the same intrinsic
capacitance value. In configurations wherein the capacitors are
close to the substrate, the variable extrinsic capacitances between
the bottom plates closest to the substrate cannot be adequately
controlled for in circuit design, as the value of the extrinsic
capacitances may not be precisely predicted. Therefore, in
conventional prior art practices wherein all of the plates closest
to the substrate are connected together, and all of the plates
farthest from the substrate are connected together, divergent
capacitance values are effectively created in the otherwise
individually equivalent capacitors.
[0009] Additional problems arise for high-density on-chip BEOL
capacitor structures incorporating both MIMCAP's 100 and VNCAP's
200, since parallel connections between the VNCAP 200 and MIMCAP
100 components must be provided to accommodate the divergent
polarities of the port terminals 116, 118, and forming such
parallel connections presents structural limitations on the
resultant composite MIMCAP 100/VNCAP 200 BEOL structure that
diminishes possible chip real estate efficiencies. It also presents
other difficulties in providing a symmetrical BEOL capacitor
structure created from multiple VNCAP's and MIMCAP's.
[0010] What is needed is a system and method for enabling the
efficient incorporation of lateral MIMCAP capacitors in BEOL
applications. Accordingly, it is necessary to develop a technique
to provide each of a plurality of MIMCAP capacitors on a substrate
with symmetry with respect to the substrate.
SUMMARY OF THE INVENTION
[0011] In one aspect, a capacitance circuit assembly mounted on a
semiconductor chip, and methods for making the same, are provided
comprising at least two capacitors mounted close to a substrate,
wherein each capacitor has a lateral lower conductive plate mounted
near enough to the substrate to have extrinsic capacitance greater
than an upper plate extrinsic capacitance. One half of lower plates
and one half of upper plates are connected to a first port, and a
remaining one half of upper plates and lower plates are connected
to a second port, the first and second port having about equal
extrinsic capacitance from the lower plates.
[0012] In another aspect, the at least two capacitors are
Metal-Insulator-Metal Capacitors, and the capacitance circuit
assembly is located in a back-end-of-line semiconductor capacitor
circuit.
[0013] In another aspect, the substrate further comprises a
front-end-of-line capacitor defining a substrate footprint, and the
at least two capacitors are electrically connected to the
front-end-of-line capacitor and disposed above the substrate within
the front-end-of-line capacitor footprint.
[0014] In another aspect, the at least two capacitors are at least
four capacitors. In a further aspect, the at least four capacitors
are arrayed in a rectangular array generally parallel to the
substrate.
[0015] In another aspect, a Vertical Native Capacitor is
electrically connected to at least two capacitors and disposed
above the substrate within the front-end-of-line capacitor
footprint.
[0016] In another aspect, the first and second plates are formed of
the same material. In a further aspect, the plates are a metal or
polysilicon, and/or the dielectric material has a permeability
value greater than about 4 (er >4).
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIGS. 1 and 2 are schematic perspective depictions of two
techniques for mounting capacitors on a substrate;
[0018] FIG. 3 depicts a schematic perspective of a MIM capacitor in
relation to a substrate;
[0019] FIG. 4 depicts a schematic perspective of a conventional
prior art connection of two MIM capacitors relative to a
substrate;
[0020] FIG. 5 depicts a schematic perspective of a connection of
two MIM capacitors relative to a substrate according to this
invention;
[0021] FIG. 6 depicts a schematic perspective of a conventional
prior art connection of four MIM capacitors relative to a
substrate;
[0022] FIG. 7 depicts a schematic perspective of a connection of
four MIM capacitors relative to a substrate according to this
invention.
[0023] FIG. 8 is perspective view of a VNCAP element;
[0024] FIG. 9 depicts a schematic perspective of a connection of
two MIM capacitors to a VNCAP according to this invention;
[0025] FIG. 10 depicts a schematic perspective of a conventional
prior art connection of four MIM capacitors relative to a
substrate; and
[0026] FIG. 11 depicts a top plan view of a symmetrical capacitor
structure relative to a substrate according to this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0027] FIG. 3 illustrates an example of a single asymmetrical BEOL
MIMCAP 300 appropriate for use with the present invention, having a
top plate 310 and a bottom plate 320 arrayed laterally with respect
to a substrate 314 and having connectors or ports 316, 318,
respectively. A dielectric material 315 placed between the plates
310, 320 completes a capacitive structure in a lateral plate
arrangement with respect to a FEOL substrate 314. (Other FEOL
structures are omitted for simplicity of illustration.)
[0028] The substrate 314 conventionally is formed of silicon which
is dielectric. Preferably, the dielectric material 315 has a
permeability value greater than about 4 (er >4). It is to be
understood that the plates 310, 320 can be formed of the same
material, e.g. polysilicon or copper or other conductive material,
or different materials which can be used conventionally for
capacitors, depending upon the need and processes.
[0029] The two conductive capacitive plates 310, 320 are mounted
close enough to the substrate 314 to have an extrinsic or parasitic
capacitance, represented diagrammatically by the extrinsic
capacitance values 324, 322, respectively. The extrinsic capacitive
values 322 between bottom plate 320 and substrate 314 defined
within bottom plate footprint 340 are greater than the extrinsic
capacitive values 324 between plate 310 and substrate 314 defined
within top plate footprint 350, this difference resulting in
differing port 316, 318 polarities as described above.
[0030] Referring now to FIG. 4, a pair of MIMCAP's 408, 409 are
shown in a conventional parallel circuit structure 400 between two
port terminals, wherein PORT 1 410 is connected to the bottom
plates 432, 434 at connectors 402, 403, respectively; and PORT 2
420 is connected to the top plates 442, 444 at connectors 405, 406,
respectively. The bottom plates 432, 434 form parasitic extrinsic
capacitors 452, 454, respectively, with a FEOL substrate disposed
below (not shown for clarity of illustration, but as described
above with respect to FIGS. 1 and 3). As the schematic
representation of FIG. 4(b) illustrates, the parallel circuit
structure 400 is asymmetrical as both of the parasitic extrinsic
capacitors 452, 454 are accordingly connected to PORT 1 410, and no
parasitic extrinsic capacitors are connected to PORT 2 420.
[0031] In one aspect, a symmetrical multi-MIMCAP capacitor design
is provided that eliminates the extrinsic/parasitic capacitance
differences of individual asymmetrical MIMCAP's between their
laterally-oriented top and bottom plates with respect to a FEOL
chip substrate. For example, FIG. 5 illustrates the pair of
MIMCAP's 408, 409 in a novel cross-coupled parallel circuit
structure 500 between the two port terminals, wherein PORT 1 410 is
connected to the MIMCAP 408 bottom plate 432 at connector 512 and
to the MIMCAP 409 top plate 444 at connector 513; and PORT 2 420 is
connected to the MIMCAP 408 top plate 442 at connector 515 and to
the MIMCAP 409 bottom plate 434 at connector 516. Again, the bottom
plates 432, 434 form equivalent parasitic extrinsic capacitors 452,
454, respectively, with a FEOL substrate disposed below (not shown
for clarity of illustration, but as described above with respect to
FIGS. 1, 3 and 4). As the schematic representation of FIG. 5(b)
illustrates, the cross-coupled parallel circuit structure 500 is
symmetrical as parasitic extrinsic capacitor 452 is accordingly
connected to PORT 1 410, and parasitic extrinsic capacitor 454 is
connected to PORT 2 620.
[0032] In another aspect, more than two MIMCAP's may be arranged in
a cross-coupled parallel circuit structure to provide symmetrical
BEOL MIM structures; what is important is that parasitic extrinsic
capacitors created through substrate proximity are allocated evenly
between the two circuit ports in order to prevent port polarity.
For example, FIG. 6 illustrates another conventional
multi-capacitor MIM structure 600, wherein four MIMCAP's 624 are
arranged in a parallel circuit structure between a first port 630
and a second port 632, wherein all of the upper plates 610 are
connected together by connector 630, and all of the bottom plates
612 more proximate to a chip substrate 614 are connected together
by connector 632. (It is to be understood that the substrate 614
may be one continuous substrate element, and that the substrate is
shown in discrete rectangular sections 614 in order to simplify and
clarify the illustration.) Thus, there is no provision made for
variations in the extrinsic capacitances of each of the MIMCAP's
624, and polarity results between the terminals 630 and 632.
[0033] In another aspect, FIG. 7 depicts a schematic perspective of
an alternative circuit structure with the four MIM capacitors 624
relative to the substrate 614 according to this invention. More
particularly, half of the upper plates 610 are connected to half of
the bottom plates 612 by first port connectors 736, and the other
half of the top plates 610 are connected by second port connectors
738 to the other half of the bottom plates 612. This results in a
symmetrical capacitor circuit 700 design with respect to the
substrate 614, whereby parasitic capacitance is allocated evenly to
each of the first port 736 and second port 738, as also discussed
with respect to FIG. 5 above. Thus, the present invention enables a
composite symmetrical BEOL circuit 700 with multiple MIMCAP 624's,
which offers improved Q-factor performance over a single
asymmetrical MIMCAP BEOL circuit (such as MIMCAP 300 of FIG. 3)
with a similar overall footprint.
[0034] In another aspect, the present invention also has
application to multiple MIMCAP structures incorporating other types
of capacitors. For example, it is desirable to incorporate VNCAP's
in BEOL chip applications. FIG. 8 provides a perspective view of a
VNCAP 800 illustrating a parallel metal plate and composite
capacitance structure that is desirable in some BEOL capacitor
applications. The VNCAP 800 is defined by three groups of
progressively larger metal layers. A first bottom group 860 of four
metal layers (M1 through M4) are each separated by an insulator (or
dielectric) material layer (V1 through V3), generally the first
metal layer M1 in circuit connection with FEOL circuit structures,
illustratively including MOSCAP structures (not shown). A second
middle group of larger metal layers 862 (M5 and M6, respectively,
the fifth and sixth metal layers) are mounted on the first group of
layers 860 and separated by a dielectric material layer V4 from
each other. Lastly, a third largest top group 864 of metal layers
(M7 and M8, respectively, the seventh and eighth metal layers) are
mounted atop the second metal layer group 862 and separated by a
dielectric material layer V7 from each other.
[0035] In another aspect, each of the three VNCAP metal levels 860,
862 and 864 further comprise parallel "-" signed and "+" signed
metal plates. More particularly, the VNCAP first level 860 metal
layers M1 through M4 further each comprise a plurality of "+"
signed metal plates 820 in an alternative horizontal parallel
relationship with a plurality of "-" signed metal plates 822. The
VNCAP second middle level 862 metal layers M5 and M6 further each
comprise a plurality of "+" signed metal plates 830 in an
alternative horizontal parallel relationship with a plurality of
"-" signed metal plates 832. And the VNCAP third top level 864
metal layers M7 and M8 further each comprise a plurality of "+"
signed metal plates 840 in an alternative horizontal parallel
relationship with a plurality of "-" signed metal plates 842.
[0036] VNCAP's may offer superior capacitance capabilities in BEOL
applications over smaller footprints than may be practiced with
other capacitor structures. In another aspect, the three
divergently sized VNCAP 800 bottom 860, middle 862 and top 864
metal layers each define a capacitor region having discrete
capacitance values Q1(C1), Q2(C2) and Q3(C3), respectively. Thus,
the VNCAP 800 also offers additional advantages in BEOL
applications for improving Q-factor performance in the overall
FEOL/BEOL circuit structure by enabling multiple discrete Q
elements within a small footprint, as is apparent to one skilled in
the art.
[0037] Accordingly, in another aspect of the present invention,
FIG. 9 depicts a schematic perspective of a symmetrical
multi-capacitor BEOL circuit structure 900 according to this
invention. More particularly, first and second MIM capacitors 920,
924 are in a cross-coupled parallel circuit connection with the
VNCAP 800 of FIG. 8. (For clarity, the VNCAP 800 middle metal
layers 862 are omitted from the view shown in FIG. 9). A PORT 1
terminal 901 is thus in circuit connection 909 with the first
MIMCAP 920 upper plate 902, in circuit connection 922 with the
second MIMCAP 924 bottom plate 904 and with the positive "+" VNCAP
800 capacitor plates through terminal 802 (as described above with
respect to FIG. 8). PORT 2 terminal 902 is in circuit connection
907 with the second MIMCAP 924 upper plate 903, in circuit
connection 920 with the first MIMCAP 920 bottom plate 901 and with
the negative "-" VNCAP 800 capacitor plates through terminal
801.
[0038] Although the present VNCAP example is described with respect
to specified numbers of metal layers within designated capacitor
groupings, as well as overall metal layer totals, it is to be
understood that the inventions described herein are not restricted
to the specific exemplary embodiments. It will be readily apparent
that more or less metal layers may be practiced within VNCAP's
within the teachings herein, and one skilled in the art may readily
form alternative embodiments with different metal layer numbers and
combinations.
[0039] In another aspect, the present invention may also be
practiced with other multi-MIMCAP structures. FIG. 10 depicts a
schematic perspective of a conventional rectangular array
multi-capacitor MIM structure 1000, wherein four MIMCAP's 1030
having upper plates 1010, lower plates 1012 and dielectric layer
1020 therebetween are arranged in a parallel circuit structure
between a first port 1002 and a second port 1004. This type of
array may offer advantages, including providing improved Q-factor
values relative to other single MIMCAP or multi-MIMCAP arrays in
BEOL applications. However, as discussed above, the four MIMCAP's
1030 each have greater parasitic capacitance values relative to the
substrate 1014 at their bottom plates 1012 than at their upper
plates 1010. In this conventional circuit structure, all of the
upper plates 1010 are connected to the first port 1002, and all of
the bottom plates 1012 more proximate to the chip substrate 1014
are connected to the second port 1004. (Again, it is to be
understood that the substrate 1014 may be one continuous substrate
element, and that the substrate is shown in discrete rectangular
sections 1014 in order to simplify and clarify the illustration.)
Thus, there is no provision made for variations in the extrinsic
capacitances of each of the MIMCAP's 1030, and polarity results
between the terminals 1002 and 1004 as discussed above. Correcting
for the polarity, or taking the polarity into account in circuit
design, poses many disadvantages over structures not presenting
polarity between the ports 1002, 1004.
[0040] Accordingly, in another aspect, FIG. 11 provides a top plan
view of symmetrical rectangular array multi-capacitor MIM structure
1100 according to the present invention. The four MIMCAP's 1030
arranged in a parallel circuit structure between a first port 1132
and a second port 1138, wherein half of the upper plates 1010 are
connected to half of the bottom plates 1012 in adjacent MIMCAP's
1030 by port connectors 110 and port circuit wiring 1112, and the
other half of the top plates 1010 are connected to the other half
of the bottom plates 1012 in adjacent MIMCAP's 1030 by port
connectors 110 and port circuit wiring 1112. This results in a
symmetrical capacitor circuit 1100 design with respect to the
substrate 1014, whereby parasitic capacitance is allocated evenly
to each of the first port 1136 and second port 1138, as discussed
above.
[0041] While preferred embodiments of the invention have been
described herein, variations in the design may be made, and such
variations will be apparent to those skilled in the art of
capacitors, as well as to those skilled in other arts. For example,
it will be understood that the present invention is not limited to
the specific numbers and arrangements of MIMCAP's and VNCAP's
described thus far, and the invention can work with circuit
structures comprising more that four MIM capacitors.
* * * * *