U.S. patent application number 11/702131 was filed with the patent office on 2007-11-22 for semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Tae Soo Lee, Yun Hwi Park.
Application Number | 20070267725 11/702131 |
Document ID | / |
Family ID | 38102845 |
Filed Date | 2007-11-22 |
United States Patent
Application |
20070267725 |
Kind Code |
A1 |
Lee; Tae Soo ; et
al. |
November 22, 2007 |
Semiconductor chip, method of manufacturing the semiconductor chip
and semiconductor chip package
Abstract
In a semiconductor chip, a body has a top surface where a
pattern is formed, an underside surface opposing the top surface
and a plurality of side surfaces. A plurality of electrode pads are
formed on the top surface of the body to connect to an external
terminal. A shielding conductive film is formed on the surfaces
excluding the top surface of the body where the pattern is formed.
A conductive via is extended through the body to connect one of the
electrode pads with the conductive film.
Inventors: |
Lee; Tae Soo; (Seoul,
KR) ; Park; Yun Hwi; (Yongin, KR) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY LLP
600 13TH STREET, N.W.
WASHINGTON
DC
20005-3096
US
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
|
Family ID: |
38102845 |
Appl. No.: |
11/702131 |
Filed: |
February 5, 2007 |
Current U.S.
Class: |
257/659 ;
257/737; 257/E21.495; 257/E23.01; 257/E23.011; 257/E23.114;
438/637 |
Current CPC
Class: |
H01L 23/552 20130101;
H01L 24/05 20130101; H01L 2924/3025 20130101; H01L 2224/13144
20130101; H01L 2224/05624 20130101; H01L 2924/01078 20130101; H01L
2224/05644 20130101; H01L 2224/0557 20130101; H01L 2924/01079
20130101; H01L 2224/13147 20130101; H01L 23/481 20130101; H01L
2224/0401 20130101; H01L 2924/04941 20130101; H01L 2224/16
20130101; H01L 2224/05568 20130101; H01L 2924/09701 20130101; H01L
2224/05647 20130101; H01L 2224/05573 20130101; H01L 2224/16227
20130101; H01L 2224/274 20130101; H01L 2224/0615 20130101; H01L
2224/05624 20130101; H01L 2924/00014 20130101; H01L 2224/05644
20130101; H01L 2924/00014 20130101; H01L 2224/05647 20130101; H01L
2924/00014 20130101 |
Class at
Publication: |
257/659 ;
257/737; 438/637; 257/E23.01; 257/E23.114; 257/E21.495 |
International
Class: |
H01L 23/48 20060101
H01L023/48; H01L 21/4763 20060101 H01L021/4763; H01L 23/552
20060101 H01L023/552 |
Foreign Application Data
Date |
Code |
Application Number |
May 16, 2006 |
KR |
10-2006-0043946 |
Claims
1. A semiconductor chip comprising: a body having a top surface
where a pattern is formed, an underside surface opposing the top
surface and a plurality of side surfaces; a plurality of electrode
pads formed on the top surface of the body to connect to an
external terminal; a shielding conductive film formed on the
surfaces excluding the top surface of the body where the pattern is
formed; and a conductive via extending through the body to connect
one of the electrode pads with the conductive film.
2. A semiconductor chip according to claim 1, wherein the electrode
pad connected to the conductive via is grounded.
3. A semiconductor chip according to claim 1, wherein the
conductive film is formed only on the underside surface of the
body.
4. A semiconductor chip package comprising: a semiconductor chip
including: a body having a top surface where a pattern is formed,
an underside surface opposing the top surface and a plurality of
side surfaces; a plurality of electrode pads formed on the top
surface of the body to connect to an external terminal; a shielding
conductive film formed on the surfaces excluding the top surface of
the body where the pattern is formed; and a conductive via
extending through the body to connect one of the electrode pads
with the conductive film, a substrate where a ground lead pattern
and a plurality of lead patterns are formed; and a plurality of
bumps disposed between the respective electrode pads of the
semiconductor chip and the respective lead patterns of the
substrate to electrically connect the semiconductor chip with the
substrate.
5. The semiconductor chip package according to claim 4, wherein the
electrode pad connected to the via hole is connected to the ground
lead pattern of the substrate.
6. The semiconductor chip package according to claim 4, wherein the
conductive film is formed only on the underside surface of the
semiconductor chip.
7. A method for manufacturing a semiconductor chip comprising:
forming via holes in a wafer including unit chip areas to connect
from an electrode pad on a top surface of a wafer where a pattern
is formed to an underside surface of the wafer opposing the top
surface so that at least one of the via holes is formed in each of
the unit chip areas; filling the via hole with conductive material;
forming a conductive film on the underside surface of the wafer to
contact the conductive material filled in the via hole; and cutting
the wafer into unit chips.
8. The method according to claim 7, further comprising: forming a
shielding conductive material on a side surface of the cut
semiconductor chip.
Description
CLAIM OF PRIORITY
[0001] This application claims the benefit of Korean Patent
Application No. 2006-43946 filed on May 16, 2006 in the Korean
Intellectual Property Office, the disclosure of which is
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor chip
package, more particularly, in which a shielding conductive film is
connected to a ground through a via hole, and a manufacturing
method thereof.
[0004] 2. Description of the Related Art
[0005] A high frequency module for use in a mobile
telecommunication device such as a mobile phone is constructed of a
high frequency circuit including a high frequency semiconductor
device and a periphery circuit that are formed on a substrate
thereof.
[0006] In general, current propagating in an electronic device
induces electric field and magnetic field therearound, thereby
generating a space due to electric potential difference. Here, the
electric field changes with time and generates electric magnetic
field therearound. That is, regardless of the induction of the
device, current flows to create electromagnetic noise, which is an
unnecessary energy.
[0007] Such electromagnetic noise, if transferred to other devices
through a path, leads to degradation in performance and malfunction
thereof.
[0008] To shield the electromagnetic noise and protect the
semiconductor device, a shielding technique for forming a shielding
film has been employed.
[0009] FIGS. 1a and 1b illustrate a shielding structure according
to the prior art.
[0010] FIG. 1a is a cross-sectional view illustrating a high
frequency module having a high frequency semiconductor device 12 on
a substrate 11 shielded via a metal cap 12.
[0011] In the conventional shielding structure of the high
frequency module shown in FIG. 1a, the metal cap 13, if reduced in
its thickness, cannot remain strong but is easily warped,
potentially contacting the high frequency device. To prevent
short-circuit caused by contact between the metal cap 13 and the
high frequency device, a certain space should be preserved under
the metal cap 13 to accommodate the metal cap 13 that may be
warped. For example, the metal cap should be formed to a thickness
of 100 .mu.m, and an inner space thereof should be designed to a
thickness of 80 .mu.m. This physical volume stands in the way of
miniaturization of the high frequency module.
[0012] FIG. 1b is a cross-sectional view illustrating the high
frequency module in which the shielding film is formed via a metal
film 15 after resin molding.
[0013] In FIG. 1b, the high frequency semiconductor device 12 is
mounted on the substrate 11 and resin molded to be hermetically
sealed. Then the shielding film is formed on a surface of a mold 14
using the metal film 15.
[0014] This leads to smaller physical volume compared to a case
where the metal cap is adopted. Yet, the metal film formed on the
mold is not connected to a ground of the substrate, thus
insignificant in terms of shielding effects.
SUMMARY OF THE INVENTION
[0015] The present invention has been made to solve the foregoing
problems of the prior art and therefore an aspect of the present
invention is to provide a semiconductor chip which has a shielding
layer formed thereon to connect to a ground, when the semiconductor
chip is mounted on a substrate, thereby to enhance shielding
effects and ensure the chip to be mounted in a minimal volume, and
a semiconductor package having the semiconductor chip.
[0016] Another aspect of the present invention is to provide a
method of manufacturing the semiconductor chip having the shielding
layer formed on a wafer.
[0017] According to an aspect of the invention, the invention
provides a semiconductor chip including a body having a top surface
where a pattern is formed, an underside surface opposing the top
surface and a plurality of side surfaces; a plurality of electrode
pads formed on the top surface of the body to connect to an
external terminal; a shielding conductive film formed on the
surfaces excluding the top surface of the body where the pattern is
formed; and a conductive via extending through the body to connect
one of the electrode pads with the conductive film.
[0018] The electrode pad connected to the conductive via may be
connected to an external ground and grounded.
[0019] The conductive film is formed only on the underside surface
of the body.
[0020] According to another aspect of the invention, the invention
provides a semiconductor chip package including the semiconductor
chip as described above; a substrate where a ground lead pattern
and a plurality of lead patterns are formed; and a plurality of
bumps disposed between the respective electrode pads of the
semiconductor chip and the respective lead patterns of the
substrate to electrically connect the semiconductor chip with the
substrate.
[0021] The electrode pad connected to the via hole is connected to
the ground lead pattern of the substrate.
[0022] The conductive film is formed only on the underside surface
of the semiconductor chip.
[0023] According to further another aspect of the invention, the
invention provides a method for manufacturing a semiconductor chip
including:
[0024] forming via holes in a wafer including unit chip areas to
connect from an electrode pad on a top surface of a wafer where a
pattern is formed to an underside surface of the wafer opposing the
top surface so that at least one of the via holes is formed in each
of the unit chip areas;
[0025] filling the via hole with conductive material;
[0026] forming a conductive film on the underside surface of the
wafer to contact the conductive material filled in the via hole;
and
[0027] cutting the wafer into unit chips.
[0028] The manufacturing method may further include forming a
shielding conductive material on a side surface of the cut
semiconductor chip.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The above and other objects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0030] FIGS. 1a and 1b are cross-sectional views illustrating a
shielding structure according to the prior art;
[0031] FIG. 2 is a cross-sectional view illustrating a
semiconductor chip package according to an embodiment of the
invention;
[0032] FIG. 3a is a perspective view illustrating a semiconductor
chip according to another embodiment of the invention, and FIG. 3b
is a cross-sectional view illustrating a semiconductor chip
package; and
[0033] FIG. 4a to 4d are perspective views illustrating a flow of a
method for manufacturing a semiconductor chip of FIG. 3a.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0034] Exemplary embodiments of the present invention will now be
described in detail with reference to the accompanying
drawings.
[0035] FIG. 2 is a cross-sectional view illustrating a
semiconductor chip package having a semiconductor chip mounted on a
substrate according to an embodiment of the invention.
[0036] Referring to FIG. 2, the semiconductor chip 20 is
flip-bonded onto the substrate 21.
[0037] The semiconductor chip 20 has a body 22 provided with a
plurality of electrode pads 28 on a top surface 22a thereof.
[0038] A conductive film 25 is formed on an underside surface 22b
and side surfaces of the body 22 of the semiconductor chip where
the electrode pads are not formed. Also, a via hole 27 is
perforated through the top surface 22a and one of the side surfaces
of the body 22.
[0039] The package substrate 21 is manufacturable by the same
process as the one for fabricating a printed circuit board (PCB),
or by High Temperature Chemical Cleaning (HTCC) or Low Temperature
Co-fired Ceramics (LTCC).
[0040] A circuit pattern is disposed on the package substrate 21 to
input and output a signal, and vias are formed to be connected
respectively with electrode pads on the circuit pattern to form a
ground lead pattern. The ground lead pattern is configured to
electrically connect the electrode pads on overlying and underlying
layers together.
[0041] As shown in FIG. 2, bumps 23 made of metal are formed on the
lead patterns of the circuit pattern disposed on the package
substrate 21, and the semiconductor chip is mounted on the
electrode pads 28 via the bumps 23. The flip-bonded semiconductor
chip allows the electrode pads 28 to be electrically connected to
the lead patterns on the package substrate 21 by the bumps 23.
[0042] In the semiconductor chip, the electrode pads 28 on the top
surface 22a of the body 22 are connected to the substrate 21 by the
bumps 23, some of which are ground bumps 23a connected to a ground
of the substrate. The bumps 23 formed between the lead patterns 29
of the substrate 21 and the electrode pads 28 of the semiconductor
chip are made of gold, copper, aluminum or alloys thereof and serve
to connect wires of the substrate with the semiconductor chip.
[0043] The ground bumps 23a are in direct contact with a conductive
via filled with a conductive material in the via hole 27 and serve
to electrically connect the conductive film 25 with the ground. Of
course, although the conductive via 27a is directly connected to
the bumps 23, the conductive via 27a, if electrically connected to
the ground bumps 23a on the substrate, may realize this feature of
the invention.
[0044] In this fashion, the conductive film 25 formed on the
underside surface 22b and the side surfaces of the body 22 of the
semiconductor chip is electrically connected to the ground. As a
result, electromagnetic wave generated from the semiconductor chip
is induced to flow toward the ground, and thus blocked. This
accordingly inhibits occurrence of noises. Further, this shields
electromagnetic wave induced to the semiconductor chip from
outside, thereby suppressing interference from the electromagnetic
wave.
[0045] To easily form the conductive film 25 on the underside
surface 22b and the side surfaces of the semiconductor chip,
conductive paint is directly applied on the top surface and side
surfaces of the semiconductor chip or sprayed thereonto.
[0046] FIG. 3a is a perspective view illustrating a semiconductor
chip according to an embodiment of the invention.
[0047] Referring to FIG. 3a, the semiconductor chip has a body
provided with electrode pads 38 on a top surface 32a thereof where
patterns are formed, and a metal film 35 on an underside surface
32b thereof. The metal film 35 has a via hole 37 perforated through
the body 32 of the semiconductor chip. The metal film 35 is brought
in contact with a conductive via 37a filled with a conductive
material in the via hole 37. The via hole 37 is connected to the
electrode pads 38 on the top surface 32a of the semiconductor chip
body 32.
[0048] The via hole 37 can be formed by laser processing or dry
etching such as reactive ion etch. The via hole 37 may feature
various shapes such as a circle, a triangle and a polygon. The via
hole 37 may have a uniform cross-section. Alternatively, the via
hole 37 may have a cross-section that is greater or smaller in
proportion to its proximity to the top surface 32a thereof.
[0049] The via hole 37 is filled with a conductive material to form
the conductive via 37a and extended to the electrode pads on the
top surface 32a of the semiconductor chip body 32 to electrically
connect the conductive film 35 with a ground on the substrate.
[0050] The conductive via 37a can be formed by electroplating and
the conductive material adopts all electroplatable metals such as
gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni),
and tungsten (W).
[0051] Alternatively, the conductive via 37a may be formed by
vacuum evaporation, sputtering, chemical vapor deposition and by
filling-up and sintering of a conductive paste. The conductive
material for filling the via hole 37 is exemplified by gold (Au),
silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W)
and alloys thereof.
[0052] To easily form the conductive film 35 on the underside
surface 32b of the semiconductor chip body 32, conductive paint is
directly applied to the underside surface of the semiconductor chip
body or sprayed thereonto.
[0053] FIG. 3b is a cross-sectional view illustrating a
semiconductor chip package having a semiconductor chip mounted on a
substrate.
[0054] Referring to FIG. 3b, the semiconductor chip is flip-bonded
onto the substrate 31.
[0055] The semiconductor chip has a body 32 provided with a
plurality of electrode pads 38 on a top surface 32a thereof.
[0056] A conductive film 35 is formed on an underside surface 32b
of the semiconductor chip body 32 where electrode pads are not
formed. Also, a via hole 37 is perforated through the top surface
32a and the underside surface 32b of the semiconductor chip body
32.
[0057] Further, the electrode pads 38 on the top surface 32a of the
semiconductor chip body 32 are connected to lead patterns 39 on the
substrate 31 via bumps 33, some of which are ground bumps 33a
connected to a ground on the substrate. The bumps formed between
the lead patterns 39 of the substrate 31 and the electrode pads 38
of the semiconductor chip are made of gold, copper, aluminum or
alloys thereof, and serve to connect wires of the substrate with
the chip.
[0058] The ground bumps 33a are made in direct contact with the
conductive via 37a filled with a conductive material in the via
hole 37 and serve to electrically connect the conductive film 35 to
the ground on the substrate. Of course, although the conductive via
37a is directly connected to another one of the bumps 33, the
conductive via 37a, if electrically connected to the ground bumps
33a on the substrate, may realize this feature of the
invention.
[0059] Although not illustrated, a barrier metal film may be formed
to facilitate bonding between the ground bumps 33a and the
conductive via 37a and prevent cracks from heat accompanied by use
of the chip, thereby ensuring reliability of the chip. The barrier
metal film may be made of one selected from a group consisting of
titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN),
Ti/TiN and Ta/TaN. The barrier metal film is preferably formed by
chemical vapor deposition.
[0060] The via hole 37 is filled with a conductive material to form
the conductive via 37a and extended to the ground bumps 33a formed
on the electrode pads disposed on the top surface 32a of the
semiconductor chip body 32 to electrically connect the conductive
film 35 with the ground on the substrate.
[0061] In this fashion, the conductive film 35 formed on the
underside surface 32b of the semiconductor chip body 32 is
electrically connected to the ground. As a result, electromagnetic
wave generated from the semiconductor chip is induced to flow
toward the ground, and thus blocked. This accordingly inhibits
occurrence of noises. Also, this shields electromagnetic wave
induced to the semiconductor chip from the outside, thereby
suppressing interference from the electromagnetic wave.
[0062] The conductive film 35 can be formed merely on the underside
surface 32b of the semiconductor chip body 32 when individual
semiconductor chips are applied with a conductive film material
separately from one another.
[0063] Here, at least one via hole is perforated through the top
surface and underside surface of the semiconductor chip body 32 and
filled with a conductive material. Then a conductive film is formed
on the underside surface of the semiconductor chip body to be
brought in contact with the conductive material. The conductive
film 35 can be easily formed by directly applying or spraying
conductive paint for shielding electromagnetic wave.
[0064] Alternatively, in a structure where the conductive film is
formed on the underside surface of the semiconductor chip, the via
hole and the conductive film are formed on a wafer before being cut
into the unit chips, and then cut into the unit chips. This
accordingly simplifies a manufacturing method.
[0065] FIGS. 4a to 4d illustrate a manufacturing method in which
the semiconductor chip of FIG. 3a is fabricated on a wafer.
[0066] To fabricate the semiconductor chip having a conductive film
therein on the wafer, the wafer is prepared, at least one via hole
is formed in each of unit chip areas on the wafer, a conductive
material is filled in the via hole, a conductive film is formed on
an underside surface of the wafer and the wafer is cut into unit
chips.
[0067] Referring to FIG. 4a, a via hole is formed on each of the
unit chip areas to connect from electrode pads on the top surface
of the wafer where patterns and the electrode pads are formed to
the underside surface of the wafer. FIG. 4a is a perspective view
in which the underside surface of the wafer faces upward. The via
hole 47 is formed by mechanical polishing or laser processing. To
realize an aspect of the invention, at least one via hole is
necessarily formed on each of the unit chip areas. Here, the via
hole is connected to one of the electrode pads disposed around
patterns (not illustrated) formed on the top surface of the wafer.
That is, the electrode pads are connected to a ground of the
substrate.
[0068] Referring to FIG. 4b, the via hole 47 formed on each of the
unit chip areas is filled with a conductive material to form a
conductive via 47a. This allows the conductive film 45 on the
underside surface of the semiconductor chip body 42 to electrically
connect to the ground of the substrate.
[0069] Referring to FIG. 4c, the conductive film is formed on the
underside surface of the wafer. The conductive film 45 can be
formed by directly applying or spraying conductive paint for
shielding electromagnetic wave. This simplifies a process and saves
material costs compared with a case where the conductive film is
formed-on each of the unit chips.
[0070] Here, the conductive film 45 is in direct contact with the
conductive via 47a filled with a conductive material in the via
hole 47. Preferably, the conductive film 45 is made of the same
conductive material filled in the via hole 47.
[0071] Referring to FIG. 4d, the wafer is cut into each of the unit
chips to produce the semiconductor chip according to the invention.
The conductive film 45 is formed on the underside surface of the
semiconductor chip body 42 and brought in contact with the
conductive material filled in the via hole 47. Accordingly, the
conductive via 47a connects the conductive film 45 with the ground
of the substrate.
[0072] Furthermore, optionally a shielding conductive material may
be formed on side surfaces of the cut semiconductor chip to boost
shielding effects of the conductive film.
[0073] Although not illustrated, the cut semiconductor chip is flip
bonded onto the substrate to connect the conductive via to the
ground of the substrate, thereby producing the semiconductor chip
package according to the invention.
[0074] The embodiments and the accompanying drawings are
illustrative only but do not limit the invention. Thus, the
conductive film and the via hole can be located variously.
[0075] As set forth above, according to exemplary embodiments of
the invention, when a semiconductor chip is mounted on a substrate,
a shielding metal film is connected to a ground to boost shielding
effects of electromagnetic wave and ensure the chip to be mounted
in a minimal volume.
[0076] In addition, the semiconductor chip can be fabricated on a
wafer to simplify a manufacturing process.
[0077] While the present invention has been shown and described in
connection with the preferred embodiments, it will be apparent to
those skilled in the art that modifications and variations can be
made without departing from the spirit and scope of the invention
as defined by the appended claims.
* * * * *