U.S. patent application number 11/382722 was filed with the patent office on 2007-11-15 for process environment variation evaluation.
Invention is credited to Brent A. Anderson, Edward J. Nowak, Noah D. Zamdmer.
Application Number | 20070263472 11/382722 |
Document ID | / |
Family ID | 38684955 |
Filed Date | 2007-11-15 |
United States Patent
Application |
20070263472 |
Kind Code |
A1 |
Anderson; Brent A. ; et
al. |
November 15, 2007 |
PROCESS ENVIRONMENT VARIATION EVALUATION
Abstract
Structures and methods are disclosed for evaluating the effect
of a process environment variation. A structure and related method
are disclosed including a plurality of electrical structures
arranged in a non-collinear fashion for determining a magnitude and
direction of a process environment variation in the vicinity of the
plurality of electrical structures. The plurality of structures may
include a first polarity FET coupled to a second polarity FET, each
of the first polarity FET and the second polarity FET are coupled
to a first pad and a second pad such that the structure allows
independent measurement of the first polarity FET and the second
polarity FET using only the first and second pads. Alternatively,
the electrical structures may include resistors, diodes or ring
oscillators. Appropriate measurements of each electrical structure
allow a gradient field including a magnitude and direction of the
effect of a process environment variation to be determined.
Inventors: |
Anderson; Brent A.;
(Jericho, VT) ; Nowak; Edward J.; (Essex Junction,
VT) ; Zamdmer; Noah D.; (Sleepy Hollow, NY) |
Correspondence
Address: |
HOFFMAN, WARNICK & D'ALESSANDRO LLC
75 STATE ST
14TH FLOOR
ALBANY
NY
12207
US
|
Family ID: |
38684955 |
Appl. No.: |
11/382722 |
Filed: |
May 11, 2006 |
Current U.S.
Class: |
365/230.03 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 22/34 20130101; H01L 2924/0002 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
365/230.03 |
International
Class: |
G11C 8/00 20060101
G11C008/00; H01L 21/8234 20060101 H01L021/8234; H01L 29/788
20060101 H01L029/788; H01L 21/336 20060101 H01L021/336 |
Claims
1. A structure comprising: a plurality of electrical structures
arranged in a non-collinear fashion for determining a magnitude and
direction of a process environment variation in a vicinity of the
plurality of electrical structures.
2. The structure of claim 1, wherein the plurality of electrical
structures includes one of a plurality of resistors, a plurality of
diodes, a plurality of ring oscillators and a plurality of
transistors.
3. The structure of claim 1, wherein each of the plurality of
electrical structures includes: a first polarity field effect
transistor (FET) and a second polarity FET, and wherein gates and
drains of the first polarity FET and the second polarity FET are
coupled to a first pad and sources of the first polarity FET and
the second polarity FET are coupled to a second pad.
4. The structure of claim 3, wherein each of the plurality of
structures measures a threshold voltage.
5. The structure of claim 1, wherein each of the plurality of
electrical structures includes: a first polarity field effect
transistor (FET) and a second polarity FET, and wherein a source of
the first polarity FET is coupled to a first pad, a gate and a
drain of the first polarity FET are coupled to a source of the
second polarity FET, and a gate and a drain of the second polarity
FET are coupled to a second pad.
6. The structure of claim 5, wherein a body of the first polarity
FET is coupled to the source of the first polarity FET and a body
of the second polarity FET is coupled to the source of the second
polarity FET.
7. The structure of claim 5, wherein each of the plurality of
structures measures an off current (I.sub.off).
8. The structure of claim 1, wherein the process environment
variation includes one of: a spacer etch variation, a
photolithography exposure variation, a gate length variation, a
variation in film deposition, and an anneal temperature
gradient.
9. The structure of claim 1, wherein the non-collinear fashion
includes a substantially triangulated fashion.
10. The structure of claim 1, wherein the plurality of electrical
structures are substantially identical.
11. A structure comprising: a first polarity field effect
transistor (FET) coupled to a second polarity FET, each of the
first polarity FET and the second polarity FET coupled to a first
pad and a second pad; and wherein the structure provides for
independent measurement of the first polarity FET and the second
polarity FET using only the first pad and the second pad.
12. The structure of claim 11, wherein gates and drains of the
first polarity FET and the second polarity FET are coupled to the
first pad and sources of the first polarity FET and second polarity
FET are coupled to the second pad.
13. The structure of claim 11, wherein a source of the first
polarity FET is coupled to a first pad, a gate and a drain of the
first polarity FET are coupled to a source of the second polarity
FET, and a gate and a drain of the second polarity FET are coupled
to the second pad.
14. The structure of claim 13, wherein a body of the first polarity
FET is coupled to the source of the first polarity FET and a body
of the second polarity FET is coupled to the source of the second
polarity FET.
15. A method of determining a gradient field of a process
environment variation, the method comprising: providing a plurality
of electrical structures arranged in a non-collinear fashion in a
substrate; performing a process on the substrate; measuring an
electrical property of each of the electrical structures; and
determining a magnitude and a direction of the process environment
variation in the vicinity of the plurality of electrical structures
based on the measurements.
16. The method of claim 15, wherein the plurality of electrical
structures includes one of a plurality of resistors, a plurality of
diodes, a plurality of ring oscillators and a plurality of
transistors.
17. The method of claim 15, wherein the providing includes
providing each of the plurality of electrical structures as: a
first polarity field effect transistor (FET) and a second polarity
FET, wherein gates and drains of the first polarity FET and the
second polarity FET are coupled to a first pad and sources of the
first polarity FET and the second polarity FET are coupled to a
second pad.
18. The method of claim 17, wherein the electrical property
includes a threshold voltage.
19. The method of claim 15, wherein the providing includes
providing each of the plurality of electrical structures as: a
first polarity field effect transistor (FET) and a second polarity
FET, wherein a source of the first polarity FET is coupled to a
first pad, a gate and a drain of the first polarity FET are coupled
to a source of the second polarity FET, and a gate and a drain of
the second polarity FET are coupled to a second pad.
20. The method of claim 19, wherein the electrical property
includes an off current (I.sub.off).
21. The method of claim 15, wherein the process environment
variation includes one of: a spacer etch variation, a
photolithography exposure variation, a gate length variation, a
variation in film deposition, and an anneal temperature
gradient.
22. The method of claim 15, wherein the providing includes
providing the plurality of electrical structures in a substantially
triangulated fashion.
23. The method of claim 15, wherein the providing includes
providing the plurality of electrical structures interconnected to
a plurality of pads.
24. A method of independently evaluating transistors, the method
comprising: forming a first polarity field effect transistor (FET)
coupled to a second polarity FET, each of the first polarity FET
and the second polarity FET coupled to a first pad and a second
pad; and independently measuring the first polarity FET and the
second polarity FET using only the first pad and the second
pad.
25. The method of claim 24, wherein the forming includes forming
gates and drains of the first polarity FET and the second polarity
FET are coupled to the first pad and sources of the first polarity
FET and second polarity FET are coupled to the second pad.
26. The method of claim 25, wherein the measuring includes
measuring a threshold voltage.
27. The method of claim 24, wherein the forming includes coupling a
source of the first polarity FET to a first pad, a gate and a drain
of the first polarity FET to a source of the second polarity FET,
and a gate and a drain of the second polarity FET to the second
pad.
28. The method of claim 27, wherein the forming further includes
coupling a body of the first polarity FET to the source of the
first polarity FET and a body of the second polarity FET to the
source of the second polarity FET.
29. The method of claim 27, wherein the measuring includes
measuring an off-current (Ioff).
30. The method of claim 24, wherein the measuring includes at least
one of: applying a positive voltage ramp to the first pad with
respect to the second pad to maintain the first polarity FET in an
off-state and measuring the second polarity FET; and applying a
negative voltage ramp to the first pad with respect to the second
pad to maintain the second polarity FET in an off-state and
measuring the first polarity FET.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical Field
[0002] The invention relates generally to microelectronics
fabrication, and more particularly, to structures and methods for
evaluating the effect of process environment variations across a
chip.
[0003] 2. Background Art
[0004] In the microelectronic fabrication industry, there is often
a need to evaluate the effect of process environment variations on
a chip and, in particular, across a chip. For example, oftentimes
data pertaining to electrical properties of threshold voltage (Vt)
of field effect transistors (FETs) based on variations in a process
is required. More specifically, it may be required to evaluate the
variation of PFET and NFET threshold voltage with respect to
process environment variations experienced during fabrication.
Threshold voltage (Vt) may vary within a chip, for example, due to
variations in gate length caused by reactive ion etching (RIE) load
variation or photoresist planarization variations. In another
example, a pattern density of various material stacks can modulate
the rapid thermal anneal (RTA) temperature locally and may cause as
much as 100 mV variation in threshold voltage (Vt) within a chip.
One approach to this problem is to measure an electrical property
of two transistors and then to characterize across chip variation
based on those measurements. This approach, however, can require a
very large sample size of transistors to provide adequate data for
variations over many length scales. For example, the
characterization does not enable an evaluation of a direction of
the process environment variation on the chip. Currently, there is
no mechanism available for accurately determining a magnitude and a
direction of the effect of a process environment variation across a
chip.
SUMMARY OF THE INVENTION
[0005] Structures and methods are disclosed for evaluating the
effect of a process environment variation. A structure and related
method are disclosed including a plurality of electrical structures
arranged in a non-collinear fashion for determining a magnitude and
direction of a process environment variation in the vicinity of the
plurality of electrical structures. The plurality of structures may
include a first polarity FET coupled to a second polarity FET, each
of the first polarity FET and the second polarity FET are coupled
to a first pad and a second pad such that the structure allows
independent measurement of the first polarity FET and the second
polarity FET using only the first and second pads. Alternatively,
the electrical structures may include resistors, diodes or ring
oscillators. Appropriate measurements of each electrical structure
allow a gradient field including a magnitude and direction of the
effect of a process environment variation to be determined.
[0006] A first aspect of the invention provides a structure
comprising: a plurality of electrical structures arranged in a
non-collinear fashion for determining a magnitude and direction of
a process environment variation in a vicinity of the plurality of
electrical structures.
[0007] A second aspect of the invention provides a structure
comprising: a first polarity field effect transistor (FET) coupled
to a second polarity FET, each of the first polarity FET and the
second polarity FET coupled to a first pad and a second pad; and
wherein the structure provides for independent measurement of the
first polarity FET and the second polarity FET using only the first
pad and the second pad.
[0008] A third aspect of the invention provides a method of
determining a gradient field of a process environment variation,
the method comprising: providing a plurality of electrical
structures arranged in a non-collinear fashion in a substrate;
performing a process on the substrate; measuring an electrical
property of each of the electrical structures; and determining a
magnitude and a direction of the process environment variation in
the vicinity of the plurality of electrical structures based on the
measurements.
[0009] A fourth aspect of the invention provides a method of
independently evaluating transistors, the method comprising:
forming a first polarity field effect transistor (FET) coupled to a
second polarity FET, each of the first polarity FET and the second
polarity FET coupled to a first pad and a second pad; and
independently measuring the first polarity FET and the second
polarity FET using only the first pad and the second pad.
[0010] The illustrative aspects of the present invention are
designed to solve the problems herein described and/or other
problems not discussed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] These and other features of this invention will be more
readily understood from the following detailed description of the
various aspects of the invention taken in conjunction with the
accompanying drawings that depict various embodiments of the
invention, in which:
[0012] FIG. 1 shows one embodiment of a structure for evaluating
process environment variation according the invention.
[0013] FIG. 2A shows a first embodiment of an electrical structure
used in the structure of FIG. 1 including resistors.
[0014] FIG. 2B shows a second embodiment of an electrical structure
used in the structure of FIG. 1 including diodes.
[0015] FIG. 2C shows a third embodiment of an electrical structure
used in the structure of FIG. 1 including ring oscillators.
[0016] FIG. 3 shows a fourth embodiment of an electrical structure
used in the structure of FIG. 1 including transistors.
[0017] FIG. 4 shows the fourth embodiment of the electrical
structure of FIG. 3 implemented in the layout of FIGS. 2A-2B.
[0018] FIG. 5 shows an alternative fourth embodiment of an
electrical structure used in the structure of FIG. 1 including
transistors.
[0019] FIG. 6 shows the alternative fourth embodiment of the
electrical structure of FIG. 5 implemented in the layout of FIG.
2A-B.
[0020] It is noted that the drawings of the invention are not to
scale. The drawings are intended to depict only typical aspects of
the invention, and therefore should not be considered as limiting
the scope of the invention. In the drawings, like numbering
represents like elements between the drawings.
DETAILED DESCRIPTION
[0021] Referring to the drawings, FIG. 1 shows one embodiment of a
structure 100 for evaluating the effect of a process environment
variation across a chip 102. Structure 100 includes a plurality of
electrical structures 104 arranged in a non-collinear fashion for
determining a magnitude and a direction of a process environment
variation in the vicinity of plurality of electrical structures
104. The process environment variation may include practically any
environmental characteristic that varies during a particular
fabrication process, e.g., etching, annealing, material deposition,
ion implanting, etc. For example, a process environment variation
may include a spacer etch variation, a photolithography exposure
variation, a gate length variation, a variation in film deposition,
and an anneal temperature gradient. While three electrical
structures 104A-C are shown, it is understood that any number of
electrical structures 104 greater than or equal to three may be
used. Each electrical structure is positioned at an X-coordinate
and a Y-coordinate within chip 102 such that the three (or more)
structures are not collinear. As illustrated, only electrical
structures 104A and 104B share a Y coordinate, i.e., Y1=Y2. In one
embodiment, where three electrical structures 104A-C are used, this
results in a substantially triangulated arrangement. The triangular
arrangement does not need to be any particular type of triangle,
e.g., isosceles, right, etc. Electrical structures 104A-C are
interconnected, via interconnects 110, to a plurality of probe pads
(or simply "pads") 106. As illustrated, electrical structures
104A-C are interconnected by four pads 106A-D, but more may be
employed where more electrical structures 104 are used.
[0022] Electrical structures 104 may take the form of a variety of
different electrical devices. In one embodiment, electrical
structures may each include a resistor, a diode or a ring
oscillator. In this case, each end (input or output) of the
aforementioned devices are coupled as indicated in FIG. 1. FIG. 2A
shows one embodiment employing doped polysilicon resistors 120A-C.
As illustrated, resistors 122A-C are interconnected to pads 106A-D.
FIG. 2B shows another embodiment employing diodes 122A-122C. As
illustrated, diodes 120A-C are interconnected to pads 106A-D. FIG.
2C shows another embodiment employing ring oscillators 124A-C. As
illustrated, ring oscillators 124A-C are interconnected to pads
106A-D, and output signals of each ring oscillator 124A-C are
connected to a signal probe pad 126.
[0023] Turning to FIGS. 3 and 5, in another embodiment, each
electrical structure 104 may include a plurality of transistors. In
FIGS. 3 and 5, two transistors 130A-B are shown, respectively.
However, it is understood that any number of transistors 130A-B
greater than or equal to two may be used. In the transistor
embodiment, each electrical structure 104 may include a first
polarity field effect transistor (FET), e.g., a NFET 130A, 230A,
coupled to a second polarity FET, e.g., a PFET 130B, 230B. It is
understood that the position of each type FET may be switched from
what is illustrated. As will be described in greater detail below,
first polarity FET 130A, 230A and second polarity FET 130B, 230B
are each coupled to a first pad 206A, 306A and a second pad 206B,
2306B. With this structure, independent measurement of first
polarity FET 130A, 230A and second polarity FET 130B, 230B using
only first pad 206A, 306A and second pad 206B, 306B is made
possible. The electrical property measured may be varied depending
on the particular structure provided.
[0024] With specific reference to FIG. 3, in one version of the
transistor embodiment of electrical structure 104, gates 140 and
drains 142 of first polarity FET 130A and second polarity FET 130B
are coupled to first pad 206A, and sources 144 of first polarity
FET 130A and second polarity FET 130B are coupled to second pad
206B. In this case, each electrical structure 104 employs
measurement of a threshold voltage (Vt). FIG. 4 shows the
transistor embodiment of electrical structure 104 of FIG. 3
implemented in the layout of FIGS. 2A-B. Referring to FIGS. 3 and
4, to measure NFET 130A Vt, positive voltage is supplied to pad
206A to which the gates are connected with reference to ground on
pad 206B. The voltage applied is adjusted until the current drawn
achieves a preset condition defining threshold voltage (typically
40 to 400 nA times the width of the FET and divided by the length
of the FET). Similarly, PFET 130B Vt can be measured by providing
negative voltage to pad 206A to which the gates are connected with
reference to ground on pad 206B. The voltage applied is adjusted
until the current drawn achieves a preset condition defining
threshold voltage (typically 40 to 400 nA times the width of the
FET and divided by the length of the FET).
[0025] Turning to FIG. 5, in another version of the transistor
embodiment of electrical structure 104, a source 244A of a first
polarity FET 230A (e.g., an NFET) is coupled to first pad 306A, a
gate 240A and a drain 242A of first polarity FET 230A are coupled
to a source 244B of second polarity FET 230B (e.g., a PFET), and a
gate 240B and a drain 242B of second polarity FET 230B are coupled
to a second pad 306B. In this case, electrical structure 104
measures an off current (I.sub.off). As an option in this case, a
body 246A of first polarity FET 230A is coupled to source 244A of
first polarity FET 230A and a body 246B of second polarity FET 230B
is coupled to source 244B of second polarity FET 230B. Another
option allows for each body 246A, 246B to be connected to a
dedicated probe pad (not shown). FIG. 6 shows the transistor
embodiment of electrical structure 104 of FIG. 5 implemented in the
layout of FIGS. 2A-B. Referring to FIGS. 5 and 6, the off-current
of NFET 230A is measured by providing a positive voltage (greater
than Vt) on pad 306A to which only a drain is electrically
connected to ground on pad 306B. The current measured in this state
is the off-current (Ioff) of NFET 230A. The off-current of PFET
230B is obtained by providing a negative voltage (greater than Vt)
on pad 306A to which only a drain is electrically connected to
ground on pad 306B. The current measured in this state is
off-current (Ioff) of PFET 230B.
[0026] It is understood that, in one embodiment, each electrical
structure 104 is substantially identical in design to the others
used therewith to provide accurate gradient measurements. However,
some variation may be allowed in some cases.
[0027] In one embodiment, the above-described structure 100 (FIG.
1) may be employed to measure the effect of a process environment
variation across a chip 102 (FIG. 1). In this case, one of the
above-described embodiments of electrical structures 104 is
provided. That is, a plurality of electrical structures 104 are
arranged in a non-collinear fashion in a substrate 150 (FIG. 1)
used to fabricate a chip 102. Next, a process is performed on
substrate 102. The process may include any now known or later
developed semiconductor fabrication process, e.g., an etch, an
anneal, material deposition, ion implanting, etc. An electrical
property, e.g., threshold voltage (Vt), resistance (R), off current
(Ioff), etc., of each of electrical structures 104 is measured. The
particular type of electrical property measured varies depending on
the type of electrical structure 104 used. For example, resistance
is measured if resistors are used, threshold voltage (Vt) or off
current (Ioff) is measured if transistors are used, a reverse bias
leakage or forward bias voltage may be measured if diodes are used,
and a speed or delay using fixed voltages may be measured if ring
oscillators are used.
[0028] Based on the measurements, a magnitude and a direction of
the process environment variation in the vicinity of the plurality
of electrical structures 104 can be determined. For example,
assuming electrical structures 104 shown in FIG. 1 are transistor
structures as shown in FIG. 3, electrical structure 104A having a
higher threshold voltage (Vt) compared to electrical structures
104B, 104C may indicate a pattern density of various material
stacks at the location, i.e., X1, Y1, of electrical structure 104A
has altered the rapid thermal anneal (RTA) temperature locally. In
another example, electrical structures 104 may include doped
polysilicon resistors, which are sensitive to annealing
temperatures. In this case, resistance measurements can be used to
determine the anneal temperature at the location of each electrical
structure 104 (e.g., using empirical data) or the effect of the
annealing at the location of each electrical structure 104. In any
event, the non-collinear location of electrical structures 104
allows an evaluation in two dimensions, i.e., based on location,
such that a direction of the effect can be determined. For example,
the local magnitude and direction of change can be calculated from
the data obtained from the three structures 104 as follows. Let Z1,
Z2, and Z3 represent the electrical measurements obtained from
structures 104A, 104B, and 104C, respectively. Then the components
of the gradient of the variable Z can be calculated from:
dZ/dY=[(X2-X1)(Z3-Z1)-(Z2-Z1)(X3-X1)]/[(X2-X1)(Y3-Y1)-(Y2-Y1)(X3-X1-
)] (Eq. 1)
dZ/dY=[(Y3-Y1)(Z2-Z1)-(Z3-Z1)(Y2-Y1)]/[(X2-X1)(Y3-Y1)-(Y2-Y1)(X3-X1)]
(Eq. 2).
[0029] In another embodiment, a method of independently evaluating
transistors may be employed using the structure of FIG. 3 or 5
alone, or as part of the above-described embodiment for evaluating
the effect of a process environment variation. The structure used
can be selected from any of the above-described versions of the
transistor embodiment, i.e., FIGS. 3 and 5. In this case, as shown
in, for example, FIG. 3, first polarity FET 130A is coupled to
second polarity FET 130B with each first polarity FET 130A and
second polarity FET 130B coupled to first pad 206A and second pad
206B. As transistors 130A, 130B are provided, various processes are
performed on first polarity FET 130A and second polarity FET 130B.
Independently measuring first polarity FET 130A and second polarity
FET 130B using only first pad 206A and second pad 206B may then
occur to evaluate transistors 130A, 130B and, hence, the processes
used to create them. The type of electrical property measured will
vary depending the structure used. For example, referring to FIG.
3, the measuring may include: applying a positive voltage ramp to
one pad 206A with respect to the other pad 206B to maintain PFET
130B in an off-state and measuring NFET 130A, i.e., measuring a
threshold voltage thereof. Additionally, a negative voltage ramp
may be applied to pad 206B with respect to the other pad 206A to
maintain NFET 130A in an off-state and measure PFET 130B, i.e.,
measuring a threshold voltage thereof. One example may include:
applying a positive ramp on pad 206B with an ammeter to ground on
the other pad 206A. This situation will turn NFET 130A on when the
threshold voltage (Vt) is reached, while PFET 130B remains off.
Hence, the situation will force a positive current, e.g.,
approximately 300 nA.times.W/L, resulting in the value of the
threshold voltage (Vt) of NFET 130A to be communicated from pad
206B to pad 206A. Similarly, if a negative current is forced into
pad 206A of a value of, for example, approximately 70 nA.times.W/L,
then the voltage from pad 206A to pad 206B will represent the
threshold voltage (Vt) of PFET 130B. If the FIG. 5 embodiment is
employed, the same process may be implemented and the off current
(Ioff) may be measured.
[0030] For semiconductor-on-insulator (SOI) FETs, the body of each
transistor `floats` (i.e. is not explicitly electrically connected
to an external terminal) and, hence, the embodiments described
above have not addressed body connections. In bulk complementary
metal-oxide semiconductors (CMOS) and, occasionally in SOI, body
contacts are available for FETs. In this case, the bodies may
continue to be left to `float` or, the bodies may be explicitly
connected in a number of ways. One such connection is illustrated
in FIG. 3 with dashed lines connecting bodies 146A, 146B to sources
144. Alternatively, bodies 146A, 146B can be wired to other probe
pads.
[0031] The foregoing description of various aspects of the
invention has been presented for purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise form disclosed, and obviously, many
modifications and variations are possible. Such modifications and
variations that may be apparent to a person skilled in the art are
intended to be included within the scope of the invention as
defined by the accompanying claims.
* * * * *