U.S. patent application number 11/735627 was filed with the patent office on 2007-09-20 for method for mounting an electronic part on a substrate using a liquid containing metal particles.
This patent application is currently assigned to Hitachi, Ltd.. Invention is credited to HIROSHI HOZOJI, Toshiaki Morita, Hiroshi Sasaki.
Application Number | 20070216012 11/735627 |
Document ID | / |
Family ID | 35822468 |
Filed Date | 2007-09-20 |
United States Patent
Application |
20070216012 |
Kind Code |
A1 |
HOZOJI; HIROSHI ; et
al. |
September 20, 2007 |
METHOD FOR MOUNTING AN ELECTRONIC PART ON A SUBSTRATE USING A
LIQUID CONTAINING METAL PARTICLES
Abstract
An electronic part mounting method, a semiconductor module, and
a semiconductor device, which can reduce a mounting area and a
device thickness. In an electronic part mounting method for bonding
an electrode formed on a substrate and an electrode formed on an
electronic part to each other, the method comprises the step of
bonding both the electrodes through a metal layer made up of
aggregated particles of at least one kind of metal. Then, the metal
particles have an average particle size of 1 to 50 nm. Preferably,
the metal particles form a metal layer having a thickness of 5 to
100 .mu.m.
Inventors: |
HOZOJI; HIROSHI;
(Hitachiohta, JP) ; Morita; Toshiaki; (Hitachi,
JP) ; Sasaki; Hiroshi; (Mito, JP) |
Correspondence
Address: |
CROWELL & MORING LLP;INTELLECTUAL PROPERTY GROUP
P.O. BOX 14300
WASHINGTON
DC
20044-4300
US
|
Assignee: |
Hitachi, Ltd.
Chiyoda-ku
JP
|
Family ID: |
35822468 |
Appl. No.: |
11/735627 |
Filed: |
April 16, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10966038 |
Oct 18, 2004 |
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11735627 |
Apr 16, 2007 |
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Current U.S.
Class: |
257/690 ;
257/E21.51; 257/E23.14; 257/E23.141 |
Current CPC
Class: |
H01L 2924/1306 20130101;
Y02P 70/611 20151101; H01L 2224/2919 20130101; H01L 2924/01074
20130101; H01L 2924/181 20130101; H01L 2924/01044 20130101; H01L
2224/16238 20130101; H01L 24/29 20130101; H01L 25/072 20130101;
H01L 2224/48091 20130101; H01L 2224/84801 20130101; H01L 2924/01029
20130101; H01L 24/11 20130101; H01L 2924/01046 20130101; H05K 3/328
20130101; H01L 2224/371 20130101; H01L 23/24 20130101; H01L
2224/0554 20130101; H01L 2224/11505 20130101; H01L 2224/48472
20130101; H05K 2203/1131 20130101; H01L 24/45 20130101; H01L
2224/05573 20130101; H01L 2224/05644 20130101; H01L 2224/81815
20130101; H01L 2924/01027 20130101; H01L 2924/01047 20130101; H01L
2924/12044 20130101; H01L 2924/15787 20130101; H01L 2924/351
20130101; H01L 24/41 20130101; H01L 2224/11332 20130101; H01L
2224/8384 20130101; H01L 2924/01005 20130101; H05K 1/183 20130101;
H01L 2224/83191 20130101; H01L 2924/01072 20130101; H01L 2224/32225
20130101; H01L 2224/81192 20130101; H01L 2924/10253 20130101; H01L
2924/13055 20130101; H01L 2924/15788 20130101; H01L 2224/3754
20130101; H01L 2223/6644 20130101; H01L 2224/13347 20130101; H01L
2224/29144 20130101; H01L 2224/85205 20130101; H01L 2924/1301
20130101; H05K 3/102 20130101; H01L 2924/00011 20130101; H01L
2924/01024 20130101; H01L 24/13 20130101; H01L 2224/13444 20130101;
H01L 2924/01073 20130101; H01L 2924/1517 20130101; H05K 2201/10674
20130101; H01L 2224/40095 20130101; H01L 24/48 20130101; H01L
2224/13339 20130101; H01L 2224/48227 20130101; H01L 2924/01042
20130101; H01L 2924/19043 20130101; H01L 2224/8484 20130101; H01L
2224/13099 20130101; H01L 2224/13355 20130101; H01L 2224/29
20130101; H01L 2924/12041 20130101; H01L 2924/19042 20130101; H05K
2201/10636 20130101; Y02P 70/50 20151101; H01L 2224/13439 20130101;
H01L 24/03 20130101; H01L 2224/13139 20130101; H05K 2201/0218
20130101; H01L 24/40 20130101; H01L 2224/13344 20130101; H01L
2224/81191 20130101; H01L 2924/19041 20130101; H01L 24/05 20130101;
H01L 2224/40225 20130101; H01L 2924/01033 20130101; H01L 2924/01049
20130101; H01L 2924/01078 20130101; H01L 2224/73265 20130101; H01L
23/66 20130101; H01L 2224/45015 20130101; H01L 2224/49111 20130101;
H01L 2224/83801 20130101; H01L 2924/01322 20130101; H01L 2924/014
20130101; H01L 2924/0132 20130101; H01L 24/84 20130101; H01L
2924/01061 20130101; H05K 2201/0257 20130101; H01L 2924/14
20130101; H01L 2924/01006 20130101; H01L 2924/01019 20130101; H01L
2224/8121 20130101; H01L 2224/13455 20130101; H01L 2924/09701
20130101; H01L 2924/0103 20130101; H01L 24/32 20130101; H01L 24/81
20130101; H01L 2224/83192 20130101; H01L 24/37 20130101; H01L 24/49
20130101; H01L 2924/01082 20130101; H01L 2924/19107 20130101; H01L
2924/00013 20130101; H01L 2924/01023 20130101; H01L 2924/01076
20130101; H01L 2924/01079 20130101; H01L 2924/10272 20130101; H01L
24/16 20130101; H01L 2224/05568 20130101; H01L 2924/0105 20130101;
H05K 3/321 20130101; H01L 2924/01022 20130101; H01L 24/33 20130101;
H01L 2224/29101 20130101; H01L 2224/29344 20130101; H01L 2924/15153
20130101; H01L 2224/27505 20130101; H01L 24/83 20130101; H01L
2224/13006 20130101; H01L 2924/00014 20130101; H01L 2924/0665
20130101; H01L 2924/13091 20130101; H01L 2224/16013 20130101; H01L
2224/45124 20130101; H01L 2224/16225 20130101; H01L 2224/29111
20130101; H01L 25/16 20130101; H01L 2224/13144 20130101; H01L
2224/49175 20130101; H01L 2224/81205 20130101; H01L 2924/01013
20130101; H01L 2924/19105 20130101; H01L 2924/01045 20130101; H01L
2924/01077 20130101; H01L 2924/0133 20130101; H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2924/0665 20130101; H01L
2924/00 20130101; H01L 2224/29101 20130101; H01L 2924/014 20130101;
H01L 2924/00 20130101; H01L 2224/49111 20130101; H01L 2224/48472
20130101; H01L 2924/00 20130101; H01L 2224/49111 20130101; H01L
2224/48227 20130101; H01L 2924/00 20130101; H01L 2224/48472
20130101; H01L 2224/48227 20130101; H01L 2924/00 20130101; H01L
2224/83192 20130101; H01L 2224/32225 20130101; H01L 2224/49175
20130101; H01L 2224/48227 20130101; H01L 2924/00 20130101; H01L
2224/49175 20130101; H01L 2224/48472 20130101; H01L 2924/00
20130101; H01L 2224/16225 20130101; H01L 2924/13091 20130101; H01L
2924/0132 20130101; H01L 2924/01013 20130101; H01L 2924/01014
20130101; H01L 2924/0132 20130101; H01L 2924/01029 20130101; H01L
2924/01042 20130101; H01L 2924/0132 20130101; H01L 2924/01029
20130101; H01L 2924/01047 20130101; H01L 2924/0132 20130101; H01L
2924/01029 20130101; H01L 2924/01074 20130101; H01L 2924/0133
20130101; H01L 2924/01029 20130101; H01L 2924/01047 20130101; H01L
2924/0105 20130101; H01L 2924/0132 20130101; H01L 2924/0105
20130101; H01L 2924/01082 20130101; H01L 2224/16225 20130101; H01L
2224/13144 20130101; H01L 2924/00 20130101; H01L 2224/16225
20130101; H01L 2224/13139 20130101; H01L 2924/00 20130101; H01L
2224/29111 20130101; H01L 2924/01082 20130101; H01L 2924/00015
20130101; H01L 2924/00 20130101; H01L 2224/29344 20130101; H01L
2924/00014 20130101; H01L 2224/73265 20130101; H01L 2224/32225
20130101; H01L 2224/48227 20130101; H01L 2924/00 20130101; H01L
2924/00013 20130101; H01L 2224/29099 20130101; H01L 2224/48472
20130101; H01L 2224/48091 20130101; H01L 2924/00 20130101; H01L
2924/00013 20130101; H01L 2224/29199 20130101; H01L 2924/00013
20130101; H01L 2224/29299 20130101; H01L 2924/00013 20130101; H01L
2224/2929 20130101; H01L 2924/10253 20130101; H01L 2924/00
20130101; H01L 2924/12041 20130101; H01L 2924/00 20130101; H01L
2924/1306 20130101; H01L 2924/00 20130101; H01L 2924/1301 20130101;
H01L 2924/00 20130101; H01L 2224/45015 20130101; H01L 2924/00
20130101; H01L 2224/45015 20130101; H01L 2924/2076 20130101; H01L
2924/351 20130101; H01L 2924/00 20130101; H01L 2224/45015 20130101;
H01L 2924/00014 20130101; H01L 2924/2076 20130101; H01L 2224/81205
20130101; H01L 2924/00014 20130101; H01L 2924/00011 20130101; H01L
2224/83205 20130101; H01L 2924/181 20130101; H01L 2924/00012
20130101; H01L 2224/45124 20130101; H01L 2924/01014 20130101; H01L
2224/45124 20130101; H01L 2924/01028 20130101; H01L 2224/05644
20130101; H01L 2924/00014 20130101; H01L 2924/00011 20130101; H01L
2924/01005 20130101; H01L 2924/00014 20130101; H01L 2224/05599
20130101; H01L 2924/00014 20130101; H01L 2224/0555 20130101; H01L
2924/00014 20130101; H01L 2224/0556 20130101; H01L 2224/13339
20130101; H01L 2924/013 20130101; H01L 2924/00014 20130101; H01L
2224/13344 20130101; H01L 2924/013 20130101; H01L 2924/00014
20130101; H01L 2224/13355 20130101; H01L 2924/00014 20130101; H01L
2224/13439 20130101; H01L 2924/013 20130101; H01L 2924/00014
20130101; H01L 2224/13444 20130101; H01L 2924/013 20130101; H01L
2924/00014 20130101; H01L 2224/13455 20130101; H01L 2924/00014
20130101; H01L 2224/13347 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/690 ;
257/E23.141 |
International
Class: |
H01L 23/52 20060101
H01L023/52; H01L 29/06 20060101 H01L029/06 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 29, 2004 |
JP |
2004-190639 |
Claims
1. A semiconductor module wherein an electrode formed on a
substrate and an electrode formed on an electronic part are bonded
to each other through a metal layer made up of aggregated particles
at least on kind of metal having an average particle size of 1 to
50 nm and having an average particles size of 1 to 100 mm.
2. A semiconductor module having a structure in which a plurality
of semiconductor elements are connected through a first connecting
material to a substrate having an electrode formed thereon, and
said substrate is connected to an external mounting board through a
second connecting material, said first connecting material being a
metal layer made up of aggregated particles of at least one kind of
metal selected from among Au and Ag, and having an average particle
size of 1 to 50 nm and having an average particle size of 1 to 100
mm.
3. A semiconductor module according to claim 2, wherein said second
connecting material is one of a brazing material containing Sn as a
main component, a lead-free solder material, and a metal layer made
up of aggregated particles of at least one kind of metal selected
from among Au and Ag.
4. A semiconductor module having a structure in which a plurality
of semiconductor elements are connected through a first connecting
material to a substrate is connected to an material, said second
connecting material being a metal layer made up of aggregated
particles of at least one kind of metal selected from among Au and
Ag, and having an average particle size of 1 to 50 nm and having an
average particle size of 1 to 100 mm.
5. A semiconductor module according to claim 4, wherein said first
connecting material is one of a brazing material containing Sn as a
main component and a lead-free solder material.
6. A semiconductor device wherein an electrode formed on a
substrate surface and an electrode formed on an electronic part
surface are bonded to each other through a metal later made up of
particles having an average particle size of 1 to 50 nm and having
an average particle size of 1 to 100 mm, said particles being made
of at least one kind of metal selected from among Au and Ag.
7. A semiconductor device according to claim 6, wherein said metal
particles having an average particle size of 1 to 100 mm are formed
by coating layers of Au or an Au alloy on surfaces of nickel
particles.
8. A semiconductor device according to claim 6, wherein said minute
particles having an average particle size of 1 to 50 nm are coupled
to surfaces of said particles having an average particle size of 1
to 100 mm.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an electronic part mounting
method, a semiconductor module, and a semiconductor device.
[0003] 2. Description of the Related Art
[0004] Usually, a high-frequency power amplifier is incorporated in
a portable communication unit represented by a car phone or a
cellular phone based on the PDC (Personal Digital Cellular) system,
or a cellular phone based on the PHS (Personal Handy-phone System).
As well known, the high-frequency power amplifier is constituted as
a semiconductor module, and it is a multistage amplifier comprising
a plurality of amplifiers interconnected in multiple stages.
[0005] Such a high-frequency power amplifier is formed on one
principal surface of a semiconductor chip, and the semiconductor
chip including the amplifier is mounted on one principal surface of
a wiring board. Electrodes formed on the one principal surface of
the semiconductor chip and electrodes formed on the one principal
surface of the wiring board are connected to each other by
conductive wires.
[0006] More specifically, the high-frequency power amplifier
comprises, for example, a plurality of field effect transistors
electrically connected in parallel. A gate terminal serving as an
input portion of the high-frequency power amplifier is electrically
connected to a chip-side input electrode formed on the one
principal surface of the semiconductor chip.
[0007] On the other hand, a drain terminal serving as an output
portion of the high-frequency power amplifier is electrically
connected to a chip-side output electrode formed on the one
principal surface of the semiconductor chip. The chip-side input
electrode is arranged at one side of the semiconductor chip, and
the chip-side output electrode is arranged at another side of the
semiconductor chip, which is positioned in opposite relation to the
one side.
[0008] A source terminal of the high-frequency power amplifier is
electrically connected to a rear-side electrode formed on another
surface (i.e., a rear surface) of the semiconductor chip, which is
positioned in opposite relation to the one principal surface of the
semiconductor chip. The rear electrode is fixedly held at a
reference potential. The chip-side input electrode is electrically
connected, by an input wire, to a board-side input electrode formed
on the one principal surface of the wiring board in facing relation
to the one side of the semiconductor chip. The chip-side output
electrode is electrically connected, by an output wire, to a
board-side output electrode formed on the one principal surface of
the wiring board in facing relation to the other side of the
semiconductor chip.
[0009] One practical semiconductor module is described in "Hitachi
Hyoron", No. 4, 1993, pp. 12-26. published Apr. 25, 1993 by Hitachi
Hyoron Co. In this semiconductor module (i.e., a MOS power module
for the high-frequency power amplifier), power MOSFET's are
incorporated in three stages to increase an output.
[0010] Non-Patent Reference 1 further discusses various types of
semiconductor modules in the packaged form. The semiconductor
module assembled in a cellular phone employs a metallic cover and
surface mounting for the purpose of size reduction.
[0011] FIG. 15 shows the structure of a known semiconductor module
employing a metallic cover (hereinafter referred to as a "cap") and
the surface mounting. A glass-ceramic substrate 202 is fixed to a
principal surface (upper surface) of a heat radiating flange 201 in
the form of a rectangular plate by using a solder (not shown).
[0012] Active parts, such as power MOSFET's (not shown), and
passive parts, such as resistances and capacitors (not shown), are
mounted on a principal surface (upper surface) of the substrate
202. The active parts, such as the power MOSFET's, are connected to
external terminals by wire bonding.
[0013] Further, a cap 203 is attached to the heat radiating flange
201 so as to cover the principal surface of the glass-ceramic
substrate 202. Openings are formed in one side surface of the cap
203, and leads 204 having inner ends fixed to the glass-ceramic
substrate 202 are led out through the openings. Fins 205 for face
fixing are each disposed to project in the form of one step (i.e.,
an L-like bent shape) outward from a side edge of the heat
radiating flange 201.
[0014] The fins 205 for face fixing not only serve to transmit heat
to a chassis (not shown) on which a high-frequency power module 206
is mounted, but also function as a ground pin. The heat radiating
flange 201 is electrically connected to ground wiring on the
principal surface of the glass-ceramic substrate 202 through a
conductor filled in a through hole formed in the glass-ceramic
substrate 202.
[0015] JP-A-10-50926 discloses a heat radiating module in which a
heat-generating circuit part is placed in a recess formed in a
circuit board, and solder bumps of the circuit part are soldered to
land electrodes of a circuit board. Further, the thus-obtained
circuit board is mounted on a mother circuit board through a heat
conductive member, and terminal electrodes provided on a side
surface of the circuit board are soldered to land electrodes on the
mother circuit board, thereby transmitting the heat generated from
the circuit part to the mother circuit board for the purpose of
heat radiation.
[0016] Meanwhile, in a non-insulation semiconductor device as one
of power semiconductor devices for use in inverters, etc., a member
used for fixing a semiconductor element serves also as one
electrode of a semiconductor device. For example, in a
semiconductor device including a power transistor mounted on a
fixing member (made of, e.g., a copper-cuprous oxide composite
material) by using an Sn--Pb brazing paste, the fixing member (base
material) serves also as a collector electrode of the power
transistor.
[0017] In actual operation, a collector current of several amperes
or more flows, whereupon a transistor chip generates heat. To avoid
the generated heat from causing instability of characteristics and
shortening of the life, the base material is required to have
superior heat dissipation and to ensure reliability in a brazed
portion. Then, ensuring reliability in the brazed portion requires
matching in thermal expansion rate between the semiconductor
element and the fixing member.
[0018] Also in an insulation semiconductor device, from the
viewpoint of realizing the safe and stable operation of the
semiconductor element, it is required to efficiently dissipate the
heat generated during the operation of the semiconductor device to
the outside of a package, and to ensure reliability in the brazed
portion.
[0019] To clear those conditions, JP-A-8-11503) discloses a
semiconductor current controller in which an assembly obtained by
mounting a Si chip on a Cu-coated AlN board is integrally brazed to
a support member made of Mo by using a solder. With this disclosed
technique, since the Cu-coated AlN board is soldered to the Mo
support member having a thermal expansion rate (5.1 ppm/.degree.
C.) comparable to that of the Cu-coated AlN board, a soldered
portion between both the members has superior reliability.
[0020] Patent Reference 3 (JP,B 7-26174) discloses a semiconductor
module device in which an assembly obtained by mounting a thyristor
chip on an alumina board is mounted to a support member made of a
composite material in which SiC ceramic powder is dispersed in Al
or an Al alloy. With this disclosed technique, since the alumina
board is mounted to the support member made of the Al/SiC composite
material having a thermal expansion rate (2 to 13 ppm/.degree. C.)
comparable to that (7.5 ppm/.degree. C.) of the alumina board, a
bonded portion between both the members has superior
reliability.
SUMMARY OF THE INVENTION
[0021] A known semiconductor module has a small size. For example,
a body of the semiconductor module 206 comprising the heat
radiating flange 201 and the cap 203, as shown in FIG. 15, has
dimensions of 21 mm length, 10 mm width and 3.7 mm height.
[0022] However, the semiconductor module 206 has the fins 205 for
face fixing, which are disposed at a module periphery and each of
which has a length of, e.g., about 2 mm. The fins 205 for face
fixing are positioned at three sides of the high-frequency power
module 206. Therefore, the presence of the fins 25 hinder a further
reduction of a mounting area.
[0023] Also, bonding wires for connecting the active parts and the
external wiring to each other hinder a reduction of the height of
the semiconductor module and hence a further reduction of the
thickness.
[0024] Moreover, in the heat radiating module disclosed in the
above-cited publication, an Sn-based solder is used to bond not
only the circuit board and the circuit part together, but also the
circuit part and the mother circuit board together. It is therefore
difficult to set the bonding temperatures for them in a
hierarchical way.
[0025] On the other hand, in the semiconductor device mounting the
power semiconductor element thereon, because an Sn-based material
having a relatively low melting point, such as an Sn-Pb eutectic
material, is used as the solder, the semiconductor device cannot be
employed under environment at high temperatures (not lower than,
e.g., 180.degree. C.).
[0026] It is an object of the present invention to provide an
electronic part mounting method, a semiconductor module, and a
semiconductor device, which can reduce a mounting area and a device
thickness.
[0027] Another object of the present invention is to provide an
electronic part mounting method, a semiconductor module, and a
semiconductor device, which will not impair reliability for a long
term even under environment at high temperatures.
[0028] According to one aspect, the present invention provides an
electronic part mounting method for bonding an electrode formed on
a substrate and an electrode formed on an electronic part to each
other, the method comprising the step of bonding both the
electrodes through a metal layer made up of aggregated particles of
at least one kind of metal. Then, the metal particles have an
average particle size of 1 to 50 nm. Preferably, the metal
particles form a metal layer having a thickness of 5 to 100
.mu.m.
[0029] Preferably, the metal particles are made of Au, an Au alloy,
Ag, and/or an Ag alloy.
[0030] Preferably, the metal particles comprise cores and coatings
formed on core surfaces. The cores may be Ni particles and the core
surfaces may be plated with Au, an Au alloy, Ag, and/or an Ag
alloy. Instead of the Ni particles, the cores may be particles
having characteristics causing neither deformation nor
decomposition even under temperatures applied in drying and bonding
steps performed after coating the particles on core surfaces. As an
alternative, the cores may be Cu particles, core surfaces may be
plated with Ni, and Ni-plated surface layers may be plated with Au,
an Au alloy, Ag, and/or an Ag alloy. Instead of the Cu particles,
the cores may be particles having characteristics causing neither
deformation nor decomposition even under temperatures applied in
drying and bonding steps performed after coating the particles on
core surfaces.
[0031] According to another aspect, the present invention provides
an electronic part mounting method comprising the steps of coating
a liquid containing metal particles, which are made of at least one
kind of metal selected from among Au and Ag and have an average
particle size of 1 to 50 nm, on a substrate having an electrode
with a metal layer of Au or an Au alloy formed on an electrode
surface; heating the liquid after the coating step, thereby forming
an area made of aggregated metal particles on the electrode surface
layer of Au or an Au alloy; and cooling the substrate after the
heating step, placing an electronic part on the area made of the
aggregated metal particles, and reheating the area at 50 to
300.degree. C. to bond the metal particles and the electronic part,
thereby electrically connecting the electrode on the substrate and
the electronic part.
[0032] According to still another aspect, the present invention
provides an electronic part mounting method comprising the steps of
forming a water repellent layer on a substrate having an electrode
on a substrate surface; forming an area where the water repellent
layer is removed, at a predetermined position corresponding to the
electrode; coating a liquid containing metal particles, which are
made of at least one kind of metal selected from among Au and Ag
and have an average particle size of 1 to 50 nm, in the area where
the water repellent layer is removed; heating the liquid after the
coating step, thereby forming an area made of aggregated metal
particles on the electrode having a surface layer of Au or an Au
alloy; and cooling the substrate after the heating step, placing an
electronic part on the area made of the aggregated metal particles,
and reheating the area at 50 to 300.degree. C. to bond the metal
particles and the electronic part, thereby electrically connecting
the electrode on the substrate and the electronic part.
[0033] Preferably, the water repellent layer is made of an
amorphous fluorine-containing polymer having, in a molecule
thereof, a perfluoro-polyether chain and an alkoxy silane residual
group, or fluoro-alkyl chain and an alkoxy silane residual group.
Alternatively, the water repellent layer is made of an amorphous
fluorine-containing polymer having, in a molecule thereof, a
perfluoro-polyether chain and an alkoxy silane residual group, or
fluoro-alkyl chain and an alkoxy silane residual group.
[0034] According to still another aspect, the present invention
provides an electronic part mounting method comprising the step of
forming a recess on one surface of a substrate; forming, on a
bottom surface of the recess, a metal layer made up of at least one
kind of metal particles that have an average particle size of 1 to
50 nm and are selected from among Au, an Au alloy, Ag, and an Ag
alloy; and connecting the substrate and a terminal provided on one
surface of an electronic part to each other through the metal
layer.
[0035] According to still another aspect, the present invention
provides a semiconductor module wherein an electrode formed on a
substrate and an electrode formed on an electronic part are bonded
to each other through a metal layer made up of aggregated particles
of at least one kind of metal. Preferably, an electrode formed on a
substrate and an electrode formed on an electronic part are bonded
to each other through a metal layer made up of particles being made
of at least one kind of metal selected from among Au and Ag and
having an average particle size of 1 to 50 nm.
[0036] According to still another aspect, the present invention
provides a semiconductor module having a structure in which a
plurality of semiconductor elements are connected through a first
connecting material to a substrate having an electrode formed
thereon, and the substrate is connected to an external mounting
board through a second connecting material, the second connecting
material being a metal layer made up of aggregated particles of at
least one kind of metal selected from among Au and Ag. Preferably,
the first connecting material is one of a brazing material
containing Sn as a main component and a lead-free solder
material.
[0037] According to still another aspect, the present invention
provides a semiconductor device wherein an electrode formed on a
substrate surface and an electrode formed on an electronic part
surface are bonded to each other through a metal layer made up of
particles having an average particle size of 1 to 50 nm and having
an average particle size of 1 to 100 .mu.m, the particles being
made of at least one kind of metal selected from among Au and Ag.
In the semiconductor device, preferably, the metal particles having
an average particle size of 1 to 100 .mu.m are formed by coating
layers of Au or an Au alloy on surfaces of nickel particles, or the
minute particles having an average particle size of 1 to 50 nm are
coupled to surfaces of the particles having an average particle
size of 1 to 100 .mu.m.
[0038] Thus, the present invention can provide the electronic part
mounting method, the semiconductor module, and the semiconductor
device, which can reduce a mounting area and a device
thickness.
[0039] Also, the present invention can provide the electronic part
mounting method, the semiconductor module, and the semiconductor
device, which will not impair reliability for a long term even
under environment at high temperatures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0040] FIG. 1 is a schematic view showing the construction of a
semiconductor module according to one embodiment;
[0041] FIG. 2 is a vertical sectional view showing the partial
detailed structure of the semiconductor module according to one
embodiment;
[0042] FIG. 3 is an enlarged view of bonded portions between a
MOSFET device and a substrate shown in FIG. 2;
[0043] FIGS. 4(a) to 4(i) show a production flow covering steps
from mounting of the MOSFET device onto a glass-ceramic substrate
to mounting of the glass-ceramic substrate onto a circuit
board;
[0044] FIG. 5 is an enlarged view of bonded portions between the
MOSFET device and the substrate;
[0045] FIG. 6 is a vertical sectional view of a semiconductor
element, showing one example in which an aggregated layer is
employed as a bonding layer;
[0046] FIGS. 7(a) to 7(d) show a flow of successive steps for
mounting of the MOSFET device on the glass-ceramic substrate.
[0047] FIG. 8 is a circuit block diagram of a cellular phone in
which the semiconductor module according to one embodiment is
employed;
[0048] FIGS. 9(a) and 9(b) show the structure of an insulation
semiconductor device according to another embodiment of the present
invention;
[0049] FIG. 10 shows a sub-assembly of the insulation semiconductor
device, shown in FIG. 9, according to another embodiment of the
present invention;
[0050] FIGS. 11(a) and 11(b) are a plan view and a sectional view,
respectively, for explaining a ceramic insulation substrate in
detail;
[0051] FIG. 12 is a circuit diagram of the insulation semiconductor
device according to another embodiment;
[0052] FIG. 13 is a schematic view of an insulation wiring board
showing still another embodiment of the present invention;
[0053] FIG. 14 is a schematic view of an insulation wiring board
showing still another embodiment of the present invention;
[0054] FIG. 15 shows a known semiconductor module;
[0055] FIG. 16 is a schematic view showing a sub-assembly of an
insulation semiconductor device according to still another
embodiment of the present invention;
[0056] FIG. 17 is a schematic enlarged sectional view of bonded
portions among a semiconductor element, a terminal and a patterned
wire shown in FIG. 16;
[0057] FIG. 18 is an enlarged view of bonded portions between the
semiconductor element and the substrate;
[0058] FIG. 19 is an enlarged view of bonded portions between the
semiconductor element and the substrate according to another
embodiment;
[0059] FIG. 20 contains a perspective view and a schematic
sectional view showing still another embodiment of the present
invention;
[0060] FIG. 21 shows a sectional view along the line of B-B' of
FIG. 20; and
[0061] FIG. 22 shows a production flow for mounting of the
semiconductor device to an organic multilayered substrate.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0062] Embodiments of the present invention will be described below
with reference to the accompanying drawings.
First Embodiment
[0063] FIG. 1 is a schematic view showing the construction of a
semiconductor module 100 according to one embodiment of the present
invention, and FIG. 2 is a vertical sectional view taken along a
line A-A' in FIG. 1. The semiconductor module 100 of this
embodiment has a thickness of about 0.45 mm.
[0064] Referring to FIGS. 1 and 2, a glass-ceramic substrate 1 is
of a multilayered structure in which patterned wires 107 for
transmission are formed between multiple layers and passive parts
111, such as capacitors, resistances and inductors, are formed on
the substrate. Also, the substrate 1 has a recess 102 in which a
MOSFET device 101 (hereinafter referred to simply as the "MOSFET")
made of a semiconductor material is to be mounted.
[0065] The substrate 1 is mounted on a circuit board 103. Au bumps
104 are used for electrical connection between the MOSFET 101 and
the substrate 1, and are each made up of Au particles having an
average particle size of 5 nm. Electrodes 108 are formed on the
circuit board 103 and are electrically connected to the substrate 1
through Sn-based brazing pastes 106. On the substrate 1, the
passive parts 111, such as capacitors, solenoids and resistances,
are mounted through metallic brazing pastes (not shown). An epoxy
resin 110 covers the passive parts 111, such as capacitors,
solenoids and resistances, and the MOSFET 101, all of which are
mounted on the substrate 1.
[0066] FIG. 3 is an enlarged view of bonded portions between the
MOSFET 101 and the substrate 1 shown in FIG. 2, the view showing
the bonded portions given by the Au bumps 104 in more detail. The
Au bumps 104 are each made up of Au particles having an average
particle size of 5 nm and cover electrodes 501. The electrodes 501
formed on the substrate 1 are made of Ni, have surfaces coated with
Au, and are connected to the patterned wires 107 inside the
substrate 1. The surfaces of electrodes 502 formed on the MOSFET
101 are coated with Au.
[0067] The semiconductor module in this embodiment means an
assembly comprising the MOSFET 101, the substrate 1 on which the
MOSFET 101 is mounted, the passive parts 111, such as capacitors,
solenoids and resistances, which are mounted on the substrate 1,
and the epoxy resin 110 covering the passive parts 111 and the
MOSFET 101, all of which are mounted on the substrate 1.
[0068] A method of manufacturing the semiconductor module of this
embodiment will be described below with reference to FIGS. 1 and
2.
[0069] The glass-ceramic substrate 1 (with a thickness of 0.30 mm)
of the multilayered structure including the patterned wires for
transmission and the passive parts, as described above, is prepared
by sintering. The recess 102 (see FIG. 2) having a size sufficient
to allow mounting of the MOSFET 101 therein is formed in the
glass-ceramic substrate 1 at the same time when the glass-ceramic
substrate 1 is processed.
[0070] The electrodes 501 are formed on a MOSFET mounting surface
in the recess 102 and have surfaces plated with Au. On the surface
of the glass-ceramic substrate 1 on which the passive parts 111,
such as capacitors, solenoids and resistances, are to be mounted,
there are formed electrodes for mounting of the passive parts 111,
such as capacitors, solenoids and resistances, in respective
corresponding positions.
[0071] With reference to FIGS. 4(a) to 4(i), a description is now
made of a production flow covering steps from mounting of the
MOSFET 101 onto the glass-ceramic substrate 1 to mounting of the
glass-ceramic substrate 1 onto the circuit (wiring) board 103.
[0072] First, a solution 104A containing Au particles having an
average particle size of 5 nm is coated by the ink jet method over
the Ni electrodes 501, which are formed on the MOSFET mounting
surface in the recess 102 of the glass-ceramic substrate 1 and have
surfaces coated with Au (FIGS. 4(a) and 4(b)). Then, by drying the
coated solution, convex electrodes (bumps) 104 each made up of the
Au particles are formed respectively on the Ni electrodes (FIG.
4(c)). In the drying step, heat may be applied, as required, at
temperatures in the range of about 30.degree. C. to 80.degree.
C.
[0073] The MOSFET 101 is placed on the Au bumps and is fixedly
mounted in the recess 102 of the glass-ceramic substrate 1 to
establish electrical connection (FIGS. 4(d) and 4(e)). In this
step, heat is applied at temperature of about 80.degree. C. for 60
minutes. Next, the passive parts, such as capacitors, solenoids and
resistances, are placed in predetermined positions on the
glass-ceramic substrate 1 (FIG. 4(f)) with intervention of brazing
pastes (solders) containing 90 percent by weight of Pb and 10
percent by weight of Sn therebetween. These brazing pastes
containing Pb as a main component have a higher melting point than
brazing pastes, which contain Sn as a main component and are used
for mounting the glass-ceramic substrate onto the circuit
board.
[0074] Then, the passive parts 111, such as capacitors, solenoids
and resistances, are brazed at temperature of about 330.degree. C.
(FIG. 4(g)). Subsequently, the epoxy resin 110 is poured over the
passive parts 111, such as capacitors, solenoids and inductors,
which nave been mounted on the glass-ceramic substrate 1, by using
a predetermined mold. In such a condition, the epoxy resin 110 is
solidified at high temperature of about 120.degree. C.
[0075] Then, Sn-based brazing pastes 106 are coated by screen
printing over electrodes 108 of the circuit (wiring) board 103,
which correspond to an area for mounting of the glass-ceramic
substrate 1 on the circuit board. The thickness of the Sn-based
brazing pastes applied at that time is about 500 .mu.m. Next, the
glass-ceramic substrate 1 including the MOSFET mounted thereon is
placed in a predetermined position with precise alignment on the
circuit board 103 on which the Sn-based brazing pastes have been
printed. Following that, the assembly passes through a reflow
furnace at a peak temperature of about 250.degree. C. (FIG. 4(h)).
As a result, the mounting of the glass-ceramic substrate 1
including the MOSFET mounted thereon to the circuit board 103 is
ended, and a high-frequency power module of this embodiment is
completed (FIG. 4(i)).
[0076] In this embodiment, because the brazing pastes used for
mounting the passive parts 111, such as capacitors, solenoids and
resistances, are brazing pastes containing Pb as a main component
and having a higher melting point than the Sn-based brazing pastes,
the former brazing pastes are never remelted in the step of
mounting the glass-ceramic substrate 1.
[0077] Alternatively, as in the MOSFET mounting, the passive parts
111 may be each connected by using an Au nano-particle layer
instead of the Pb-based brazing paste. In this case, the MOSFET and
the passive parts 111 are mounted at the same time. It is
preferable that the high-frequency power module has a lower height
than any other parts mounted on the same circuit board 103.
[0078] To protect the MOSFET against mechanical impacts and
chemical changes caused by moisture, etc., a resin is preferably
filled in the recess 102 of the glass-ceramic substrate 1 in which
the MOSFET is mounted.
[0079] Note that FIGS. 1 to 4 show one embodiment of the present
invention, and the layout of the various elements is not limited to
the illustrated one.
[0080] Additionally, an active part, such as the MOSFET, may be
mounted in plural number.
[0081] In this embodiment, the glass-ceramic substrate 1 may be
replaced with any of other suitable multilayered substrates made of
alumina, aluminum nitride, glass, and organic materials. Also, in
this embodiment, the recess 102 is not always required to be formed
in an area of the substrate where an integrated circuit device
(such as a MOSFET) is mounted. Further, the semiconductor module
may be covered with a cap made of a metal or resin instead of
pouring the epoxy resin.
[0082] The bumps 104 each made up of Au nano-particles may be
formed on electrodes of the integrated circuit device (MOSFET). In
this case, aggregated layers of the Au nano-particles are formed as
shown in FIG. 5. FIG. 5 is an enlarged view of bonded portions
between the MOSFET 101 and the substrate 1 in that case, the view
showing the bonded portions given by the Au bumps 104 in more
detail.
[0083] More specifically, the Au bumps 104 are each made up of Au
particles having an average particle size of 5 nm. The Ni
electrodes 501 are formed on the substrate 1, have surfaces coated
with Au, and are connected to the patterned wires 107 inside the
substrate 1. The surfaces of electrodes 502 formed on the MOSFET
101 are coated with Au. The Au bumps 104 are formed so as to cover
the electrodes 502, respectively.
[0084] As described above, the present invention is based on the
mounting technique utilizing a novel natural phenomenon that Au
nano-particles aggregate on an Au electrode. A resulting aggregated
layer is employed as a bonding layer. In this connection, because
the semiconductor device, such as the MOSFET, can be bonded to and
mounted on the substrate without applying a load, it can be bonded
even to electrodes in an active area where wiring required to
constitute an electronic circuit for the semiconductor element is
already formed.
[0085] FIG. 6 represents one example of that case. Electrode pads
604 having Au-coated surfaces are formed over an entire active area
of a semiconductor element 602 and are connected, through bumps 606
each made up of Au nano-particles, to electrode pads 610, which are
formed on a substrate 608 and have Au-coated surfaces. Steps of
forming the bumps each made up of Au nano-particles and connecting
the semiconductor element and the substrate to each other are
performed in the same manners as those described above.
[0086] Thus, it is possible to arrange bonding electrodes, which
have been disposed outside the active area in the past, within the
active area, and to realize a size reduction of a semiconductor
element, a smaller mounting area, and hence a semiconductor device
and an electronic unit each having a reduced thickness. Further,
there is no risk of damages caused in the bonding step. This
results in a remarkable increase of production yield. Also, in a
nano-particle bonding method according to the present invention,
the nano-particle layer constituting the bonding layer exhibits
properties of a solid metal or a solid metal alloy, and has a high
melting point comparable to those of Au and Ag. Therefore, the
bonding layer is never remelted at the bonding (mounting)
temperature described above. Hence, even when solder pastes having
a high melting point are used to mount the glass-ceramic substrate
1 on the circuit board 103 as in this embodiment, the bonding layer
are avoided from remelting. In the case of solid-phase bonding with
Au bumps formed by the plated bump or stud bump method, a
mechanical external force (attributable to pressing or ultrasonic
vibration) must be applied in the bonding step. Bonding of the
semiconductor element onto the active area is therefore infeasible
because of a risk of bonding damages.
[0087] While this embodiment employs the solder pastes having a
high melting point to mount the glass-ceramic substrate 1 on the
circuit board 103, nano-particle aggregated layers may be used
instead of those solder pastes. By using the nano-particle
aggregated layers of the present invention in a secondary mounting
step of mounting the glass-ceramic substrate 1 on the circuit board
103, the connection between both the components can be established
at temperatures as low as about 80.degree. C., and there is no fear
of remelting of the solder pastes used to mount the semiconductor
element, such as the MOSFET, on the substrate. Accordingly, solder
pastes having relatively low melting points can be used as the
solder pastes in the primary mounting step, thus resulting in a
wider range of options in selecting brazing materials.
[0088] In the past, when a lead-free solder paste is used, there
has been a difficulty in setting the mounting temperature in the
secondary mounting step to be lower than the melting point of the
lead-free solder paste, and there has been a problem of causing
remelting in the secondary mounting step. By using the
nano-particle aggregated layer of the present invention as a
connecting material for use in the secondary mounting step, it is
possible to eliminate the fear of remelting in the secondary
mounting step, and to employ the lead-free solder paste as the
brazing material for use in the primary mounting step.
[0089] The mounting form of the semiconductor element onto the
substrate is not limited to the flip-chip structure as described
above in this embodiment, and the semiconductor element and the
substrate may be connected to each other by wire bonding, etc.
Also, the nano-particle aggregated layer of the present invention
may be applied to both of the connecting material for use in the
primary mounting step and the connecting material for use in the
secondary mounting step. In this case, because the connection can
be established at relatively low temperatures, thermal strains
caused in the components, such as the substrate and the
semiconductor element, can be suppressed. Furthermore, the
nano-particle aggregated layer is superior in corrosion resistance
and contributes to obtaining a semiconductor device with high
reliability in connection.
[0090] Thus, the nano-particle aggregated layer of the present
invention is applicable to any connecting members for use in
electronic circuit devices. Also, the semiconductor devices to
which the present invention can be applied cover various types
including a high-frequency module, a multi-chip module
(system-in-package), a ball grid array, and a-chip mounting.
Second Embodiment
[0091] A method of manufacturing the semiconductor module of this
second embodiment will be described with reference to FIGS. 1 and
2.
[0092] The glass-ceramic substrate 1 (with a thickness of 0.30 mm)
of the multilayered structure including the patterned wires for
transmission and the passive parts formed therein is prepared by
sintering. The recess 102 having a size sufficient to allow
mounting of the MOSFET 101 therein is formed in the glass-ceramic
substrate 1 at the same time when the glass-ceramic substrate 1 is
processed.
[0093] The depth of the recess 102 is set such that a rear surface
of the MOSFET 101 is flush with the surface of the glass-ceramic
substrate 1 on the MOSFET mounting side. Metallic patterned wires
are formed on a MOSFET mounting surface in the recess 102 and have
surfaces plated with Au. On the surface of the glass-ceramic
substrate 1 on which the passive parts 111, such as capacitors,
solenoids and resistances, are to be mounted, there are formed
electrodes and patterned wires for mounting of the passive parts
111, such as capacitors, solenoids and resistances, in respective
corresponding positions.
[0094] A flow of successive steps for mounting the MOSFET on the
glass-ceramic substrate 1 will be described below with reference to
FIGS. 7(a), to 7(d), which schematically show, in an enlarged
scale, the recess 102 of the glass-ceramic substrate 1.
[0095] First, a water repellent (hydrophobic) layer 310 is formed
on the MOSFET mounting surface in the recess 102 of the
glass-ceramic substrate 1. The water repellent layer is made of,
e.g., an amorphous fluorine-containing polymer that has, in its
molecule, a perfluoro-polyether chain and an alkoxy silane residual
group, or fluoro-alkyl chain and an alkoxy silane residual
group.
[0096] Then, a laser exposure is applied to peel off water
repellent films on the Ni electrodes 501 having the Au-coated
surfaces, which are formed on the MOSFET mounting surface in the
recess 102 of the glass-ceramic substrate 1, so that a hydrophilic
area 312 is formed only on the Au-coated Ni electrodes 501 (FIG.
7(a)).
[0097] Then, a solution 104A containing Au particles having an
average particle size of 5 nm is coated by the ink jet method (FIG.
7(b)). By drying the coated solution, convex electrodes (bumps) 104
each made up of the Au particles are formed respectively on the Ni
electrodes 501. In the drying step, heat may be applied, as
required, at temperatures in the range of about 30.degree. C. to
80.degree. C. (FIG. 7(c)). The MOSFET 101 is placed on the Au bumps
and is fixedly mounted in the recess 102 of the glass-ceramic
substrate 1 to establish electrical connection. In this step, heat
is applied at temperature of about 80.degree. C. for 60 minutes for
positive mounting of the MOSFET 101.
[0098] A high-frequency power module of this embodiment is
completed by performing subsequent steps of the production flow
until the passive parts 111 and the glass-ceramic substrate 1 are
mounted on the circuit board 103 in the same manners as those in
the first embodiment. In this second embodiment, the glass-ceramic
substrate 1 may be replaced with any of other suitable multilayered
wiring substrates made of alumina, aluminum nitride, glass, and
organic materials. Also, the recess 102 is not always required to
be formed in an area of the substrate where an integrated circuit
device (such as an MOSFET) is mounted. Further, the semiconductor
module may be covered with a cap made of a metal or resin instead
of pouring the epoxy resin.
[0099] The bumps each made up of Au nano-particles may be formed on
electrodes of the integrated circuit device (MOSFET).
[0100] According to this second embodiment, as described above, Au
nano-particles are caused to locally aggregate by using water
repellent layer, and the bonding layer is formed in a shorter time.
As a result, this embodiment is effective in reducing the size of
an electronic device, increasing production yield with elimination
of damages possibly caused in the bonding portions, and realizing
higher productivity with shortening of the production time.
Third Embodiment
[0101] In this third embodiment, the Au bumps used in the first and
second embodiments are replaced with Ag bumps. The embodiments
described above are each applicable to manufacturing of a
high-frequency power amplifier that is used in a transmitting unit
of a cellular cell, etc.
[0102] FIG. 8 is a circuit block diagram of a cellular phone in
which the semiconductor module according to the embodiment is
employed. A voice input signal inputted from a microphone 10 is
superimposed in a mixer 12 on a high-frequency signal from an
oscillator 14, and then transmitted as an electric wave from an
antenna 20 through an insulation semiconductor device (MOSFET) 16,
which serves as a power amplifier, and an antenna sharing unit
18.
[0103] Transmission power is monitored by a coupler 22 and the
monitored power is fed back to the insulation semiconductor device
16, which serves as a power amplifier, so that the transmission
power is kept constant. Electric waves in a band of 800 to 1000 MHz
are used in the illustrated cellular phone. While the above
embodiments of the present invention are described in connection
with the high-frequency power amplifier, the semiconductor module
100 of the present invention is not limited to the
above-described-embodiments. A signal received by the antenna 20 is
sent to a speaker 26 through a high-frequency receiver 22 and a
voice processing unit 24.
Fourth Embodiment
[0104] FIGS. 9(a) and 9(b) show the structure of an insulation
semiconductor device 1000 according to another embodiment of the
present invention. FIG. 9(a) is an upper plan view, and FIG. 9(b)
is a sectional view taken along a line A-A' in FIG. 9(a).
Semiconductor elements (MOSFET) 301 are mounted on a ceramic
insulation substrate 302, and the ceramic insulation substrate 302
is mounted on a base member 303. Then, an epoxy resin case 304,
bonding wires 305, and an epoxy resin cap 306 are attached in
place, followed by filling a silicone gel resin 307 in the
case.
[0105] In such a structure, the ceramic insulation substrate 302 is
bonded onto the base member 303 through a bonding layer 308 (with a
thickness of 100 .mu.m) made up of Au particles having an average
particle size of 5 nm. Also, eight MOSFET's 301 (with dimensions of
7 mm.times.7 mm.times.0.4 mm) made of Si are bonded onto copper
sheets 302a as components of the ceramic insulation substrate 302
through respective bonding layers 309 (with a thickness of 30
.mu.m) each made up of Au particles having an average particle size
of 5 nm.
[0106] The bonding established through the bonding layers 308 and
309 each made up of Au nano-particles is performed as follows.
First, a solution containing Au particles having an average
particle size of 5 nm is coated over both of the copper sheets 302a
(plated with Ni) of the ceramic insulation substrate 302 and the
base member 303.
[0107] Then, by drying the coated solution, the bonding layers each
made up of the Au nano-particles are formed on the copper sheets
302a (plated with Ni) and the base member 303. In the drying step,
heat may be applied, as required, at temperatures in the range of
about 30.degree. C. to 80.degree. C.
[0108] The semiconductor elements 301 and the ceramic insulation
substrate 302 are placed on the corresponding Au bonding layers for
connection to the ceramic insulation substrate 302 and the base
member 303, respectively. In this connecting step, heat is applied
at temperature of about 80.degree. C. for 60 minutes.
[0109] A gate electrode, an emitter electrode, etc. of each
semiconductor element 301 are connected to corresponding electrodes
(copper sheets) 302a, which are formed as an upper portion of the
ceramic insulation substrate 302, and terminals 310 attached to the
epoxy resin case 304 in advance by wire bonding, i.e., ultrasonic
bonding, through Al wires 305 each having a diameter of 300
.mu.m.
[0110] Numeral 311 denotes a thermistor for temperature detection,
which is brazed to relevant electrodes 302c by using a solder of
Sn--3 percent by weight Ag--0.5 percent by weight Cu. The
thermistor 311 is led to the exterior by wire bonding through the
Al wires 305 each having a diameter of 300 .mu.m, which connect the
corresponding electrodes 302c (see FIG. 11) and terminals 310.
[0111] The epoxy resin case 304 and the base member 303 are fixed
in place by filling a silicone bonding resin (not shown) in a space
between them. Recesses 306' are formed in thicker areas of the
epoxy resin cap 306, and holes 310' are formed in the terminals
310. Screws (not shown) for connecting the insulation semiconductor
device 1000 to an external circuit can be fitted to the recesses
306' and the holes 310'. The terminals 310 are each prepared by
punching and shaping a copper plate into a predetermined shape, and
then plating the copper plate with Ni. The terminals 310 are
attached to the epoxy resin case 304 in predetermined
positions.
[0112] FIG. 10 shows a sub-assembly of the insulation semiconductor
device 1000, shown in FIG. 9, according to another embodiment of
the present invention. The ceramic insulation substrate 302
including the semiconductor elements 301 is mounted on the
composite member 303 serving as the base member. The base member
303 has dimensions of 74 mm.times.43 mm.times.3 mm, and attachment
holes 303A (each having a diameter of 5.6 mm) are formed in a
peripheral portion of the base member 303. The base member 303 is
made of Cu and has a surface plated with Ni in thickness of 203
.mu.m.
[0113] The ceramic insulation substrate 302 is mounted on the base
member 303 through Au nano-particle layers, and the semiconductor
elements (MOSFET's) 301 are mounted on the ceramic insulation
substrate 302 through other Au nano-particle layers. Also, a water
repellent film 322 is formed on the base member 303 in an mounting
area for the ceramic insulation substrate 302 to prevent overflow
of the Au nano-particle containing solution when the solution is
applied.
[0114] Further, a water repellent film 321 is formed on the ceramic
insulation substrate 302 in mounting areas for the MOSFET's 301 to
prevent overflow of the Au nano-particle containing solution when
the solution is applied. The insulation semiconductor device 1000
is a device in a class operating at 100 V and 400 A.
[0115] FIGS. 11(a) and 11(b) are a plan view and a sectional view,
respectively, for explaining the ceramic insulation substrate 302
in detail. The ceramic insulation substrate 302 is prepared by
bonding, to both surfaces of an AlN-sintered member 220 (with a
thermal expansion rate of 4.3 ppm/.degree. C. and a thermal
conduction rate of 160 W/mK) having dimensions of 50 mm.times.30
mm.times.0.6 mm, sheets 302a (serving also as drain electrodes),
302b (serving also as source electrodes) and 302c (for mounting of
the thermistor) each having a thickness of 300 .mu.m and made of a
Cu--Cu.sub.2O composite material, as well as a sheet 302d having a
thickness of 250 .mu.m and made of a Cu--Cu.sub.2O composite
material by using Ag--Cu brazing pastes (each having, though not
shown, a thickness of 20 .mu.m).
[0116] The reason of using the Cu--Cu.sub.2O composite material as
a wiring material to form the respective electrode resides in
achieving matching with the thermal expansion rate of the
AlN-sintered member 302, and hence ensuring reliability for a long
term. Ni-plated coatings (not shown) each having a thickness of 2
.mu.m are formed respective surfaces of the sheets 302a, 302b, 302c
and 302d each made of the Cu--Cu.sub.2O composite material. As a
modification, the AlN-sintered member 302 can be replaced with a
sintered member of silicon nitride (with a thermal expansion rate
of 3.1 ppm/.degree. C. and a thermal conduction rate of 120
W/mK).
[0117] FIG. 12 is a circuit diagram of the insulation semiconductor
device of this embodiment. Two blocks 1001 each including four
MOSFET's 301 arranged in parallel are connected in series and have
input terminals Ain, output terminals Aout, etc. led out of the
blocks 1001 from respective predetermined positions. Further, the
thermistor 311 for detecting the temperature during the operation
of the circuit is independently disposed In the insulation
semiconductor device 1000.
[0118] According to this embodiment of the present invention, as
described above, a semiconductor element and a substrate can be
mounted respectively on the substrate and a target circuit board at
low temperatures through bonding layers each made up of Au
nano-particle layers. It is therefore possible to reduce
deformations of the substrate and the circuit board and residual
stresses caused in the bonding layers after the bonding when the
semiconductor element and the substrate are bonded at high
temperatures, and hence to increase reliability of the
semiconductor device.
[0119] Also, according to the nano-particle bonding method in this
embodiment of the present invention, the nano-particle layer
constituting the bonding layer behaves as a bulk material.
Therefore, the bonding layer is never remelted at the bonding
temperature described above. Hence, the nano-particle bonding
method can also be applied to semiconductor devices employing
semiconductor elements which are made of silicon carbide, gallium
nitride, etc. and are able to operate under environment at high
temperatures.
[0120] Further, this embodiment of the present invention employs
the mounting based on a novel natural phenomenon that metal
particles at a nano-size level aggregate on an electrode. When
bonding a semiconductor element and a wire-patterned substrate
through a resulting aggregated layer, the bonding can be
established at low temperatures without applying a load. As a
result, product reliability and production yield can be remarkably
increased without causing damages in the bonding step.
[0121] Moreover, since the bonding can be achieved with a low load,
a semiconductor element can be bonded onto an area where wiring for
the semiconductor element is already formed. Consequently, a
semiconductor device area can be reduced and hence a smaller-sized
electronic device can be provided.
[0122] The metal-particle aggregated layer (bonding layer) after
the bonding behaves as a bulk material in the form of a metal
particle material constituting the bonding layer. Accordingly, when
an electronic part mounting the semiconductor element thereon is
mounted on the circuit board in this embodiment of the present
invention, the joining layer is prevented from remelting even in
the case of using a solder paste containing Sn or Pb as a main
component. This also contributes to increasing the production
yield.
Fifth Embodiment
[0123] FIG. 13 is a schematic view of an insulation wiring board in
which a metal plate having a stress buffer effect is mounted on an
emitter electrode of a semiconductor element constituting an IGBT
(Insulated-Gate Bipolar-Power Transistor). More specifically, a
stress buffer plate 134 is connected to an emitter electrode of an
IGBT chip 132 through an Au nano-particle layer. The stress buffer
plate 134 is made of, e.g., Cu, a Cu--Cu.sub.2O composite material,
a Cu--Mo composite material, a Cu--W composite material, a
Cu-Invar-Cu laminated material, or a Cu--C composite material. It
is desirable that Ni is plated on the surface of the stress buffer
plate 134 and the thickness of a plated coating is in the range of
about 0.05 mm to 0.1 mm. The stress buffer plate 134 is bonded to
the emitter electrode by the same manner as described above.
[0124] Bonding wires 136 are each made of, e.g., pure Al, an Al--Si
alloy, or an Al--Si alloy mixed with Ni. In the structure described
above, since the stress buffer plate 134 is bonded at low
temperatures, residual strains caused between the stress buffer
plate 134 and the IGBT chip 132 made of Si. Further, when the IGBT
chip 132 including the stress buffer plate 134 bonded thereto is
mounted on a wiring board 138 through an Sn-based solder, the Au
nano-particle layer serving as a bonding layer between the IGBT
chip 132 and the stress buffer plate 134 is never remelted. In
addition, connecting the boding wires 136 to the stress buffer
plate 134 makes it possible to relieve thermal strains otherwise
caused between the Al-based wires and the Si chip, and to increase
the life of the connection of the bonding wires.
[0125] FIG. 14 is a schematic view of an insulation wiring board on
which a semiconductor element made of SiC is mounted. A
semiconductor chip 142 is mounted on an insulation wiring board 144
through an Au nano-particle layer. Bonding wires 146 connect the
semiconductor chip 142 and patterned wires 148 to each other. In
such a structure, since the semiconductor chip 142 is bonded at low
temperatures, residual strains caused between the insulation wiring
board 144 and the semiconductor chip 142 made of SiC are small.
Further, even when the insulation wiring board 144 is put under
environment at high temperatures of about 200.degree. C., the Au
nano-particle layer serving as a bonding layer between the
semiconductor chip 142 and the insulation wiring board 144 is never
remelted.
Sixth Embodiment
[0126] FIG. 16 is a schematic view showing a sub-assembly of an
insulation semiconductor device according to still another
embodiment of the present invention.
[0127] In this embodiment, semiconductor elements 401 and a ceramic
insulation substrate 402 are bonded through bonding layers 408 (see
FIG. 17) each made up of Au particles having an average particle
size of 5 nm. Also, an emitter electrode of each of the
semiconductor elements 401 is connected to a copper patterned wire
402b, which is formed on the ceramic insulation substrate 402 and
plated with Au and Ni, through a connecting terminal 431 by using
Au particle layers 409, 410 (see FIG. 17).
[0128] FIG. 17 is a schematic enlarged sectional view of mounting
portions of the semiconductor element shown in FIG. 16. The
connecting terminal 431 is formed of a copper sheet plated with Ni
and then Au on the Ni-plated surface. After bonding each
semiconductor element 401 onto a patterned wire 402a on the
insulation substrate 402, a solution containing Au particles having
an average particle size of 5 nm is coated over the emitter
electrode (on the upper side) of the semiconductor element 401.
Further, the Au-particle containing solution is also coated over an
Au-plated area of a copper patterned wire 402b on the insulation
substrate 402, which is formed by Ni-plating a copper wiring
pattern on the surface of the insulation substrate 402 and then
Au-plating an area of the copper wiring pattern to be connected to
the emitter electrode of the semiconductor element 401 through the
terminal 431. After drying the Au-particle containing solution
coated on both the emitter electrode of the semiconductor element
401 and the copper patterned wire 402b on the insulation substrate
402 to form electrodes made up of the Au particles, the connecting
terminal 431 is placed on and mounted to the electrodes made up of
the Au particles by applying at temperature of about 80.degree. C.
for 60 minutes, the connection between the semiconductor element
401 and the patterned wire 402b is completed. In an insulation
semiconductor device, a large current flows in not only a collector
electrode, but also en emitter electrode. By using the connecting
terminal 431 having a large wiring width, the connection
reliability on the emitter electrode side can be further
increased.
Seventh Embodiment
[0129] This seventh embodiment represents a modified example of the
bonding layers used in the first embodiment. The other structure
than Au bumps 104, i.e., bonding layers between the MOSFET 101 and
the substrate 1, and the method of manufacturing the module are the
same as those in the first embodiment.
[0130] FIG. 18 is an enlarged view of bonded portions between the
MOSFET 101 and the substrate 1 similar to those shown in FIG. 2,
the view showing the bonded portions given by the Au bumps 104 in
more detail. The Au bumps 104 are each made of a particle mixture
comprising Au particles having an average particle size of 5 nm and
Au particles having an average particle size of 20 .mu.m at a
volume ratio of 5:1, and they cover electrodes 501 made of Ni. The
Ni electrodes 501 are formed on the substrate 1, have surfaces
coated with Au, and are connected to the patterned wires 107 inside
the substrate 1. The surfaces of electrodes 502 formed on the
MOSFET 101 are coated with Au. In this embodiment, a layer made up
of Au particles having average particle sizes different from each
other is employed as the bonding layer. The bonding layer is
preferably formed as a layer made up of minute Au particles in the
range of 1 to 50 nm and relatively large Au particles in the range
of 1 to 100 .mu.m.
[0131] The bumps 104 each made up of Au particles in this
embodiment may be formed on electrodes of the integrated circuit
device (MOSFET). In this case, aggregated layers of the Au
particles are formed as shown in FIG. 19. FIG. 19 is an enlarged
view of bonded portions between the MOSFET 101 and the substrate 1
in that case, the view showing the bonded portions given by the Au
bumps 104 in more detail. The Au bumps 104 are each made of a
particle mixture comprising Au particles having an average particle
size of 5 nm and Au particles having an average particle size of 20
.mu.m at a volume ratio of 5:1. The Ni electrodes 501 are formed on
the substrate 1, have surfaces coated with Au, and are connected to
the patterned wires 107 inside the substrate 1. The surfaces of
electrodes 502 formed on the MOSFET 101 are coated with Au. The Au
bumps 104 are formed so as to cover the electrodes 502,
respectively.
[0132] This embodiment utilizes such properties that minute metal
particles having an average particle size of 1 to 5 nm tend to
aggregate together at temperatures lower than the melting point. By
mixing relatively large metal particles having an average particle
size of 1 to 100 .mu.m to the minute metal particles, an aggregated
layer can be formed in a larger thickness than the case of using
only the minute metal particles to form the bonding layer. When
there is a large difference in thermal expansion rate between an
electronic part and a substrate on which the electronic part is
mounted, a thicker bonding layer contributes to releasing thermal
stresses caused in the bonded portion due to the difference in
thermal expansion rate, and to increasing reliability in the bonded
portion.
[0133] Further, in the particle coating step, a thicker coating
layer can be formed as a result of mixing the relatively large
metal particles having an average particle size of 1 to 100 .mu.m.
Therefore, defects and other failures are hard to occur in the step
of forming the bonding layer, and the life of the bonded portion
can be further prolonged. The electrode surface of the substrate
and the electrode surface of the electronic part, which are used
for bonding between them, have unevenness due to the presence of
the patterned wires formed in respective inner layers. This raises
a fear that, when the bonding layer is thin, a non-bonded area may
occur between the electrode on the substrate and the electrode on
the electronic part. Moreover, the electrode on the substrate and
the electrode on the electronic part are deformed under influences
of the production steps, such as wiring formation and heat
treatment, performed in manufacturing the substrate and the
electronic part, whereby those electrodes are slightly deviated
from the same plane. There is hence a possibility that, when the
electrode on the substrate and the electrode on the electronic part
are connected to each other, some electrodes having lower heights
may remain not connected. To avoid those problems, the minute metal
particles having an average particle size of 1 to 5 nm and
relatively large metal particles having an average particle size of
1 to 100 .mu.m are used in a mixed form in this embodiment. By
mixing the metal particles having a relatively large average
particle size, the bonding layer can be coated and formed in a
relatively large thickness that has been difficult to obtain with
the case of using the minute metal particles, and troubles, such as
non-connection and defects in the connected portion, become harder
to occur.
[0134] The minute metal particles having an average particle size
of 1 to 50 nm can be made of at least one kind of metal or an alloy
consisting of two or more kinds of metals selected from among gold,
silver, copper, platinum, palladium, rhodium, osmium, ruthenium,
iridium, iron, tin, zinc, cobalt, nickel, chromium, titanium,
tantalum, tungsten, indium, silicon, and aluminum. In particular,
preferably, Au, an Au alloy, Ag, and an Ag alloy are used solely or
in a mixed form of two or more selected from among them. Also, the
relatively large metal particles having an average particle size of
1 to 100 .mu.m can be formed as particles, which are made of Au, an
Au alloy, Ag, and/or an Ag alloy, which are formed by plating the
surfaces of nickel particles, as cores, with Au, an Au alloy, Ag,
and/or an Ag alloy, or which are formed by plating the surfaces of
copper particles, as cores, with Ni and further plating the
surfaces of Ni-plated coating with Au, an Au alloy, Ag, and/or an
Ag alloy. Particles serving as cores can be made of not only a
metal, but also a plastic, such as polyimide or polyetherimde, so
long as it will neither deform nor decompose even under
temperatures applied in the drying and bonding steps performed
after coating the particles in a mixed form. In the latter case,
the plastic particles can be used through the steps of Ni-plating
the surfaces of those particles by the electroless plating method
or the electrolytic plating method after forming a conductive film
for the plating, and then plating, as in the case of the metal
particles, the surfaces of the Ni-plated particles with Au, an Au
alloy, Ag, and/or an Ag alloy.
[0135] To prevent individual particles from aggregating and
cohering together during storage or the coating step, the minute
metal particles and the relatively large metal particles are
handled and used in a state dispersed in water or a surfactant that
interacts with the surfaces of the individual particles and is
easily separable at the bonding temperature.
[0136] A paste containing the minute metal particles and the
relatively large metal particles in a dispersed state can be coated
over the electrodes on the substrate or the connected portions of
the electronic part by using any of the following methods, namely
an ink jet method of ejecting the paste through a thin nozzle; a
method of applying the paste to only required areas through a metal
mask or a mesh-like mask having openings corresponding to the areas
where the paste is to be coated; a method of applying the paste to
only required areas by using a dispenser; a method of applying a
water repellent resin containing silicone, fluorine or the like
through a metal mask or a mesh-like mask having opening
corresponding to only the required areas, or applying a
photosensitive or water repellent resin onto the substrate or the
electronic part and exposing or developing the applied resin to
remove it only in the required areas where the paste comprising the
minute metal particles and the relatively large metal particles is
to be coated, and then coating the bonding paste to the openings;
and a method of applying the water repellent resin onto the
substrate or the electronic part, removing the coated resin with a
laser only in the required areas where the paste comprising the
minute metal particles and the relatively large metal particles is
to be coated, and then coating the bonding paste to the openings.
Those coating methods can be used in a combined way depending on
the area and shape of the electrode to be bonded.
[0137] It is needless to say that similar advantages to those in
this seventh embodiment can also be obtained by employing the
bonding layer used in this seventh embodiment as the bonding layers
used in the second to sixth embodiments.
Eighth Embodiment
[0138] A method of manufacturing a semiconductor module according
to this eighth embodiment will be described below with reference to
FIGS. 20 and 21.
[0139] An organic multilayered substrate 600 (with a thickness of
0.30 mm) of the multilayered structure including patterned wires
for transmission formed therein is prepared. A recess 602 having a
size sufficient to allow mounting of a MOSFET therein is formed in
the organic multilayered substrate 600.
[0140] Metallic patterned wires are formed on a MOSFET mounting
surface in the recess 602 and have surfaces plated with Au. On the
surface of the organic multilayered substrate 600 on which passive
parts 611, such as capacitors, solenoids and resistances, are to be
mounted, there are formed electrodes and patterned wires for
mounting of the passive parts 611, such as capacitors, solenoids
and resistances, in respective corresponding positions.
[0141] A flow of successive steps for mounting of the MOSFET on the
organic multilayered substrate 600 will be described below with
reference to FIG. 22.
[0142] First, a solution 104A containing Au and Ag particles having
an average particle size of 5 nm is coated over the metallic
patterned wires 501 (serving also as the electrodes) that are
formed on the MOSFET mounting surface in the recess 602 of the
organic multilayered substrate 600 and have surfaces coated with
Au, thereby forming, on the electrodes, convex layers (bumps) each
made up of the Au and Ag particles (FIG. 21(a)). The MOSFET is
placed on the Au--Ag bumps and is fixedly mounted in the recess 602
of the organic multilayered substrate 600 (FIG. 21(b)). In this
step, heat is applied at temperature of about 80.degree. C. for 60
minutes for positive mounting of the MOSFET (FIG. 21(c)).
[0143] A high-frequency power module of this embodiment is
completed by performing subsequent steps of the production flow
until mounting of the passive parts 611 and the organic
multilayered substrate 600 onto a circuit board 603 in the same
manners as those in the first embodiment. In this eighth
embodiment, the organic multilayered substrate 600 may be replaced
with any of other suitable multilayered wiring substrates made of
alumina, aluminum nitride, glass, and glass ceramics. Also, the
recess is not always required to be formed in an area of the
substrate where an integrated circuit device (such as a MOSFET) is
mounted. Further, the semiconductor module may be covered with a
cap made of a metal or resin instead of pouring the epoxy resin.
The solder bonded portion may be performed by using solder balls as
in a ball grid array (BGA). A distribution ratio of Ag and Au is
not limited to a particular value.
[0144] As described above, this embodiment represents an example in
which the bonding layer made up of Au and Ag mixed minute particles
are locally provided, and the bonding can be achieved in a shorter
time. Au and Ag do not form a particular compound phase and remain
in a full solid solution state. Therefore, contact portions between
Au and Ag are free from bonding defects, and hence exhibit good
electrical conductivity and thermal conductivity. In addition, the
bonding layer containing Au is also effective in suppressing
electro-migration (ion migration) wherein Ag dissolves in the
component exuded from the packaged resin, water intruding from the
exterior, etc.
* * * * *