U.S. patent application number 11/746508 was filed with the patent office on 2007-09-06 for device having a redundant structure.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Birendra N. AGARWALA, Du Binh NGUYEN, Hazara Singh RATHORE.
Application Number | 20070205515 11/746508 |
Document ID | / |
Family ID | 38041474 |
Filed Date | 2007-09-06 |
United States Patent
Application |
20070205515 |
Kind Code |
A1 |
AGARWALA; Birendra N. ; et
al. |
September 6, 2007 |
DEVICE HAVING A REDUNDANT STRUCTURE
Abstract
Device with a damascene interconnect for integrated circuits
with improved reliability and improved electromigration properties.
The device including a dual damascene line having a metal line and
a via, and a redundant liner arranged to divide the metal line.
Inventors: |
AGARWALA; Birendra N.;
(Hopewell Junction, NY) ; NGUYEN; Du Binh;
(Danbury, CT) ; RATHORE; Hazara Singh;
(Stormville, NY) |
Correspondence
Address: |
GREENBLUM & BERNSTEIN, P.L.C.
1950 ROLAND CLARKE PLACE
RESTON
VA
20191
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
10504
|
Family ID: |
38041474 |
Appl. No.: |
11/746508 |
Filed: |
May 9, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11164223 |
Nov 15, 2005 |
|
|
|
11746508 |
May 9, 2007 |
|
|
|
Current U.S.
Class: |
257/758 ;
257/E21.577; 257/E21.585 |
Current CPC
Class: |
H01L 21/76805 20130101;
H01L 2924/0002 20130101; H01L 21/76847 20130101; H01L 21/76883
20130101; H01L 23/53238 20130101; H01L 23/53295 20130101; H01L
21/76877 20130101; H01L 2924/00 20130101; H01L 2924/0002
20130101 |
Class at
Publication: |
257/758 |
International
Class: |
H01L 23/52 20060101
H01L023/52 |
Claims
1. A device comprising: a dual damascene line comprising a metal
line and a via; and a redundant liner arranged to divide the metal
line.
2. The device in accordance with claim 1, further comprising: an
interlevel layer formed over the dual damascene line; and the
interlevel layer comprising at least one second metal line and at
least one second via, the at least one second via extending through
the redundant liner.
3. The device in accordance with claim 2, wherein the at least one
second via extends into the metal line arranged below the redundant
liner.
4. The device in accordance with claim 2, further comprising a cap
layer formed between the dual damascene line and the interlevel
layer.
5. The device in accordance with claim 1, further comprising: a
plurality of interlevel layers formed over the dual damascene
layer, wherein each interlevel layer includes at least one metal
line divided by a redundant liner and at least via; and each at
least one via extends through a structurally lower redundant
liner.
6. The device in accordance with claim 5, further comprising a
plurality of cap layers formed between each of the plurality of
interlevel layers.
7. The device in accordance with claim 1, further comprising at
least one hardmask formed on at least one of the plurality of
interlevel layers.
8. A device, comprising: a redundant liner structured and arranged
to divide a metal line of dual damascene line; and a trench having
at least a portion arranged to extend through the redundant liner.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application is a divisional of U.S. patent
application Ser. No. 11/164,223 filed Nov. 15, 2005, the disclosure
of which is expressly incorporated by reference herein in its
entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to an interconnect structure,
e.g., a damascene interconnect, for integrated circuits with
improved reliability and improved electromigration properties.
BACKGROUND DESCRIPTION
[0003] According to the known art, "fatwire" structure is a wiring
layout laid out with a metal line having thicker height and wider
width, e.g., thickness and pitch of 2.times., 4.times., 6.times.,
etc. of a thin wire, minimum ground rules dimensions. However, with
regard to electromigration effects, reliability of fatwire
structures with a larger pitch becomes worse than in a thin wire
structure. This inconsistent reliability is due to the fatwire
structure. In this regard, fatwire failure generally occurs at the
top of the metal line, i.e., near the surface of the stripe, and/or
at the bottom of the interlevel via. In the known structure, the
bottom of the via may not fully contact the sidewall liner.
Moreover, even when the via contacts the sidewall liner, the liner
is too thin to sustain all the current density of the fatwire.
[0004] A conventional process for forming a dual damascene line is
shown in FIGS. 1-4. In particular, a trench 12 is formed in a
substrate 11 into which a metal, e.g., copper or aluminum, is
provided, e.g., via electroplating, in order to form metal line Mx
and at least one via Vx. Substrate 11 may be, e.g., Si0.sub.2, a
low K organic material, a PCVD low dielectric material or other
suitable material having a thickness of 400 to 2500 angstroms,
metal line Mx may have a thickness in a range between 0.4-1.0
micron and a width of 0.2 to 1.0 micron, and via Vx may have a
depth of 0.4 to 1.0 micron from the bottom of Mx and a diameter of
0.2 to 0.4 micron. Moreover, substrate 11 may optionally be covered
by a hardmask layer 13, which can be, e.g., a PCVD oxide, SiCNH,
SiC, Si.sub.3N.sub.4, or other suitable material. Moreover, the
portion of hardmask 13 over trench 12 removed during the formation
of trench 12 is filled with metal Mx. Further, metal line Mx is
patterned by removing excess metal from the upper surface of
substrate 11 or optional hardmask 13, e.g., through chemical
mechanical polishing, to form a smooth upper surface.
[0005] In a next production step, a cap layer 14 is applied over
the top of substrate 11/hardmask 13 and metal line Mx. Cap layer 14
can be, e.g., SiN.sub.x, SiCNH, or other suitable cap layer
material for metal line Mx, and have a thickness of 200-1000
angstroms. A substrate or interlevel layer 15 is deposited onto cap
layer 14. Interlayer 15, like substrate 11, can be, e.g.,
Si0.sub.2, a low K organic material, a PCVD low k-dielectric
material or other suitable material having a thickness of 4000
(1.times.) to 24000 (6.times.). Optionally, a hardmask layer 16 can
be deposited onto the surface of interlevel layer 15. Hardmask
layer 16 can be, e.g., a PCVD oxide, SiCNH, or other suitable
material with a thickness of 300-2000 angstroms.
[0006] In a next step in the conventional process, as shown in FIG.
2, a dual damascene trench 17 is formed in interlevel layer 15 and
optional hardmask 16. Trench 17, which is formed by, e.g.,
lithography and etching, is composed of two portions: a first
portion 18 extending to a depth of 0.6-2 micron from the surface of
interlevel layer 15/hardmask 16 and a second portion 19 extending
from first portion 18 down through cap layer 14 to contact metal
line Mx.
[0007] As illustrated in FIG. 3, a liner 20 is deposited into
trench 17 in order to form a barrier layer having a thickness of
50-500 angstroms. Liner 20 can be, e.g., Ta, TaN, W, Ti, TiN, or a
combination of Ta, TaN, Ti, TiN, W or with other suitable material
to act as a barrier layer for the metal to be deposited in liner
20. Moreover, liner 20 can be formed from one or more of the
identified materials.
[0008] As noted above, and shown in FIG. 4, a metal, e.g., copper,
is deposited in trench 17, and more particularly liner 20, in order
to form metal line MQ in portion 18 of trench 17 and via VL in
portion 19 of trench 17. Further, in accordance with the
conventional process, wiring lines are patterned by removing excess
metal from metal line MQ from the upper surface of substrate 15 or
optional hardmask 16, e.g., through chemical mechanical polishing,
to achieve a smooth upper surface with a metal stripe.
SUMMARY OF THE INVENTION
[0009] The present invention is directed to a method of fabricating
a device. The method includes forming a trench in a metal stripe of
a dual damascene line, depositing a barrier layer in the trench,
and filling a remainder of the trench with metal.
[0010] Moreover, the present invention is directed to a device that
includes a dual damascene line having a metal line and a via, and a
redundant liner arranged to divide the metal line.
[0011] The instant invention is directed to a method for
fabricating an interconnect structure. The method includes forming
a trench in a substrate, depositing metal in the trench, forming a
second trench in the metal, depositing a redundant liner in the
second trench, and depositing metal in the second trench.
[0012] Still further, the invention is directed to a method of
forming a redundant device that includes forming a redundant liner
to divide a metal line of dual damascene line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIGS. 1-4 illustrate a conventional formation of a dual
damascene line (prior arts); and
[0014] FIGS. 5-10 illustrate the formation of a redundant fatwire
from the conventional dual damascene line depicted in FIG. 4 in
accordance with the features of the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENT INVENTION
[0015] The invention relates to a process for forming a wire from a
conventional dual damascene line. According to the invention, the
formed fatwire eliminates the line opens and improves reliability
(electromigration) by providing a longer lifetime and tighter sigma
than conventional fatwire structures.
[0016] According to the invention, the fatwire structure includes a
thin redundant liner in the fatwire interconnect structure to
isolate voids from underneath the via and to prevent such voids
from propagating upward above the redundant liner. As a result,
upward propagation of voids into the upper part of the metal layer
is prevented.
[0017] The via opening is etched through the redundant liner, which
increases the mechanical strength of the interconnect and
essentially eliminates any thermal cycle and/or stress migration
effects. Further, the depth of the via improves performance against
the electromigration effects by increasing contact surface around
the via.
[0018] The present invention increases the reliability of the
conventional dual damascene line shown in FIG. 4 by using a
redundant line. In particular, as illustrated in FIG. 5, a blanket
reactive ion etch (RIE) or a blanket wet etch is performed on the
metal stripe, e.g., copper, to remove a portion of the thickness of
metal line MQ to form metal line MQ'. However, the portion of
barrier layer 20 lying adjacent the removed thickness is not
removed, such that a trench 21 is formed between facing portions of
barrier layer 20 and between an upper surface of metal line MQ' and
the upper surface of interlevel layer 15/hardmask 16. Trench 21 can
be up to one-half of the thickness of metal line MQ, may be at
least 100 angstroms, and preferably, is between 10-30% of the
thickness of metal line MQ.
[0019] After formation of trench 21, a barrier layer (redundant
liner) 22, as shown in FIG. 6, is deposited onto the surface of
interlevel layer 15/hardmask 16, as well as into and along the
sides of trench 21. Barrier layer 22 can have a thickness of 50-500
angstroms, preferably 50-100 angstroms, and be formed of, e.g., Ta,
TaN, W, Ti, TiN, or other suitable material to act as a diffusion
barrier layer for the metal to be deposited in barrier layer 22.
Moreover, layer 22 can be formed from one or more of the identified
materials. Thereafter, a metal, e.g., copper, is deposited into
trench 21, and more particularly into barrier layer 22, in order to
form metal line MQ''.
[0020] As shown in FIG. 7, a wiring line is patterned by removing
excess metal from metal line MQ' and portions of barrier layer 22
from the upper surface of substrate 15 or optional hardmask 16,
e.g., through chemical mechanical polishing, to achieve a smooth
upper surface with a metal stripe. Thus, barrier layer 22 forms a
redundant layer in the middle of the fatwire, i.e., between metal
lines MQ' and MQ''.
[0021] In a next production step, as illustrated in FIG. 8, a cap
layer 24 is applied over the top of substrate 15/hardmask 16 and
the metal stripe patterned from metal line MQ''. Cap layer 24 can
be, e.g., SiNx, SiCNH, or other suitable cap layer material for
metal line Mx, and have a thickness of 200-1000 angstroms. A
substrate or interlevel layer 25 is deposited onto cap layer 24.
Interlayer 25, like substrates 11 and 15, can be, e.g., Si0.sub.2,
a low K organic material, a PCVD low k-dielectric material or other
suitable material having a thickness of 5000 to 24000 angstroms.
Again, an optional hardmask layer (not shown) can be deposited onto
the surface of interlevel layer 25 in the manner set forth
above.
[0022] As illustrated in FIG. 9, a trench 27 is formed in
interlevel layer 25, e.g., by lithography and etching, and is
composed of two portions: a first portion 28 extending to a depth
of 0.6-2 microns from the surface of interlevel layer 25 and a
second portion 29 extending from first portion 28 down through at
least barrier (redundant) layer 22 in order to create the desired
redundance. Subsequently, a layer (liner) is deposited into trench
27, followed by deposition of metal into trench 27, or more
specifically, into the liner within trench 27, in order to form
metal line LN and via VQ, as shown in FIG. 10. Moreover, a portion
of metal line LN can be etched so that a redundant liner can be
placed within the etched portion, and then deposited with metal.
The wiring line can be patterned by chemical mechanical polishing
to provide a smooth surface and metal strip. This procedure can be
repeated a number of time, e.g., 8-9 times, depending upon the
particular interconnect design.
[0023] In this manner, via VQ is etched through cap layer 24,
barrier layer 22, and into MQ'. Thus, via VQ can be, e.g., a depth
deeper than one-half the thickness of the fatwire. Moreover,
barrier layer 22 additionally forms a redundant layer between metal
lines MQ' and LN.
[0024] As a result of this construction, barrier layer 22 will
prevent any voids from underneath via VQ from propagating upward to
metal line MQ''. Further, the depth of via VQ will improve
performance by increasing the contact surface around via V2, and
improve reliability by having a longer lifetime and tighter sigma.
This type of interconnect, in which the via VQ is deep into the
fatwire will make the structure mechanically stronger, and,
therefore, less prone to thermal cycle or stress migration failures
due to the expansion or contraction of metal and the interlevel low
k-dielectrics.
[0025] The circuit as described above is part of the design for an
integrated circuit chip. The chip design is created in a graphical
computer programming language, and stored in a computer storage
medium (such as a disk, tape, physical hard drive, or virtual hard
drive such as in a storage access network). If the designer does
not fabricate chips or the photolithographic masks used to
fabricate chips, the designer transmits the resulting design by
physical means (e.g., by providing a copy of the storage medium
storing the design) or electronically (e.g., through the Internet)
to such entities, directly or indirectly. The stored design is then
converted into the appropriate format (e.g., GDSII) for the
fabrication of photolithographic masks, which typically include
multiple copies of the chip design in question that are to be
formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed.
[0026] Moreover, the above-described method is used in the
fabrication of integrated circuit chips.
[0027] While the invention has been described in terms of exemplary
embodiments, those skilled in the art will recognize that the
invention can be practiced with modifications and in the spirit and
scope of the appended claims.
* * * * *