Agarwala; Birendra N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Agarwala; Birendra N..The latest application filed is for "device having a redundant structure".

Company Profile

0.14.11

Agarwala; Birendra N. - Hopewell Junction NY
Agarwala; Birendra N. - Wappingers Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dual damascene multi-level metallization Grant 7,470,613 - Agarwala , et al. December 30, 2	2008-12-30
Process for forming a redundant structure Grant 7,279,411 - Agarwala , et al. October 9, 2	2007-10-09
Device Having A Redundant Structure App 20070205515 - AGARWALA; Birendra N. ; et al.	2007-09-06
Dual-damascene metallization interconnection Grant 7,224,063 - Agarwala , et al. May 29, 2	2007-05-29
Process For Forming A Redundant Structure App 20070111497 - Agarwala; Birendra N. ; et al.	2007-05-17
Dual Damascene Multi-level Metallization App 20070111510 - Agarwala; Birendra N. ; et al.	2007-05-17
Edge seal for a semiconductor device Grant 7,163,883 - Agarwala , et al. January 16, 2	2007-01-16
Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines Grant 7,138,714 - Nguyen , et al. November 21, 2	2006-11-21
Reliability And Functionality Improvements On Copper Interconnects With Wide Metal Line Below The Via App 20060180930 - Nguyen; Du B. ; et al.	2006-08-17
Stacked via-stud with improved reliability in copper metallurgy App 20060014376 - Agarwala; Birendra N. ; et al.	2006-01-19
Stacked via-stud with improved reliability in copper metallurgy Grant 6,972,209 - Agarwala , et al. December 6, 2	2005-12-06
Structure And Method For Eliminating Time Dependent Dielectric Breakdown Failure Of Low-k Material App 20040256729 - Agarwala, Birendra N. ; et al.	2004-12-23
Structure and method for eliminating time dependent dielectric breakdown failure of low-k material Grant 6,825,561 - Agarwala , et al. November 30, 2	2004-11-30
Stacked via-stud with improved reliability in copper metallurgy App 20040101663 - Agarwala, Birendra N. ; et al.	2004-05-27
Method of making an edge seal for a semiconductor device Grant 6,734,090 - Agarwala , et al. May 11, 2	2004-05-11
Edge seal for a semiconductor device App 20040087078 - Agarwala, Birendra N. ; et al.	2004-05-06
Edge seal for a semiconductor device App 20030157794 - Agarwala, Birendra N. ; et al.	2003-08-21
Integration scheme for advanced BEOL metallization including low-k cap layer and method thereof App 20030134495 - Gates, Stephen ; et al.	2003-07-17
Dual damascene multi-level metallization App 20020182855 - Agarwala, Birendra N. ; et al.	2002-12-05
Method for providing electrically fusible links in copper interconnection Grant 6,033,939 - Agarwala , et al. March 7, 2	2000-03-07
Process of making pad structure for solder ball limiting metallurgy having reduced edge stress Grant 5,376,584 - Agarwala December 27, 1	1994-12-27
Etching processes for avoiding edge stress in semiconductor chip solder bumps Grant 5,268,072 - Agarwala , et al. December 7, 1	1993-12-07
Method of forming dual height solder interconnections Grant 5,251,806 - Agarwala , et al. October 12, 1	1993-10-12
Solder mass having conductive encapsulating arrangement Grant 5,130,779 - Agarwala , et al. July 14, 1	1992-07-14
Multilayered metallurgical structure for an electronic component Grant 4,985,310 - Agarwala , et al. January 15, 1	1991-01-15

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