U.S. patent application number 11/726161 was filed with the patent office on 2007-07-19 for mos transistor with elevated source and drain structures and method of fabrication thereof.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Young-gun Ko, Chang-bong Oh.
Application Number | 20070164354 11/726161 |
Document ID | / |
Family ID | 32866976 |
Filed Date | 2007-07-19 |
United States Patent
Application |
20070164354 |
Kind Code |
A1 |
Ko; Young-gun ; et
al. |
July 19, 2007 |
MOS transistor with elevated source and drain structures and method
of fabrication thereof
Abstract
A transistor and method of formation thereof includes source and
drain extension regions in which the diffusion of dopants into the
channel region is mitigated or eliminated. This is accomplished, in
part, by elevating the source and drain extension regions into the
epitaxial layer formed on the underlying substrate. In doing so,
the effective channel length is increased, while limiting dopant
diffusion into the channel region. In this manner, performance
characteristics of the transistor can be accurately determined by
controlling the respective geometries (i.e. depths and widths) of
the source/drain extension regions, the source/drain regions, the
channel width and an optional trench formed in the underlying
substrate. In the various embodiments, the source/drain regions and
the source/drain extension regions may extend partially, or fully,
through the epitaxial layer, or even into the underlying
semiconductor substrate.
Inventors: |
Ko; Young-gun;
(Sungnam-City, KR) ; Oh; Chang-bong;
(Sungnam-City, KR) |
Correspondence
Address: |
MILLS & ONELLO LLP
ELEVEN BEACON STREET
SUITE 605
BOSTON
MA
02108
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Suwon-si
KR
|
Family ID: |
32866976 |
Appl. No.: |
11/726161 |
Filed: |
March 21, 2007 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10697826 |
Oct 30, 2003 |
7227224 |
|
|
11726161 |
Mar 21, 2007 |
|
|
|
Current U.S.
Class: |
257/330 ;
257/E21.43; 257/E21.438; 257/E21.444; 257/E29.267 |
Current CPC
Class: |
H01L 29/66545 20130101;
H01L 29/66621 20130101; H01L 29/7834 20130101; H01L 29/665
20130101; H01L 29/66628 20130101 |
Class at
Publication: |
257/330 |
International
Class: |
H01L 29/94 20060101
H01L029/94 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 28, 2003 |
KR |
10-2003-0012793 |
Claims
1. A MOS transistor having elevated source and drain structures,
comprising: a gate dielectric layer on a substrate; a gate
electrode on the gate dielectric layer, wherein the gate dielectric
layer includes a horizontal portion that extends across a bottom
portion of the gate electrode and side portions that extend in a
vertical direction along lower side portions of the gate electrode;
an epitaxial layer contacting the side portions of the gate
dielectric layer on the substrate and extending from a point of
contact with the side portions of the gate dielectric layer
substantially parallel to the substrate in a horizontal direction;
and first source/drain regions in the epitaxial layer contacting
the side portions of the gate dielectric layer at the lower side
portions of the gate electrode.
2. The transistor of claim 1, further comprising insulating
sidewall spacers on the epitaxial layer at upper side portions of
the gate electrode.
3. The transistor of claim 2, further comprising second
source/drain regions adjacent the first source/drain regions
opposite the gate electrode.
4. The transistor of claim 3, wherein the second source/drain
regions are formed by doping exposed surfaces with impurities using
the gate electrode and the insulating sidewall spacers as
masks.
5. The transistor of claim 3, wherein the first source/drain
regions comprise source/drain extension regions and wherein the
second source/drain regions comprise deep source/drain regions.
6. The transistor of claim 3, wherein depths of the first
source/drain regions are less than depths of the second
source/drain regions.
7. The transistor of claim 3, wherein the second source/drain
regions extend into portions of the substrate.
8. The transistor of claim 3, wherein the first source/drain
regions extend into portions of the substrate.
9. The transistor of claim 2, further comprising a silicon oxide
buffer layer between the gate electrode and the insulating sidewall
spacers.
10. The transistor of claim 1, wherein the first source/drain
regions are formed by doping the epitaxial layer with
impurities.
11. The transistor of claim 1, wherein the substrate is formed
using one selected from the group consisting of: silicon,
silicon-on-insulator (SOI), SiGe, SiGe-on-insulator (SGOI),
strained silicon, strained silicon-on-insulator, and GaAs.
12. The transistor of claim 1, wherein the epitaxial layer
comprises silicon or silicon germanium.
13. The transistor of claim 1, wherein the gate dielectric layer
and the gate electrode extend into a trench formed in an upper
portion of the substrate.
14. The transistor of claim 13, wherein the trench is of a depth
that is less than about 50 nm.
15. The transistor of claim 1, further comprising a channel region
in the substrate under the gate electrode and adjacent the lower
side portions of the gate electrode.
16. The transistor of claim 1, wherein the gate dielectric layer
comprises a material selected from the group consisting of: silicon
oxide, silicon oxy-nitride (SiON), tantalum oxide, and a
high-dielectric-constant material.
17. The transistor of claim 1, wherein the gate dielectric layer is
formed using a deposition process or a thermal oxidation
process.
18. The transistor of claim 1 wherein the gate electrode comprises
a film selected from the group consisting of a polysilicon film, a
silicon geranium film, a silicide film, a metal film, and a
laminate film.
19. The transistor of claim 1, further comprising a silicide film
on the first source/drain regions and the gate electrode.
20. The transistor of claim 19, wherein the silicide film comprises
a material selected from the group consisting of Co, Ni, W, Ti and
combinations thereof.
21. The transistor of claim 1, wherein the gate dielectric layer
and the gate electrode are formed following formation of the
epitaxial layer.
22. The transistor of claim 1, wherein the gate dielectric layer
and the gate electrode are formed in an opening between neighboring
portions of the epitaxial layer, the opening exposing the
substrate.
Description
RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 10/697,826, filed on Oct. 30, 2003, which relies for priority
upon Korean Patent Application No. 03-12793, filed on Feb. 28,
2003, the contents of which are herein incorporated by reference in
their entirety.
BACKGROUND OF INVENTION
[0002] the semiconductor industry, minimization of the feature size
of MOS transistors in integrated circuits is a common goal. This
goal is essentially driven by the need to produce integrated
circuits at ever-lower costs, while improving circuit functionality
and speed. Such downscaling can be achieved by reducing the
characteristic dimensions of the transistors, i.e. reducing the
gate lengths, the gate oxide thickness, and the junction depths,
and by increasing the channel doping levels. However, scaled-down
MOS transistors generally suffer from a phenomenon referred to as
the "short-channel effect". The short-channel effect has an adverse
impact on the switching performance of the transistors, because
such switching is inefficiently controlled by the gate electrode,
which leads to an undesired decrease in the threshold voltage.
Mechanically, the depletion regions around the source and the drain
occupy an increasingly large fraction of the channel region, so
that a lower potential on the gate is needed to achieve inversion
in the channel.
[0003] Referring to the FIG. 1, a conventional scaled-down MOS
transistor 100, which is fabricated within a semiconductor
substrate 102, includes a source extension region 106a and a drain
extension region 106b. The source extension region 106a and the
drain extension region 106b have shallow junctions in order to
minimize the short-channel effect that occurs in MOS transistors
having sub-micron or nanometer dimensions. The MOS transistor 100
further includes a source region 108a and a drain region 108b that
have deeper junctions, relative to the source extension region 106a
and the drain extension region 106b, to provide lower resistance.
The MOS transistor 100 also includes a gate structure 110, which is
comprised of a gate dielectric 112 and a gate electrode 114. An
insulative spacer 118, which is typically comprised of silicon
nitride (SiN), is disposed on the sidewalls of the gate structure
110. The MOS transistor 100 further includes silicide regions 120a,
120b, and 120c to provide low-resistance electrical contact with
the source/drain 106a/106b and the gate electrode 114. The MOS
transistor is electrically isolated from other devices by shallow
trench isolation structures 104.
[0004] A problem lies in that impurities in the source/drain
extension regions 106a/106b tend to diffuse to the region
immediately under the gate 110. The portions of the source/drain
extension regions 106a/106b formed immediately under the gate 110
have a higher electric resistance relative to the portions of the
extension regions 106a/106b located immediately under the sidewall
spacers 118. For this reason, the transistor 100 has effective
resistances R that are connected in series to the source and the
drain. This inhibits the flow of electric current, thus decreasing
operation speed.
[0005] A second problem concerns the rise of channel dopant
concentration, which in turn causes a rise in threshold voltage in
the field effect transistor. In order to meet miniaturization
requirements in MOS transistors, the impurity concentration of the
channel impurity region is necessarily raised. At the same time,
contemporary semiconductor devices are designed to operate with a
lower power supply voltage, such as ranging from 5V to 3.3V. For
operation with such a low power supply voltage, the threshold
voltage of the field effect transistor needs to be lower. For this
reason, any rise in the threshold voltage of MOS transistor due to
the rise in channel dopant concentration is undesirable. On the
other hand, a channel doping level that is too high in scaled-down
devices gives rise to superfluous leakage current and junction
breakdown.
[0006] In an attempt to overcome the stated disadvantages, elevated
source and drain structures have been suggested. Referring to FIG.
2, a gate structure 210 comprised of a gate dielectric 212 and a
gate electrode 214 is formed on the surface of the semiconductor
substrate 202. A source extension region 206a and a drain extension
region 206b are then formed in the semiconductor substrate. A
spacer 218, typically comprised of silicon nitride (SiN), is formed
on the sidewalls of the gate structure 210. An epitaxial layer 205,
typically comprised of silicon, is grown on the exposed portions of
the source/drain extension regions 206a/206b, typically using
selective epitaxial growth. Following the growth of the epitaxial
layer 205, dopants are implanted and activated to form an elevated
source 208a and an elevated drain 208b. The MOS transistor 200
further includes silicide regions 220a, 220b, and 220c to provide
electrical contacts to the elevated source/drain regions 208a/208b
and the gate electrode 214.
[0007] A MOS transistor having an elevated source/drain produced
according to the structure of FIG. 2 is effective for reducing the
resistance of the source and drain regions by increasing the
thickness and the doping level by elevating the source/drain
regions 208a/208b. However, it is inevitable that the dopants of
the source/drain extension regions 206a/206b diffuse into the
region immediately under the gate 210, which result in junction
leakage current through the source/drain extension regions
206a/206b.
SUMMARY OF THE INVENTION
[0008] The present invention is directed to a MOS transistor having
elevated source and drain structures, and a method of formation
thereof, that overcomes the limitations of the conventional
embodiments. In particular, the present invention provides for a
transistor that includes source and drain extension regions in
which the diffusion of dopants into the channel region is mitigated
or eliminated. This is accomplished, in part, by elevating the
source and drain extension regions into the epitaxial layer formed
on the underlying substrate. In doing so, the effective channel
length is increased, while limiting dopant diffusion into the
channel region.
[0009] The performance characteristics of the transistor of the
present invention can be accurately determined by controlling the
respective geometries (i.e. depths and widths) of the source/drain
extension regions, the source/drain regions, the channel width and
an optional trench formed in the underlying substrate. In the
various embodiments, the source/drain regions and the source/drain
extension regions may extend partially, or fully, through the
epitaxial layer, or even into the underlying semiconductor
substrate.
[0010] In one aspect, the present invention is directed to a method
for forming a MOS transistor having elevated source and drain
structures. A sacrificial gate pattern is provided on a substrate.
An epitaxial layer is provided on the substrate adjacent the
sacrificial gate pattern. A silicon nitride film and a silicon
oxide film are provided on the epitaxial layer adjacent the
sacrificial gate pattern. The sacrificial gate pattern is removed
to expose a portion of the substrate and wall portions of the
epitaxial layer. A gate dielectric layer is provided on the exposed
portion of the substrate and along the wall portions of the
epitaxial layer. A gate electrode is provided on the gate
dielectric layer. The silicon oxide film and silicon nitride film
are removed. The epitaxial layer is doped with impurities using the
gate electrode as a mask to form source/drain extension regions in
the epitaxial layer proximal to the gate dielectric layer.
Insulating spacers are provided on sidewalls of an upper portion of
the gate electrode. The epitaxial layer is doped with impurities
using the gate electrode and insulating spacers as a mask to form
deep source/drain regions adjacent the source/drain extension
regions.
[0011] In one embodiment, the source/drain extension regions are
formed by doping the epitaxial layer with impurities prior to
providing the silicon nitride film and silicon oxide film on the
epitaxial layer. Providing the sacrificial gate pattern may
comprise sequentially forming a silicon oxide film and a silicon
nitride film and patterning the sequentially formed films to form
the sacrificial gate pattern.
[0012] The substrate is, for example, of a type selected from the
group consisting of: silicon; silicon-on-insulator (SOI); SiGe;
SiGe-on-insulator(SGOI); strained silicon; strained
silicon-on-insulator; and GaAs. The substrate is optionally formed
of a material of a first conductivity type and the impurities used
for doping the epitaxial layer are of a second conductivity type
opposite that of the first conductivity type. A pad oxide layer may
be formed on the epitaxial layer.
[0013] The step of providing a silicon nitride film and a silicon
oxide film on the epitaxial layer adjacent the sacrificial gate
pattern may comprise: sequentially providing a silicon nitride film
and a silicon oxide film on the epitaxial layer and the sacrificial
gate pattern; and planarizing the silicon nitride film, silicon
oxide film and sacrificial gate pattern to expose an upper surface
of the sacrificial gate pattern. The silicon oxide film is
provided, for example, by a chemical vapor deposition (CVD)
process. The step of planarizing comprises, for example,
planarizing by a chemical-mechanical polishing process (CMP) or an
etch-back treatment.
[0014] Removal of the sacrificial gate pattern comprises etching
the sacrificial gate pattern to expose an upper surface of the
substrate, or, optionally, forming a recess in the substrate, in
which case the gate dielectric layer is formed on bottom and side
walls of the recess of the substrate. The recess is preferably of a
depth that is less than 50 nm.
[0015] The exposed portion of the substrate may be doped with
impurities to form a channel region following removal of the
sacrificial gate pattern, or, optionally, prior to providing the
sacrificial gate pattern on the substrate, the channel region
corresponding to an area of the substrate covered by the
sacrificial gate pattern.
[0016] The gate dielectric layer preferably comprises a material
selected from the group of materials consisting of: silicon oxide
film; silicon oxy-nitride (SiON); tantalum oxide; and a
high-dielectric-constant material.
[0017] The step of providing the gate electrode comprises, for
example, forming a gate electrode material film on the gate
dielectric layer and the silicon oxide film; and planarizing the
gate electrode material film and silicon oxide film. Planarizing
comprises, for example, planarizing by a chemical-mechanical
polishing process (CMP) or an etch-back treatment.
[0018] The gate electrode comprises a material selected from the
group of materials consisting of polysilicon film; silicon geranium
film; silicide film; metal film; and a laminate film. The step of
removing the silicon oxide film and silicon nitride film comprises
removing using a wet etching process.
[0019] The step of providing insulating spacers on sidewalls of an
upper portion of the gate electrode comprises, for example,
providing a silicon nitride film on the resultant structure; and
anisotropically etching the silicon nitride film. Prior to
providing the silicon nitride film, a silicon oxide buffer layer
may be provided on the resultant structure.
[0020] Doping the epitaxial layer with impurities using the gate
electrode and insulating spacers as a mask to form source/drain
regions adjacent the source/drain extension regions comprises, for
example, doping with impurities of a same conductivity type as that
of the source/drain extension regions.
[0021] A silicide film may optionally be formed on the source/drain
regions and the gate electrode. The silicide film comprises, for
example, a cobalt silicide film.
[0022] The source/drain extension regions are formed, for example,
to a first depth and the deep source/drain regions are formed to a
second depth. In one example, the first depth is less than the
second depth. The deep source/drain regions and/or the source/drain
extension regions may optionally extend into the substrate.
[0023] Trench isolation structures in the substrate may be formed
on opposite sides of the deep source/drain regions, for example,
according to a shallow trench isolation process.
[0024] In another aspect, the present invention is directed to a
MOS transistor having elevated source and drain structures. A gate
dielectric layer is provided on a substrate. A gate electrode is
provided on the gate dielectric layer. An epitaxial layer is
provided adjacent the gate dielectric layer on the substrate. First
source/drain regions are provided in the epitaxial layer adjacent
the gate dielectric layer at lower side portions of the gate
electrode.
[0025] In one example, the gate dielectric layer extends across a
bottom portion and the lower side portions of the gate electrode;
The first source/drain regions are formed by doping the epitaxial
layer with impurities. The substrate is formed of a material of a
first conductivity type and. wherein the impurities used for doping
the epitaxial layer are of a second conductivity type opposite that
of the first conductivity type.
[0026] Insulating spacers may be provided on the epitaxial layer at
an upper side portion of the gate electrode; and second
source/drain regions may be provided adjacent the first
source/drain regions opposite the gate electrode . In this case,
the second source/drain regions are formed, for example, by doping
exposed surfaces with impurities using the gate electrode and
insulating spacers as a mask. The first source/drain regions
comprise source/drain extension regions and the second source/drain
regions comprise deep source/drain regions. The first source/drain
regions are formed to a first depth in the epitaxial layer and the
second source/drain regions are formed to a second depth. The first
depth is, in one example, less than the second depth. The first
source/drain regions and/or the second source/drain regions may
optionally extend into a portion of the substrate.
[0027] The substrate may be formed of a type selected from the
group consisting of: silicon; silicon-on-insulator (SOI); SiGe;
SiGe-on-insulator(SGOI); strained silicon; strained
silicon-on-insulator; and GaAs. The epitaxial layer may comprise
silicon.
[0028] The gate dielectric layer and gate electrode extend into a
trench formed in an upper portion of the substrate. In one example,
the trench is of a depth that is less than 50 nm.
[0029] A channel region is formed in the substrate under the gate
electrode and adjacent the lower side portions of the gate
electrode.
[0030] The gate dielectric layer comprises a material selected from
the group of materials consisting of: silicon oxide film; silicon
oxy-nitride (SiON); tantalum oxide; and a high-dielectric-constant
material. The gate electrode comprises a material selected from the
group of materials consisting of polysilicon film; silicon geranium
film; silicide film; metal film; and a laminate film. A silicon
oxide buffer layer may be provided between the gate electrode and
the insulating spacers. A silicide film, for example comprising a
cobalt silicide film, may be formed on the source/drain regions and
the gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The foregoing and other objects, features and advantages of
the invention will be apparent from the more particular description
of preferred embodiments of the invention, as illustrated in the
accompanying drawings in which like reference characters refer to
the same parts throughout the different views. The drawings are not
necessarily to scale, emphasis instead being placed upon
illustrating the principles of the invention.
[0032] FIG. 1 is a cross-sectional schematic view of a conventional
MOS transistor.
[0033] FIG. 2 is a cross-sectional schematic view of a conventional
MOS transistor having elevated source and drain regions.
[0034] FIG. 3 is a cross-sectional schematic view of a MOS
transistor having elevated source and drain regions, in accordance
with a first embodiment of the present invention.
[0035] FIG. 4 is a cross-sectional schematic view of a MOS
transistor having elevated source and drain regions, in accordance
with a second embodiment of the present invention.
[0036] FIGS. 5, 6 and 7 are cross-sectional schematic views of MOS
transistors having elevated source and drain regions, wherein the
source and drain regions and the source and drain extension regions
are of various depths, in accordance with the present
invention.
[0037] FIGS. 8A and 8B are cross-sectional schematic views of MOS
transistor having elevated source and drain regions, in accordance
with the first and second embodiments of the present invention
formed on an silicon-on-insulator (SOI) substrate.
[0038] FIGS. 9A-9L are cross-sectional schematic views of a method
for fabricating the MOS transistor of the first embodiment of the
present invention.
[0039] FIGS. 10A-10C are cross-sectional schematic views of a
method for fabricating the MOS transistor of the second embodiment
of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0040] A MOS transistor structure 300 according to the present
invention is illustrated in FIG. 3. A gate electrode 314 is formed
over a semiconductor substrate 302 to form a gate 310. A gate
dielectric 312, for example formed of silicon oxide (SiO.sub.2), is
formed under the gate electrode 314 and at the lower portions of
the sidewalls of the gate electrode 314. An epitaxial layer 305,
for example comprising silicon or silicon germanium, is formed on
the substrate 302 adjacent opposite sides of the gate 310. An
insulative spacer 318, is formed at the upper portions of the
sidewalls of the gate 310. In the epitaxial layer 305, a source
extension region 306a and a drain extension region 306b are formed
under the spacers 318. A source 308a and a drain 308b are formed on
the exposed portions of the source/drain extension regions
306a/306b, i.e. portions of the epitaxial regions that do not lie
under the spacers 318. The MOS transistor 300 may further
optionally include silicide regions 320a, 320b, and 320c to provide
low-resistance electrical contacts for the elevated source/drain
306a/306b and the gate electrode 314.
[0041] The insulative spacer 318 is comprised, for example, of
silicon nitride (SiN). In addition, an optional silicon oxide layer
316 may be formed as a buffer layer between the SiN spacer 318 and
other silicon layers such as the gate electrode 314 and epitaxial
layer 305.
[0042] With reference to FIG. 4, the gate electrode 414 may
optionally be formed in a trench 417 or a recessed portion, of the
semiconductor substrate 402, as shown. In this case, the gate
dielectric 412 is partially formed under, and at the lower portions
of, the sidewalls of the gate electrode, for example, on the bottom
and side surfaces of the gate trench 417 of the semiconductor
substrate 402 and at the sidewalls of the epitaxial layer 405 as
shown. The trench embodiment of FIG. 4 provides for an effective
lengthening of the channel region between the source and drain
extension regions 406a, 406b.
[0043] The effective channel length of the transistor structure of
the present invention can be varied by controlling several factors,
including the thickness of the epitaxial layer 305 (405), the depth
of the source/drain extension regions 306a/306b (406a/406b), the
depth of the source/drain regions 308a/308b (408a/408b), and the
depth of the gate trench 417.
[0044] In the exemplary embodiments of FIGS. 3 and 4, the depths of
the source/drain regions 308a/308b (408a/408b) extend into the
semiconductor substrate 302 (402) as shown. Optionally, the depths
of the source/drain extension regions 306a/306b (406a/406b) may
also extend into the semiconductor substrate 302 (402) (not shown).
In the example of FIG. 5, the source/drain regions 508a/508b extend
to the boundary between the epitaxial layer 505 and the
semiconductor substrate 502, while the source/drain extension
regions 506a/506b extend partially through the epitaxial layer 505.
In the example of FIG. 6, the source/drain regions 608a/608b extend
to the boundary between the epitaxial layer 605 and the
semiconductor substrate 602, and the source/drain extension regions
606a/606b also extend to the boundary between the epitaxial layer
605 and the semiconductor substrate 602. In the example of FIG. 7,
the source/drain regions 708a/708b partially extend through the
epitaxial layer 705, and the source/drain extension regions
706a/706b also partially extend through the epitaxial layer 705 to
a depth that is different than that of the source/drain regions
708a/708b.
[0045] By controlling the channel length, various device
characteristics can be achieved , and the short-channel effect can
be prevented, despite the need for down-scaling of device size. In
a conventional transistor, the channel length is controlled
primarily by the gate length; however, in the transistor of the
present invention, the channel length is not only controlled by the
gate length but also controlled according to the thickness of the
epitaxial layer, the depth of the source/drain regions, and the
depth of the gate trench.
[0046] According to the present invention, with reference to FIG.
3, since the impurities in the source/drain extension regions
306a/306b are located in the epitaxial layer 305, the impurities
will not diffuse into the region under the gate 310, as in the
conventional embodiments, even following a heat treatment of the
silicon substrate 302. In this manner, shortening of the channel
length relative to the gate length, is prevented. Furthermore, the
channel length can be variably lengthened to include the lower
sidewall of the gate as well as the region located immediately
under the gate electrode by controlling the thickness of epitaxial
layer 305, the depth of the source/drain extension regions
306a/306b in the epitaxial layer, or the depth of the gate trench
417 in the semiconductor substrate. In this manner, a channel of
sufficient length can be achieved in a transistor structure that
includes a minimized gate length.
[0047] According to the present invention, the concentration
distribution of impurities in the channel region between the source
extension region and the drain extension region can be precisely
controlled. As a result, the resulting threshold voltage of a MOS
transistor can be accurately predicted, and, accordingly, a
semiconductor device having optimal electrical characteristics can
be obtained.
[0048] Rise in the threshold voltage of the MOS transistor can be
restrained, for example, by forming source/drain regions 308a/308d
in the epitaxial layer 305 to have lower impurity concentrations,
thereby affording compatibility with a decrease in the power supply
voltage of the semiconductor device.
[0049] The material of the semiconductor substrate is not limited
to silicon, but may comprise any of a number of other semiconductor
materials or configurations including silicon-on-insulator (SOI),
SiGe, SiGe-on-insulator (SGOI), strained silicon (silicon-on-SiGe),
strained silicon-on-insulator, and GaAs. A cross-sectional
schematic view of an embodiment of the present invention, where a
MOS transistor is formed on an SOI substrate 702, is shown in FIGS.
8A and 8B. In the FIG. 8A embodiment, the MOS transistor 700 formed
on an SOI substrate 702 includes a gate 710 that is formed on the
SOI substrate 702, as in the embodiment of FIG. 3. In the FIG. 8B
embodiment, the MOS transistor 800 formed on an SOI substrate 802
includes a gate 810 that is formed in a trench 817 formed in the
SOI substrate 802, as in the embodiment of FIG. 4. In this manner,
the transistor 700, 800 in accordance with the present invention is
fully compatible with SOI fabrication processes. As such, the
thickness of the channel impurity region in the transistor can be
maintained or decreased dramatically, while increasing the junction
depths of the resultant elevated source/drain regions.
[0050] In an SOI device, the depth of the source/drain regions
becomes shallow, since the thickness of the surface silicon is
relatively shallow. As a result, the resulting resistance of the
source/drain region increases. The present invention alleviates
this problem, since the source/drain regions have adequate depth by
virtue of the epitaxial layer.
[0051] The gate dielectric 312, 412, may be formed of silicon oxide
film, as stated above, or alternatively, silicon-oxy-nitride
(SiON). Alternatively, a film comprising a high-dielectric-constant
material such as tantalum oxide may be used. The gate dielectric
layer may be formed, for example, in a deposition process, or,
alternatively, in a thermal oxidation process. For the gate
electrode, a silicon germanium film, a silicide film, or a metal
film, for example, may be used instead of the polysilicon film.
Optionally, a laminate film of the above materials may be used.
[0052] A first embodiment of the present invention is shown and
described above with reference to FIG. 3. A method of fabricating a
semiconductor device according to the first embodiment of the
present invention will now be described with reference to FIGS.
9A-9L.
[0053] Initially, referring to FIG. 9A, an element isolation film
304 is formed in a silicon substrate 302, for example, by a shallow
trench isolation method. Next, impurities are doped into the
silicon substrate 302, so as to form a well region and a channel
impurity region (not shown). Next, a silicon oxide film 332 and a
silicon nitride film 334 are sequentially formed on the silicon
substrate 302 and are subjected to anisotropic etching in order to
form a dummy gate electrode 330.
[0054] Next, referring to FIG. 9B, an epitaxial layer 305 is
selectively grown on the substrate 302 on sides of the dummy gate
330. For example selective epitaxial growth (SEG) may be used to
form the epitaxial layer 305 such that it is formed on the surface
of the silicon substrate and not on the silicon nitride 334 layer
or oxide trench isolation elements 304. The epitaxial layer 305 may
optionally be doped at this stage to form the source/drain
extension regions, or alternatively, may remain un-doped at this
stage. In a preferred embodiment, doping of the source/drain
extension regions follows formation of the gate electrode, as
described below with reference to FIG. 9I. If the epitaxial layer
is doped at this stage, an optional pad oxide layer (not shown) is
provided on the epitaxial layer 305 as a buffer layer, in order to
protect the epitaxial layer during implantation of dopants. The
optional pad oxide layer may be grown by thermal oxidation.
[0055] As shown in FIG. 9C, a silicon nitride film 337 is formed on
the entire surface of the resulting structure of FIG. 9B. Next, a
silicon oxide film 338 is formed, for example, by a CVD method.
Next, the silicon oxide film 338 is subjected, for example, to a
chemical mechanical polishing treatment, or an entire surface
etching-back treatment, so as to planarize the surface of the
silicon oxide film 338 and to expose the surface of the silicon
nitride 334 as shown in FIG. 9D.
[0056] Referring to FIG. 9E, the dummy gate 330, including the
silicon nitride film 334 and the silicon oxide film 332, is
removed, exposing a portion of surface of the semiconductor
substrate 302. Since the surface of the semiconductor substrate
above the channel region is exposed, the channel impurity region
may be optionally formed at this time, rather than forming the
channel impurity region during formation of the well region as
described above with respect to FIG. 9A. In this manner, the
channel impurity region can be formed in the semiconductor
substrate in a region that is localized to the area under the
region of the now removed dummy gate pattern. This is especially
beneficial for the FIG. 4 embodiment, which includes a trench
formed in the semiconductor substrate, and a channel region formed
under the trench.
[0057] Referring to FIG. 9F, a gate dielectric 312 layer, for
example of silicon oxide film, is formed on the exposed channel
impurity region and the side walls of the epitaxial layer 305. The
gate dielectric 312 layer may be formed of silicon oxide using a
thermal oxidation process, or, alternatively, a deposition of
high-dielectric-constant material such as silicon oxy-nitride
(SiON), aluminum oxide, HfO.sub.2, or tantalum oxide may be used.
Next, a gate electrode 314, for example of polysilicon film, is
deposited on the gate dielectric 312. The gate electrode 314
material may alternatively comprise, for example, a silicon
germanium film, a silicide film, a tungsten film, a TiN film, or a
metal film, or laminates thereof. With reference to FIG. 9G, the
polysilicon film is next planarized, for example, by a chemical
mechanical polishing treatment or a entire surface etch-back
treatment to remove the upper portion of the gate dielectric layer
312 and to expose the silicon oxide film 338. Next, with reference
to FIG. 9H, the silicon oxide 338 and silicon nitride 337 layers
are removed, for example by a wet etching process, to form a gate
structure 310.
[0058] Next, as shown in FIG. 9I, impurities having an opposite
conductivity type to that of the silicon substrate are implanted
into the epitaxial layer 305 so as to form respective source
extension and drain extension regions 306a, 306b. A pad oxide film
316, for example of silicon oxide material, formed by thermal
oxidation or deposition, may optionally be formed on the epitaxial
layer 305 as a buffer layer, in order to protect the surface of the
epitaxial layer 305 from damage during the implanting process.
[0059] Referring to FIG. 9J, a silicon nitride (SiN) film is
provided to cover the substrate, which is then subjected to
anisotropic etching, or alternatively a dry etch process, so as to
form spacers 318 on the upper sidewalls of the gate 310. The
silicon oxide buffer layer 316 between the SiN spacer 318 and the
other silicon layers, such as the gate electrode 314 and the
epitaxial layer 305, remains following the anisotropic etch.
[0060] Referring to FIG. 9K, using the gate 310 and the spacers 318
as a mask, impurities having the same conductivity type as the
source/drain extension regions 306a/306b are implanted into the
epitaxial layer 305, so as to form a source region 308a and a drain
region 308b. At this time, the source/drain extension regions
308a/308b remain under the spacers 318 and the source/drain regions
308a/308b are formed beside the spacers 318 in the epitaxial layer.
The depth of the source and drain regions 308a, 308b is controlled
according to the doping process for example, according to the
concentration of impurities and the length of time of exposure.
[0061] Referring to FIG. 9L, a cobalt film is formed, for example,
by a sputtering method, and then subjected to a heat treatment at a
temperature ranging between 500.degree. C. and 1000.degree. C. in a
nitrogen atmosphere or an argon atmosphere, so as to allow the
cobalt film to react with the silicon in the epitaxial layer 305
and the gate 310, thereby to form cobalt silicide films 320a, 320b,
and 320c in a self-aligned manner on exposed surfaces of the
source/drain regions 308a/308b and the gate electrode 314,
respectively. Unreacted cobalt film is then removed using
conventional means. Alternatively, the silicide films may comprise
other suitable materials, including Co, Ni, W, Ti, and combinations
thereof.
[0062] In this manner, by deferring formation of the source/drain
extension regions 306a/306b until after the gate electrode 314 is
formed, fewer steps are required for fabrication of the transistor
structure of the present invention. Alternatively, as stated above,
the source/drain extension regions 306a/306b may be formed at the
step shown in FIG. 9B, using the dummy gate pattern 330 as a mask.
However, this approach requires additional steps.
Second Embodiment
[0063] A second embodiment of the invention is shown and described
above with reference to FIG. 4. In the second embodiment, the gate
electrode 414 is formed in a trench or a recessed portion 417 of
the semiconductor substrate 402. Other components of the transistor
configuration of the second embodiment are similar to those of the
first configuration above, and therefore their description will be
omitted here. Components of FIG. 4 having a reference numeral
beginning with the prefix "4" and a unique suffix "4xx" share the
same purpose as those components of FIG. 3, described above, having
the same suffix "3xx".
[0064] A method of fabricating a semiconductor device according to
the second embodiment of the present invention will now be
described with reference to FIGS. 10A-10C.
[0065] The processes preceding the step shown at FIG. 10A are
identical to those shown in FIGS. 9A-9D above with reference to the
first embodiment.
[0066] Referring to FIG. 10A, the dummy gate, including the silicon
nitride film and the silicon oxide film, is removed, exposing a
portion of surface of the semiconductor substrate 302. The exposed
surface of the semiconductor substrate is further subjected to
etching in order to form a trench 417 or recessed region. The depth
of the trench 417 is determined according to the desired channel
length of the resulting device; the deeper the trench 417, the
longer the effective channel length. In general, the depth of the
trench 417 is less than 50 nm.
[0067] As explained above, since the surface of the semiconductor
substrate above the channel region is exposed, the channel impurity
region may be optionally formed at this time, rather than forming
the channel impurity region during formation of the well region as
described above with respect to FIG. 9A. In this manner, the
channel impurity region can be formed in the semiconductor
substrate in a region that is localized to the area under the
region of the now removed dummy gate pattern. This is especially
beneficial for the present embodiment, which includes a trench
formed in the semiconductor substrate, and a channel region formed
under the trench, since the channel region is not fully defined
until the trench is formed.
[0068] Referring to FIG. 10B, a gate dielectric 412 layer, for
example of silicon oxide film, is formed on the exposed channel
impurity region, the side walls of the trench 417, and the side
walls of the epitaxial layer 405. As described above, the gate
dielectric 412 layer may be formed of silicon oxide using a thermal
oxidation process, or, alternatively, a deposition of
high-dielectric-constant material such as silicon oxy-nitride
(SiON), aluminum oxide, HfO.sub.2, or tantalum oxide may be used.
Next, a gate electrode 414, for example of polysilicon film, is
deposited on the gate dielectric layer 412. The gate electrode 414
material may alternatively comprise, for example, a silicon
germanium film, a silicide film, a tungsten film, a TiN film, or a
metal film, or laminates thereof. With reference to FIG. 10C, the
polysilicon film is next planarized, for example, by a chemical
mechanical polishing treatment or a entire surface etch-back
treatment to remove the upper portion of the gate dielectric layer
412 and to expose the silicon oxide film 438.
[0069] Thereafter, the processes are identical to those shown in
reference to FIG. 9H to FIG. 9L explained in the first
embodiment.
[0070] The performance characteristics of the resulting transistor
can be accurately determined by controlling the respective
geometries (i.e. depths and widths) of the source/drain extension
regions, the source/drain regions, the channel width and the
optional trench. In the various embodiments, the source/drain
regions and the source/drain extension regions may extend
partially, or fully, through the epitaxial layer, or even into the
underlying semiconductor substrate.
[0071] While this invention has been particularly shown and
described with references to preferred embodiments thereof, it will
be understood by those skilled in the art that various changes in
form and details may be made herein without departing from the
spirit and scope of the invention as defined by the appended
claims.
* * * * *