U.S. patent application number 11/469011 was filed with the patent office on 2007-06-21 for field plate trench transistor and method for producing it.
This patent application is currently assigned to INFINEON TECHNOLOGIES AUSTRIA AG. Invention is credited to Franz Hirler, Wolfgang Klein, Thorsten Meyer, Frank Pfirsch, Walter Rieger.
Application Number | 20070138544 11/469011 |
Document ID | / |
Family ID | 37762870 |
Filed Date | 2007-06-21 |
United States Patent
Application |
20070138544 |
Kind Code |
A1 |
Hirler; Franz ; et
al. |
June 21, 2007 |
FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT
Abstract
A field plate trench transistor having a semiconductor body is
disclosed. In one embodiment, the semiconductor has a trench
structure and an electrode structure embedded in the trench
structure. The electrode structure being electrically insulated
from the semiconductor body by an insulation structure and having a
gate electrode structure and a field electrode structure. The field
plate trench transistor has a voltage divider configured such that
the field electrode structure is set to a potential lying between
source and drain potentials.
Inventors: |
Hirler; Franz; (Isen,
DE) ; Rieger; Walter; (Arnoldstein, AT) ;
Meyer; Thorsten; (Munich, DE) ; Klein; Wolfgang;
(Zorneding, DE) ; Pfirsch; Frank; (Munich,
DE) |
Correspondence
Address: |
DICKE, BILLIG & CZAJA, P.L.L.C.
FIFTH STREET TOWERS
100 SOUTH FIFTH STREET, SUITE 2250
MINNEAPOLIS
MN
55402
US
|
Assignee: |
INFINEON TECHNOLOGIES AUSTRIA
AG
Siemensstr. 2
Villach
AT
9500
|
Family ID: |
37762870 |
Appl. No.: |
11/469011 |
Filed: |
August 31, 2006 |
Current U.S.
Class: |
257/330 ;
257/E29.027; 257/E29.133; 257/E29.183; 257/E29.187;
257/E29.327 |
Current CPC
Class: |
H01L 27/04 20130101;
H01L 29/0696 20130101; H01L 29/0878 20130101; H01L 29/732 20130101;
H01L 29/407 20130101; H01L 29/735 20130101; H01L 27/0727 20130101;
H01L 29/7803 20130101; H01L 29/404 20130101; H01L 29/42368
20130101; H01L 29/66734 20130101; H01L 29/7808 20130101; H01L
29/861 20130101; H01L 29/7813 20130101 |
Class at
Publication: |
257/330 |
International
Class: |
H01L 29/94 20060101
H01L029/94 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 31, 2005 |
DE |
10 2005 041 358.7 |
Claims
1. A field plate trench transistor having a semiconductor body
comprising: a trench structure; and an electrode structure embedded
in the trench structure, the electrode structure being electrically
insulated from the semiconductor body by an insulation structure
and having a gate electrode structure and a field electrode
structure arranged below and/or alongside the gate electrode
structure and electrically insulated from the latter; and a voltage
divider provided in and/or on the semiconductor body, the voltage
divider being electrically connected to the field electrode
structure or integrated into the latter, the voltage divider being
configured such that the field electrode structure is set to a
potential lying between source and drain potentials and/or gate and
drain potentials.
2. The field plate trench transistor as claimed in claim 1, wherein
the field electrode structure is divided into a plurality of field
electrode regions arranged vertically one above another and the
voltage divider is divided into a plurality of voltage divider
regions, each voltage divider region being electrically connected
to a field electrode region or integrated into the latter, so that
at least two different field electrode regions are at different
potentials.
3. The field plate trench transistor as claimed in claim 1, wherein
the voltage divider is realized as a series circuit comprising at
least one resistor and at least one diode which is forward-biased
with respect to the drain potential or as a series circuit
comprising a plurality of diodes which are forward-biased with
respect to the source potential, which are connected between source
and drain potentials.
4. The field plate trench transistor as claimed in claim 3, wherein
the at least one diode is a zener diode.
5. The field plate trench transistor as claimed in claim 2, wherein
the different field electrode regions within the trench structure
are electrically insulated from one another, and the voltage
divider is provided outside the field electrode structure.
6. The field plate trench transistor as claimed in claim 2, wherein
the different field electrode regions within the trench structure
are electrically connected to one another, and the voltage divider
is provided within the field electrode structure.
7. The field plate trench transistor as claimed in claim 6, wherein
pn diodes are provided between the field electrode regions, in such
a way that the pn diodes are interlinked with one another via the
field electrode regions to form a vertically running diode series
circuit.
8. The field plate trench transistor as claimed in claim 7, wherein
the upper end of the diode series circuit directly adjoins a source
metallization layer of the transistor, and the lower end of the
diode series circuit directly adjoins a drift zone provided within
the semiconductor body.
9. The field plate trench transistor as claimed in claim 1, wherein
the voltage divider has at least one substrate diode which is
connected between source and drain potentials and is forward-biased
with respect to the drain potential, the substrate diode being
formed by the pn junction between a semiconductor zone of a first
conduction type provided in the semiconductor body, in particular
within the mesa structure, and the part of the semiconductor body
of a second conduction type lying below the semiconductor zone, the
semiconductor zone of the first conduction type being produced
together with the body zones of the trench transistor in one
process.
10. The field plate trench transistor as claimed in claim 9,
wherein that end of the substrate diode which faces the source
potential is connected to a voltage limiting element connected
between substrate diode and source potential, which voltage
limiting element prevents the potential of the field electrode
structure from exceeding a potential maximum value and/or falling
below a potential minimum value in the operating state.
11. The field plate trench transistor as claimed in claim 10,
wherein the voltage limiting element is at least partly realized in
the form of one or a plurality of series-connected diodes which are
forward-biased with respect to the drain potential and are formed
within the cell array region or the edge region of the
semiconductor body or within the trench structure.
12. The field plate trench transistor as claimed in claim 10,
wherein the voltage limiting element is at least partly formed in
the form of a MOS transistor, the body zone of which is the
semiconductor zone of the first conduction type of the substrate
diode.
13. The field plate trench transistor as claimed in claim 9,
wherein the voltage limiting element is at least partly formed in
the form of one or a plurality of capacitive elements formed within
the semiconductor body.
14. The field plate trench transistor as claimed in claim 9,
wherein that end of the substrate diode which faces the source
potential is connected to a pull-down element connected between
substrate diode and source potential or gate potential, which
pull-down element prevents the potential of the field electrode
structure from drifting, in the off state of the transistor, to
drain potential as a result of leakage currents occurring within
the substrate diode.
15. The field plate trench transistor as claimed in claim 14,
wherein the pull-down element is at least partly realized in the
form of a resistance element provided within the mesa structure,
the gate electrode structure, the field electrode structure or
within a conductive element provided above the semiconductor body
and electrically insulated from the latter.
16. The field plate trench transistor as claimed in claim 14,
wherein the pull-down element is at least partly realized in the
form of a transistor formed within the semiconductor body, in
particular within the mesa structure.
17. The field plate trench transistor as claimed in claim 9,
wherein the substrate diode has a reduced breakdown voltage
compared with the transistor elements provided within the cell
array of the transistor.
18. A method for producing a field plate trench transistor,
comprising: forming a trench structure; and providing an insulation
structure lining the trench structure, the remaining free space
within the trench structure extending downward toward the
semiconductor body; filling the free space by alternately
depositing n- and p-doped semiconducting material and
metal-containing material; or filling the free space by repeatedly
depositing a layer made of semiconducting material of the first
conduction type, carrying out a coating process in order to form a
zone of the second conduction type in the previously deposited
layer, and producing a silicide layer on the previously-formed zone
of the second conduction type.
19. The method as claimed in claim 18, wherein that part of the
insulation structure which is formed in the upper region of the
trench structure is partly etched back into the trench structure,
and the gate electrode structure is introduced into the resulting
cutout.
20. A field plate trench transistor having a semiconductor body
comprising: a trench structure; and means for providing an
electrode structure embedded in the trench structure, the electrode
structure being electrically insulated from the semiconductor body
by an insulation structure means and having a gate electrode
structure and a field electrode structure arranged below and/or
alongside the gate electrode structure and electrically insulated
from the latter; and means for providing a voltage divider in
and/or on the semiconductor body, the voltage divider means being
electrically connected to the field electrode structure or
integrated into the latter, the voltage divider means being
configured such that the field electrode structure is set to a
potential lying between source and drain potentials and/or gate and
drain potentials.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This Utility Patent Application claims priority to German
Patent Application No. DE 10 2005 041 358.7 filed on Aug. 31, 2005,
which is incorporated herein by reference.
BACKGROUND
[0002] The invention relates to a field plate trench transistor and
a method for producing it.
[0003] FIG. 1 illustrates an extract from a conventional field
plate trench transistor to which the invention relates,
particularly in cross-sectional illustration:
[0004] A field plate trench transistor (also referred to
hereinafter as a trench transistor) 1 has a semiconductor body 2,
in which the trench structure 3 and an electrode structure 4
embedded in the trench structure are provided. A cell array region
(illustrated in the Figure) and an edge region (not illustrated in
the Figure) are provided within the semiconductor body 2. That part
of the semiconductor body 2 which is situated between the trenches
of the trench structure 3 is also referred to as a "mesa
structure". The electrode structure 4 is electrically insulated
from the semiconductor body 2 by means of an insulation structure 5
and has a gate electrode structure 6 and a field electrode
structure 7 arranged below the gate electrode structure and
electrically insulated from the latter. The semiconductor body 2 is
subdivided into a body region 8, a drift region 9 and a drain
region 10. Source regions 11 are formed in the body region 8. The
body region 8 is electrically short-circuited with the source
regions 11 via a source metallization 12. The drain region 10 is
contact-connected by a drain metallization 13. The potential of the
gate electrode structure 6 is at gate potential and the potential
of the field electrode structure 7 is at source potential. The gate
electrode structure 6 is electrically insulated from the source
metallization 12 by means of an insulation structure 14.
[0005] What is disadvantageous about the trench transistor 1
described above is that in the off-state case, that region of the
insulation structure 5 which is situated in the bottom of the
trench structure 3 has to withstand virtually the full reverse
voltage, which means that the thickness of the insulation structure
5 is not permitted to fall below a specific minimum value. This in
turn has the consequence that limits are imposed on the degree of
miniaturization of the trench structure 3 with performance
parameters remaining the same.
[0006] In order to solve this problem, it is known to set the
potential of the field electrode structure 7 in the off-state case
to a potential lying between source potential and drain
potential.
[0007] For these and other reasons, there is a need for the present
invention.
SUMMARY
[0008] The present invention provides a field plate trench
transistor having a semiconductor body. In one embodiment, the
semiconductor has a trench structure and an electrode structure
embedded in the trench structure. The electrode structure being
electrically insulated from the semiconductor body by an insulation
structure and having a gate electrode structure and a field
electrode structure. The field plate trench transistor has a
voltage divider configured such that the field electrode structure
is set to a potential lying between source and drain
potentials.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The accompanying drawings are included to provide a further
understanding of the present invention and are incorporated in and
constitute a part of this specification. The drawings illustrate
the embodiments of the present invention and together with the
description serve to explain the principles of the invention. Other
embodiments of the present invention and many of the intended
advantages of the present invention will be readily appreciated as
they become better understood by reference to the following
detailed description. The elements of the drawings are not
necessarily to scale relative to each other. Like reference
numerals designate corresponding similar parts.
[0010] FIG. 1 illustrates an extract from a conventional field
plate trench transistor in cross-sectional illustration.
[0011] FIG. 2 illustrates an extract from a first embodiment of the
field plate trench transistor according to the invention in
cross-sectional illustration.
[0012] FIG. 3 illustrates an extract from a second embodiment of
the field plate trench transistor according to the invention in
cross-sectional illustration.
[0013] FIG. 4 illustrates an extract from a third embodiment of the
field plate trench transistor according to the invention in
cross-sectional illustration.
[0014] FIG. 5 illustrates an extract from a possible realization of
the embodiment illustrated in FIG. 4, in cross-sectional
illustration.
[0015] FIG. 6 illustrates an extract from a fourth embodiment of
the field plate trench transistor according to the invention in
cross-sectional illustration.
[0016] FIG. 7 illustrates a first process of a first embodiment of
the production method according to the invention in cross-sectional
illustration.
[0017] FIG. 8 illustrates a second process of a first embodiment of
the production method according to the invention in cross-sectional
illustration.
[0018] FIG. 9 illustrates a third process of a first embodiment of
the production method according to the invention in cross-sectional
illustration.
[0019] FIG. 10 illustrates a fourth process of a first embodiment
of the production method according to the invention in
cross-sectional illustration.
[0020] FIG. 11 illustrates a fifth process of a first embodiment of
the production method according to the invention in cross-sectional
illustration.
[0021] FIG. 12 illustrates a sixth process of a first embodiment of
the production method according to the invention in cross-sectional
illustration.
[0022] FIG. 13 illustrates a seventh process of a first embodiment
of the production method according to the invention in
cross-sectional illustration.
[0023] FIG. 14 illustrates an eighth process of a first embodiment
of the production method according to the invention in
cross-sectional illustration.
[0024] FIG. 15 illustrates a ninth process of a first embodiment of
the production method according to the invention in cross-sectional
illustration.
[0025] FIG. 16 illustrates a tenth process of a first embodiment of
the production method according to the invention in cross-sectional
illustration.
[0026] FIG. 17 illustrates a first process of a second embodiment
of the production method according to the invention in
cross-sectional illustration.
[0027] FIG. 18 illustrates a second process of a second embodiment
of the production method according to the invention in
cross-sectional illustration.
[0028] FIG. 19 illustrates a third process of a second embodiment
of the production method according to the invention in
cross-sectional illustration.
[0029] FIG. 20 illustrates a fourth process of a second embodiment
of the production method according to the invention in
cross-sectional illustration.
[0030] FIG. 21 illustrates a fifth process of a second embodiment
of the production method according to the invention in
cross-sectional illustration.
[0031] FIG. 22 illustrates a sixth process of a second embodiment
of the production method according to the invention in
cross-sectional illustration.
[0032] FIG. 23 illustrates a seventh process of a second embodiment
of the production method according to the invention in
cross-sectional illustration.
[0033] FIG. 24 illustrates an extract from a known field plate
trench transistor in cross-sectional illustration.
[0034] FIG. 25 illustrates diagrams showing the ideal
voltage/current profile within a field electrode structure of a
field plate trench transistor.
[0035] FIG. 26 illustrates a basic schematic circuit diagram of a
fifth embodiment of the field plate trench transistor according to
the invention.
[0036] FIG. 27 illustrates a detail view of an extract from one
possible realization of the embodiment illustrated in FIG. 26.
[0037] FIG. 28 illustrates a detail view of an extract from one
possible realization of the embodiment illustrated in FIG. 26.
[0038] FIG. 29 illustrates a detail view of an extract from one
possible realization of the embodiment illustrated in FIG. 26.
[0039] FIG. 30 illustrates a basic schematic circuit diagram of a
seventh embodiment of the field plate trench transistor according
to the invention.
[0040] FIG. 31 illustrates an extract from one possible realization
of the embodiment illustrated in FIG. 30, in cross-sectional
illustration.
[0041] FIG. 32 illustrates a plan view of one possible realization
of the embodiment illustrated in FIG. 26.
[0042] FIG. 33 illustrates a plan view of one possible realization
of the embodiment illustrated in FIG. 26.
[0043] FIG. 34 illustrates a plan view of one possible realization
of the embodiment illustrated in FIG. 30.
DETAILED DESCRIPTION
[0044] In the following Detailed Description, reference is made to
the accompanying drawings, which form a part hereof, and in which
is shown by way of illustration specific embodiments in which the
invention may be practiced. In this regard, directional
terminology, such as "top," "bottom," "front," "back," "leading,"
"trailing," etc., is used with reference to the orientation of the
Figure(s) being described. Because components of embodiments of the
present invention can be positioned in a number of different
orientations, the directional terminology is used for purposes of
illustration and is in no way limiting. It is to be understood that
other embodiments may be utilized and structural or logical changes
may be made without departing from the scope of the present
invention. The following detailed description, therefore, is not to
be taken in a limiting sense, and the scope of the present
invention is defined by the appended claims.
[0045] The present invention provides a field plate trench
transistor with which the potential to which the field electrode
structure is to be set can be generated as simply as possible.
[0046] In one embodiment, the field plate trench transistor
according to the invention has a semiconductor body, in which:
[0047] a trench structure and
[0048] an electrode structure embedded in the trench structure are
provided, the electrode structure being electrically insulated from
the semiconductor body by an insulation structure and having a gate
electrode structure and a field electrode structure arranged below
and/or alongside the gate electrode structure and electrically
insulated from the latter.
[0049] A voltage divider provided in and/or on the semiconductor
body is electrically connected to the field electrode structure or
integrated into the latter in such a way that the field electrode
structure is set to a potential lying between source and drain
potentials and/or between gate and drain potentials.
[0050] The term "electrode structure" is to be understood to mean,
in particular, all electrodes provided within the trench structure.
The term "gate electrode structure" is to be understood to mean, in
particular, all parts of the electrode structure which function as
gate. The term "field electrode structure" is to be understood to
mean, in particular, all parts of the electrode structure which
function as field electrode.
[0051] In one embodiment of the invention, the field electrode
structure is divided into a plurality of field electrode regions
arranged vertically one above another and the voltage divider is
divided into a plurality of voltage divider regions, each voltage
divider region being electrically connected to a field electrode
region or integrated into the latter, so that at least two
different field electrode regions are at different potentials. For
this purpose, the field electrode regions within the trench
structure are electrically insulated from one another.
[0052] The voltage divider may be realized as a series circuit
having at least one resistor (or a MOS transistor or a capacitance
in each case functioning as a resistor) and at least one diode
which is forward-biased with respect to the drain potential or as a
series circuit having a plurality of diodes which are
forward-biased with respect to the source potential, which are
connected between source and drain potentials.
[0053] In one embodiment, at least one diode is a zener diode.
[0054] The different field electrode regions may be electrically
insulated from one another, for example, and the voltage divider
may be provided outside the field electrode structure.
[0055] In another embodiment, the different field electrode regions
are electrically connected to one another, and the voltage divider
is provided within the field electrode structure. In this case, pn
diodes are preferably provided between the field electrode regions,
in such a way that the pn diodes are interlinked with one another
via the field electrode regions to form a vertically running diode
series circuit. In this case, the upper end of the diode series
circuit may directly adjoin a source metallization layer of the
transistor, and the lower end of the diode series circuit directly
adjoins a drift zone provided within the semiconductor body.
[0056] In one embodiment, the voltage divider has at least one
substrate diode which is connected between source and drain
potentials and is forward-biased with respect to the drain
potential, the substrate diode being formed by the pn junction
between a semiconductor zone of a first conduction type provided in
the semiconductor body, in particular within the mesa structure,
and the part of the semiconductor body of a second conduction type
lying below the semiconductor zone, the semiconductor zone of the
first conduction type being produced together with the body zones
of the trench transistor in one process.
[0057] That end of the substrate diode which faces the source
potential is connected to a voltage limiting element connected
between substrate diode and source potential, which voltage
limiting element prevents the potential of the field electrode
structure from exceeding a potential maximum value and/or falling
below a potential minimum value in the switched-on state (on
state). In this case, the voltage limiting element may be at least
partly realized in the form of one or a plurality of
series-connected diodes which are forward-biased with respect to
the drain potential and are formed within the cell array region or
the edge region of the semiconductor body or within the trench
structure. The voltage limiting element may be at least partly
formed in the form of a MOS transistor, the body zone of which
corresponds to the semiconductor zone of the first conduction type
of the substrate diode. Moreover, the voltage limiting element may
be at least partly formed in the form of one or a plurality of
capacitive elements provided within the semiconductor body.
[0058] Furthermore, that end of the substrate diode which faces the
source potential is connected to a pull-down element connected
between substrate diode and source potential or gate potential,
which pull-down element prevents the potential of the field
electrode structure from drifting, in the off state of the
transistor, to drain potential as a result of leakage currents
occurring within the substrate diode.
[0059] In this case, the pull-down element may be at least partly
realized in the form of a resistance element provided within the
mesa structure, the gate electrode structure, the field electrode
structure or within a conductive element provided above the
semiconductor body and electrically insulated from the latter. The
pull-down element may be at least partly realized in the form of a
transistor formed within the semiconductor body, in particular
within the mesa structure. The pull-down element may be at least
partly formed in the form of at least one capacitive element
provided within the semiconductor body.
[0060] The substrate diode has a reduced breakdown voltage compared
with the transistor elements provided within the cell array of the
transistor.
[0061] The invention furthermore provides a method for producing
the field plate trench transistor according to the invention,
proceeding from a semiconductor body in which:
[0062] a trench structure and
[0063] an insulation structure lining the trench structure are
provided, the remaining free space within the trench structure
extending downward toward the semiconductor body,
[0064] having the following process of:
[0065] filling the free space by alternately depositing n- and
p-doped semiconducting material and metal-containing material.
[0066] In another embodiment, the filling may be effected by
repeatedly performing the following: depositing semiconducting
material (completely filling the free space), etching back the
deposited semiconducting material into the free space, carrying out
a coating process with regard to the semiconducting material that
has remained in the free space, and producing a silicide layer on
the semiconducting material.
[0067] In one embodiment, that part of the insulation structure
which is formed in the upper region of the trench structure is
partly etched back into the trench structure, and the gate
electrode structure is introduced into the resulting cutout.
[0068] In the Figures, identical or mutually corresponding regions,
components and component groups are identified by the same
reference numerals. Furthermore, the conduction types of all the
embodiments may be configured inversely, that is to say that n-type
zones may be replaced by p-type zones, and vice versa.
[0069] FIG. 2 illustrates a first embodiment A of the field plate
trench transistor according to the invention.
[0070] A field plate trench transistor (also referred to
hereinafter as a trench transistor) 1 has a semiconductor body 2,
in which a trench structure 3 and an electrode structure 4 embedded
in the trench structure are provided. The electrode structure 4 is
electrically insulated from the semiconductor body 2 by means of an
insulation structure 5 and has a gate electrode structure 6 and a
field electrode structure 7 arranged below the gate electrode
structure and electrically insulated from the latter. The
semiconductor body 2 is subdivided into a body region 8, a drift
region 9 and a drain region 10. Source regions 11 are formed in the
body region 8. The body region 8 is electrically short-circuited
with the source regions 11 via a source metallization 12. The drain
region 10 is contact-connected by a drain metallization 13. The
potential of the gate electrode structure 6 is at gate potential
and the potential of the field electrode structure 7 is at source
potential. The gate electrode structure 6 is electrically insulated
from the source metallization 12 by means of an insulation
structure 14.
[0071] According to one embodiment of the invention, a voltage
divider 15 is provided in and/or on the semiconductor body 2, the
voltage divider being electrically connected to the field electrode
structure 7. By means of the voltage divider 15, the field
electrode structure 7 is set to a potential lying between source
and drain potentials. In this embodiment, the voltage divider 15
includes a series circuit having a resistor 16 and a diode 17 which
is forward-biased with respect to the source potential (source
terminal). The diode 17 is a zener diode in this embodiment.
[0072] FIG. 3 illustrates a second embodiment B of the field plate
trench transistor according to the invention. The embodiment B
differs from the embodiment A by the fact that the voltage divider
15 is realized as a series circuit having two diodes 17 which are
in each case forward-biased with respect to the source potential
and are connected between source and drain potentials. Furthermore,
a resistor 16 is connected in parallel with the diode 17 facing the
source metallization 12, the resistor serving for optimizing the
switching properties of the field plate trench transistor. The
resistor 16 may be omitted.
[0073] In the embodiments A and B, a potential value lying between
source potential and drain potential is in each case generated by
means of the voltage divider 15. In the third embodiment C of the
field plate trench transistor according to the invention as
illustrated in FIG. 4, three different potential values lying
between source potential and drain potential are generated by means
of the voltage divider 15, which is divided into three voltage
divider regions 15.sub.1 to 15.sub.3. Furthermore, the field
electrode structure 7 is divided into a plurality of field
electrode regions 7.sub.1 to 7.sub.3 arranged vertically one above
another. The field electrode regions 7.sub.1 to 7.sub.3 are
electrically insulated from one another within the trench structure
3 by means of corresponding insulations 18. Each field electrode
region 7.sub.1 to 7.sub.3 is electrically connected to a dedicated
voltage divider region 15.sub.1 to 15.sub.3, so that the field
electrode regions 7.sub.1 to 7.sub.3 are at different potential
values.
[0074] The voltage divider 15 illustrated in the embodiments A to C
may be provided within the cell array of the field plate trench
transistor or may be provided outside the cell array in or on the
semiconductor body. The resistors 16 may be omitted in the
embodiment C since they only serve for optimizing the switching
properties of the field plate trench transistor.
[0075] As is illustrated in FIG. 5, the series circuit including
the diodes 17 may be realized for example in the form of an
interlinking of p-type zones and n-type zones which are formed
within the semiconductor body, for example each p-doped zone 19
being electrically connected to one of the field electrode regions
7.sub.1 to 7.sub.3. In this case, the topmost p-type zone 19 is
electrically connected to the source metallization 12, and the
bottommost n-type zone 20 is electrically connected to the drain
metallization 13. The n-doped zones 20 are in part short-circuited
with the p-doped zones 19 by metal elements 21 or otherwise highly
conductive materials. The sequence of p-type zones and n-type zones
alternating with one another forms a series circuit of diodes, for
example, zener diodes.
[0076] FIG. 6 illustrates a fourth embodiment D, in which the
voltage divider 15 in the form of a diode series circuit is
integrated directly into the field electrode structure 7. In this
embodiment, n-type zones, p-type zones and metal zones alternate
with one another in this order. The topmost p-type zone 19 is
electrically connected to the source metallization 12, and the
bottommost n-type zone 20 is electrically connected to the drain
metallization 13. By means of the diode series circuit provided
within the field electrode structure 7, a continuously increasing
or decreasing potential profile is generated within the field
electrode structure 7. In this embodiment, the field electrode
structure is completely electrically insulated from the
semiconductor body 2 apart from corresponding electrical
connections.
[0077] In the description below, a first embodiment of the
production method according to the invention will be explained with
reference to FIGS. 7 to 16. The starting point, as illustrated in
FIG. 7, is a semiconductor body 2, in which a trench structure 3 is
provided. Body regions 8 and source regions 11 are formed in the
mesa zones 22 provided between the trenches of the trench structure
3. A patterned hard mask layer 23 serves for introducing the trench
structure 3 into the semiconductor body 2, the hard mask layer
being removed again after the trench structure has been introduced
into the semiconductor body 2.
[0078] In a first process (FIG. 8) a thermal oxidation process is
carried out, by means of which parts of the semiconductor material
of the semiconductor body 2 are converted into an insulation
structure 5 (oxide structure). A nitride layer 24 is deposited on
the insulation structure 5.
[0079] In a second process (FIG. 9), that part of the insulation
structure which is situated in the bottom region of the trench
structure 3 and the horizontally running part of the insulation
structure 5 and of the nitride layer 24 are completely or partly
removed by means of an anisotropic etching-back process. In this
case, the etching parameters are chosen such that the free space 25
produced within the trench structure 3, in the bottom region of the
trench structure 3, directly adjoins the semiconductor body 2. In a
third process (FIG. 10) the free space 25 is filled alternately
with p-doped material 19, n-doped material 20 and a metal or
metal-containing material 21. This is done until the free space 25
has been completely filled (fourth process, see FIG. 1 1). Each
deposition operation is followed by a corresponding etching-back
process which sets the thickness of the p-doped zones 19, of the
n-doped zones 20 and of the metal-containing elements 21 to
corresponding values. As an alternative, the filling of the free
space 25 may be effected by repeatedly performing the following:
depositing semiconducting material of one doping type (completely
filling the free space 25), etching back the deposited
semiconducting material into the free space, carrying out a coating
process with regard to the semiconducting material that has
remained in the free space (in order to divide the semiconducting
material that has remained in the free space into two regions of
different doping), producing a silicide layer on the semiconductor
conducting material (containing two doping regions).
[0080] In a fifth process (FIG. 12) the upper part of the
insulation structure 5 is etched back into the trench structure 3.
A thermal oxidation process is subsequently carried out, in such a
way that cutouts 26 arise in the upper region of the trench
structure 3.
[0081] In a sixth process (FIG. 13) the cutouts 26 are filled with
conductive material, with the result that a gate electrode
structure 6 arises.
[0082] In a seventh process (FIG. 14) the horizontally running part
of the insulation structure 5 is removed by means of an
etching-back process. Afterward (FIG. 15) a source metallization 12
is deposited over the whole area of the semiconductor body 2, with
the result that the topmost p-doped zone 19 is electrically
connected to the source metallization 12, and the bottommost
p-doped zone 19 is electrically connected to the semiconductor body
2.
[0083] In this way, it is possible to produce a field electrode
structure 7, the upper end of which is electrically connected to
the source metallization 12, and the lower end of which is
electrically connected to the semiconductor body 2. In this way, a
series circuit of diodes is formed within the field electrode
structure 7, with the result that a continuously falling/rising
potential profile occurs within the field electrode structure 7
between the semiconductor body 2 and the source metallization 12.
The potential profile brings about a continuous reduction of the
potential that is to be reduced in the off-state case.
[0084] As an alternative, the production process may also be
conducted such that the bottommost n-doped zone 20 is omitted, that
is to say is replaced by a p-doped zone 19.
[0085] In the description below, a second embodiment of the
production method according to the invention will be described with
reference to FIGS. 17 to 23.
[0086] The starting point is the state illustrated in FIG. 17, in
which a trench structure 3 has been introduced in a semiconductor
body 2 and source regions 11 and body region 8 have been provided
in the mesa zones 22. The surface of the semiconductor body 2 is
coated with an oxide layer or nitride layer 27.
[0087] In a first process (FIG. 18) the nitride layer 27 is
patterned in such a way that residues of the nitride layer 27
remain only in the bottom region of the trench structure 3. A
thermal oxidation process is subsequently performed, whereby an
oxide layer 28 is formed on the parts of the semiconductor body 2
which are not covered by the nitride layer 27.
[0088] In a second process (FIG. 19), the residual parts of the
nitride layer 27 are removed and a further nitride layer 29 is
deposited across the entire semiconductor body 2, the horizontally
running parts of the further nitride layer being removed by means
of an anisotropic etching process. The free spaces 25 that have
remained in the trench structure 3 are filled by deposition and
etching-back processes with an alternating arrangement of p-doped
zones 19, n-doped zones 20 and metal elements or metal-containing
elements 21 (e.g., silicide or tungsten).
[0089] The free spaces 25 are filled up to a vertical position
lying above the vertical position of the surface of the source
regions 11 (FIG. 20). In a fifth process (FIG. 21) a CMP process is
carried out (chemical mechanical polishing). The upper part of the
oxide layer 28 is subsequently etched back into the trench
structure 3 by means of an etching process.
[0090] The resulting cutouts in the insulation structure 5 are then
lined with an oxide layer 30 (gate oxide), and a gate electrode
structure 6 is introduced into the free spaces that have still
remained.
[0091] Finally (FIG. 23), a source metallization 12 is deposited,
which contact-connects both the source regions 11 and the topmost
n-doped zones 20 of the field electrode structure 7.
[0092] FIG. 24 illustrates an extract from a conventional field
plate trench transistor, which differs from the field plate trench
transistor illustrated in FIG. 1 merely in terms of the concrete
configuration of the gate electrode structure 6 and the concrete
configuration of the body region 8.
[0093] FIG. 25(a) illustrates the ideal voltage profile 30 of the
field electrode structure 7 for a given drain voltage profile 31
and gate voltage profile 32, FIG. 25(b) illustrates the ideal
charging current profile 33 of the field electrode structure 7 and
the gate electrode charging current profile 34 corresponding
thereto: with ideal circuitry connection, FP must block in both
directions relative to the rear side. The charging currents of the
field plate have the same direction as the gate charging currents.
The field plate must be subjected to charge reversal relative to
source (or drain) if the gate driver is not to be loaded.
[0094] In order to achieve at least approximately ideal voltage and
current profiles in the field electrode structure 7 (also referred
to as field electrode structure or field plate), a field electrode
structure 7 is used which is connected to a substrate diode
structure 35, a pull-down structure 36 and a voltage limiting
structure 37 in the manner specified in FIG. 26. "G", "S" and "D"
are to be understood to mean gate potential, source potential and
drain potential. The following should be noted with regard to the
functioning of this circuit:
[0095] a) Transistor switched off:
[0096] body substrate diode with pull-down element holds the field
plate voltage at V.sub.D-V.sub.br (body substrate diode)
[0097] pull-down current is conducted away via source
[0098] b) Transistor switched on:
[0099] the pull-down holds the field plate at source potential and
thus limits the Ron loss due to an excessively low field plate
potential
[0100] c) Switch-on operation:
[0101] drain voltage drops
[0102] the field plate is thus pulled capacitively in the direction
of negative voltages
[0103] the voltage limiting element prevents the voltage from
dropping to large negative voltages
[0104] the pull-down element "pulls" the field plate voltage (with
a certain delay) to source potential
[0105] d) Switch-off operation:
[0106] drain voltage rises
[0107] field plate voltage concomitantly rises capacitively
[0108] in order that it does not rise excessively highly, the
discharge current of the field electrode-substrate capacitance
possibly has to flow away via pull-down element or voltage limiting
element.
[0109] FIG. 27 discloses an example of an embodiment of the
substrate diode structure 35 illustrated in FIG. 26. The substrate
diode structure 35 includes pn junctions between p-doped
semiconductor zones 38/p.sup.+-doped semiconductor zones 39
provided within the mesa zones 22 and the parts of the
semiconductor body 2 (n-doped) which lie below the semiconductor
zones, each of the pn junctions forming a part of the substrate
diode structure 35. Contact-connections 40 are provided in the
upper region of the p-doped zones 38, and are electrically
connected to the field electrode structure 7. FIG. 32 illustrates a
plan view of a field plate trench transistor according to the
invention in order to illustrate that the region in which the
substrate diode structure 35 is formed is spaced apart from the
cell array region 47 of the field plate trench transistor. The
p-doped zones 38 can be produced together with the body regions 8
in one process. The p.sup.+-doped zones 39 can be produced together
with corresponding body contact zones 41 in one process.
[0110] FIG. 32 illustrates the case where the width of the mesa
zone 22 in which the substrate diode structure 35 is formed is
wider than the mesa zone 22 of the cell array region. FIG. 33
illustrates the case where the width of the mesa zone 22' in which
the substrate diode structure 35 is formed is twice as wide as the
mesa width 22 within the cell array region 47. By means of the mesa
zone 22' which is twice as wide, it is possible to obtain a
reduction of the breakdown voltage of the substrate diode structure
in comparison with the breakdown voltage of the transistor elements
localized within the cell array region 47. The breakdown voltage is
freely selectable by variation of the mesa width down to
approximately 50% of the breakdown voltage of the cell array. The
breakdown is pinned in the mesa center at least in technology
variants with body reinforcement and is thus noncritical with
regard to drift processes.
[0111] FIG. 28 illustrates that n+-doped zones 42 can be provided
within the p-doped zone 38, the pn junction formed from the
n+-doped zone 42 and the p-doped zone 38 corresponding to the
voltage limiting structure 37 illustrated in FIG. 26. This case is
likewise illustrated in plan view in FIG. 34. Furthermore, FIG. 34
illustrates a resistance element 43 having a p-doped zone which is
formed in the drift region 9 and connects the body region 8 of the
cell array to the p-doped zone 38 of the substrate diode structure
35. The resistance element 43 corresponds to the pull-down
structure 36 illustrated in FIG. 26. FIG. 28 accordingly
illustrates a body substrate diode with integrated NMOS for voltage
limiting during switch-on. When the transistor is switched on, the
thick oxide transistor in the body substrate diode is also switched
on. The NMOS transistor prevents the field electrode from being
pulled capacitively to negative voltages. During switch-off, the
NMOS transistor remains switched on for a certain period of time
and prevents the field plate potential from concomitantly rising
too far.
[0112] FIG. 29 illustrates an alternative embodiment of the cell
array region 47, in which an electrode shielding structure 44 is
provided between the field electrode structure 7 and the gate
electrode structure 6 within the trench structure 3, and can
prevent or reduce a capacitive coupling of the field electrode
structure 7 to the gate electrode structure 6. The electrode shield
structure 44 has to be connected to source with relatively low
impedance in order to be able to conduct away the large
charge-reversal currents during switching. The dielectric between
electrode shielding structure and field electrode structure 7 must
have the same dielectric strength as the dielectric between field
electrode structure 7 and silicon epitaxial layer. The capacitance
ratio of electrode shielding structure/field electrode structure
and field structure/silicon epitaxial layer must be approximately
1:1 in order that the charge-reversal currents can be conducted
away capacitively during switching.
[0113] FIG. 30 illustrates an alternative interconnection of the
substrate diode structure 35 with respect to FIG. 26. The
difference is that a further diode structure 45 is provided and the
pull-down structure 36 is connected to gate potential. FIG. 31
discloses one possible realization of the interconnection
illustrated in FIG. 30. The essential difference with respect to
the embodiment illustrated in FIG. 28 is that the n+-doped zones 42
have been merged to form a common n.sup.+-doped zone 46 with the
result that the p.sup.+-doped zones do not directly adjoin the
contact-connections 40. The following should be noted with regard
to the functioning of the circuit illustrated in FIG. 30:
[0114] Transistor switched off:
[0115] body substrate diode with pull-down elements holds field
plate voltage at V.sub.D-V.sub.br (body substrate diode)
[0116] pull-down current is conducted away via external gate
shunt
[0117] Transistor switched on:
[0118] the pull-down element holds the field plate at gate
potential and thus optimizes Ron by forming an accumulation layer
in the lower trench region
[0119] additional diode prevents a forward current from drain to
field plate
[0120] Switch-on operation:
[0121] drain voltage falls
[0122] the field plate is thus pulled capacitively in the direction
of negative voltages
[0123] the voltage limiting element prevents the voltage from
falling to large negative voltages
[0124] the pull-down pulls the field plate voltage (with a certain
delay) to gate potential
[0125] Switch-off operation:
[0126] drain voltage rises
[0127] the field plate voltage concomitantly rises capacitively
[0128] in order that it does not rise excessively highly, the
discharge current of the field plate-substrate capacitance possibly
has to flow away via pull-down or voltage limiter.
[0129] Further embodiments of the invention will be explained in
the description below.
[0130] In the conventional field plate trench transistor, the
polysilicon filling of the trench is completely at gate potential
or is divided into an upper region at gate potential and a lower
region at source potential. In any event the polysilicon in the
trench is completely connected to the low side of the switch. This
means that the oxide in the trench bottom (depending on specific
embodiment) has to withstand almost the full reverse voltage of the
transistor. This condition limits the thickness of the oxide toward
the bottom. However, the minimum trench width is also determined
with the oxide thickness. Since the mesa width has actually already
been reduced to a minimum in the present field plate trench
technology, there is only little shrink potential in this concept.
Likewise, this limitation means it is not possible to expand the
field plate trench concept to voltage classes above 200 V.
[0131] The documents U.S. Pat. No. 6,677,641 B2 and DE 10339455.9
describe the idea of incorporating into the trench bottom region
one or a plurality of further field plate(s) which, in the
off-state case, is (are) held at intermediate potentials between
source and drain and thus enable(s) a step-by-step reduction of the
voltage even in the trench. The oxides in the trench then only have
to take up in each case part of the reverse voltage and can thus
become thinner. This means that the way is free for further shrinks
of the field plate trench technology and for expanding the concept
to higher voltage classes.
[0132] In the application the question remains open as to how the
intermediate potentials mentioned can be generated within a
discrete MOS switch technology. The invention specifies a number of
possibilities in this respect.
[0133] According one embodiment of the invention, by means of a
voltage divider one or a plurality of electrodes lying one below
another in the trench are brought to a potential between source
(low side) and drain (high side) in such a way that only a fraction
of the voltage difference (drain-source) is present laterally
between the electrode and silicon mesa.
[0134] As a result, the field plate oxide can be made thinner and
the transistor can be shrunk further. The voltage divider is
realized by at least one zener diode and a resistor or by a
plurality of series-connected zener diodes. The zener diodes are
integrated either in the chip edge as a separate component or
vertically in the field plate technology. The nodes between the
components are thus at a defined potential between source and
drain. In order to prevent the np junctions from blocking when the
transistor is switched on, and to provide the possibility for
discharging the field plates when the transistor is switched on,
e.g., metallic short circuits are used according to the
invention.
[0135] One embodiment of the invention accordingly consists in
realizing the driving of an additional deep field electrode in the
trench of the DMOS cell by means of a series circuit including at
least one zener diode and a resistor or by means of a series
circuit having a plurality of zener diodes. The potentials
established at the nodes between the components are thus held at
the desired potential between source and drain. In the dynamic case
(switch-on: the field plate is "pulled" capacitively below the
source potential), the diodes which are forward-biased with respect
to the source prevent the field electrode being "pulled" below
n.times.Vf (n=number of zener diodes between the electrode and
source, Vf=forward voltage of the zener diodes). During switch-off,
the zener breakdown of the diodes prevents the potential of the
electrode from being able to rise above the defined zener voltage.
With the use of zener diodes within the field electrode, moreover,
the lead resistance for charge reversal is drastically reduced in
the dynamic case, which has a particularly effect on the switching
times. No additional space is required in this case.
[0136] FIG. 1 illustrates a known trench transistor (realized in
SFET3 EDP). The additional electrode in the lower trench region is
fixedly connected up to the source. This means that the field plate
oxide must be made thick enough to withstand the maximum
source-drain voltage. FIG. 2 illustrates an external voltage
divider which connects the field electrode toward drain with a
zener diode. The zener diode is intended to have a breakdown
voltage which is expediently half the source-drain breakdown
voltage of the transistor. The resistor to source prevents the
electrode potential from drifting in the off-state case as a result
of the leakage current of the zener diode in the direction of the
drain voltage. During switch-off, the resistor prevents the field
electrode from being pulled capacitively to negative potentials.
This last is achieved more effectively if a diode is connected in
parallel with the resistor (FIG. 3).
[0137] In this case, the resistor may have a very high resistance
or be entirely obviated. The diodes may be produced in a body well
between two trenches by means of additional implantation zones or
by means of polydiodes on field oxide at the edge of the chip. FIG.
4 illustrates how a plurality of insulated, vertically arranged
electrodes have to be connected to a voltage divider having a
plurality of zener diodes in order to achieve even smaller
potential differences between electrode and drift zone. FIG. 5
illustrates the realization by means of n-type and p-type zones in
a polysilicon strip and metal short circuits which may be situated
on the chip edge.
[0138] FIG. 6 illustrates a structure in which the zener diodes are
integrated into the vertical field electrode. FIGS. 7 to 23
describe two possible production methods A and B showing how
vertical zener diodes (zener diode chains) of this type could be
produced. The following process would be necessary for a diode
structure in the trench: deposition and etching-back of doped
polysilicon (n-doped for n-MOS transistors), counterdoping near the
surface by coating (e.g., from the vapor phase), self-aligned
silicide (e.g., TiSi) for forming an ohmic contact between p-type
and n-type polysilicon. As a result, the diode chain is switched to
the on state in the reverse direction.
[0139] In one embodiment of the invention, the lowered breakdown
voltage of a body substrate diode with a larger mesa width (or
without a trench boundary) is used to generate a suitable
intermediate voltage between rear side and front side.
[0140] A description will be given of how the potential of the deep
field electrode would have to behave in the ideal case during the
switching of the transistor:
[0141] 1. In the switched-on state, the field electrode ought not
to be at a highly negative voltage, since otherwise a pinch-off of
the epitaxial layer in the mesa structure occurs which brings about
an increased on resistance. The field electrode would ideally be at
a positive voltage which leads to an accumulation in the mesa
structure and thus even additionally lowers the on resistance.
[0142] 2. In the off state, the field electrode ought to be at a
medium potential between rear side and front side, so that the
oxides at trench bottom, trench sidewall and between field
electrode and gate electrode are loaded as uniformly as
possible.
[0143] 3. During switch-on, the field electrode-drain capacitance
must be rapidly charged: the voltage between field electrode and
drain rises from a negative value to zero or even a positive value.
The charge-reversal current should not load the gate driver.
[0144] 4. During switch-off, the field electrode-drain capacitance
must be rapidly discharged: the voltage between field electrode and
drain falls to a negative value. In this case, too, the discharge
current of the field electrode-drain capacitance should not load
the gate driver.
[0145] A body substrate diode may serve to fulfill requirement 2
(see basic circuit diagram, FIG. 26). For this purpose, the body
layer of the diode must be electrically connected to the field
electrode. The lowered breakdown voltage of the diode thus upwardly
limits the voltage between substrate and field electrode. However,
a positive voltage cannot then be present at the field electrode
(relative to source) in the switched-on state since the body
substrate diode would otherwise be forward biased.
[0146] A pull-down element is additionally required, which, in the
off state case, prevents the potential of the field electrode from
slowly drifting up to substrate potential due to the diode leakage
current of the body substrate diode. Moreover, an element is
required which can take up the large charge-reversal currents of
the field electrode during the switching of the trench transistor
(which may be realized in particular as a DMOS) and upwardly and
downwardly limits the voltage of the field electrode (a voltage
limiter). What is essential is that these elements can also be
integrated directly into the trench transistor chip and be realized
with the structure elements afforded by the pure field plate trench
transistor.
[0147] In one embodiment, it is possible to integrate both
pull-down and voltage limiting in the negative direction directly
into the body substrate diode (FIG. 28):
[0148] A lateral PMOS transistor extending from the body of the
diode along trench sidewall, trench bottom or silicon surface to
the body of the DMOS may serve as the pull-down element. For this
purpose, the gate of the PMOS transistor must be at source
potential. The PMOS transistor is thus connected up as a MOS diode
and becomes conductive as the potential of the body of the
substrate diode rises. As an alternative, a simple p-type well
resistance could also connect the p-type zone of the body substrate
diode to body/source of the DMOS.
[0149] A vertical NMOS transistor integrated into the trench
sidewalls of the body substrate diode may be used as voltage
limiting. The gate of the transistor is at gate potential of the
DMOS. This means that the transistor concomitantly switches on when
the DMOS is switched on, and short-circuits the field electrode
potential with the rear side. This prevents the field electrode
from being pulled capacitively to negative voltages.
[0150] Voltage limiting of the field electrode voltage in the
positive direction is not manifested in this embodiment. Here, the
coupling capacitances in the DMOS cell need to be designed such
that the field electrode voltage does not rise too far when the
transistor is turned off. (As an alternative, an additional
voltage-limiting structure would have to be integrated).
[0151] The core of this embodiment consists in realizing the
driving of an additional deep field electrode in the trench of the
DMOS cell directly on the chip in which the cell array is formed,
together with the structure elements made available by the field
plate trench process. The use of a body substrate diode with a
lowered breakdown voltage for setting the field electrode voltage
in the off-state case is an essential aspect of this concept.
[0152] There are also various other possibilities for realizing the
two elements of pull-down and voltage limiting, and they are
described in detail in the accompanying Powerpoint
presentation.
[0153] 1. Possibilities for realizing the pull-down element: [0154]
a. As body resistance in mesa, as gate poly resistance in trench,
as FP poly resistance in trench or as planar poly resistance on
field oxide. [0155] b. As PMOS transistor. Variants: trench bottom,
trench sidewall, silicon surface. [0156] c. As NMOS depletion-mode
transistor with gate oxide.
[0157] 2. Possibilities for realizing the voltage limiting element:
[0158] a. as diode or diode chain in silicon [0159] b. as diode or
diode chain in poly [0160] c. as NMOS transistor in the trench
directly in the body substrate diode structure [0161] d. as
FP-source capacitor
[0162] The function of pull-down and voltage limiter may be
undertaken in part or entirely by suitable tuning of the parasitic
capacitances contained in the transistor cell. For this purpose, as
is illustrated in FIG. 29, a further electrode may be provided in
the trench, the further electrode serving for shielding and tuning
of the capacitances.
[0163] A further variant uses not only the pure body substrate
diode, but an arrangement in which the body substrate diode is
reverse-connected in series with a further diode (see FIGS. 30 and
31). In this variant, the pull-down element may be connected up to
gate instead of to source. In the switched-on state, the additional
diode then prevents a current flow from gate to drain.
[0164] Detailed description of the realization of the voltage
limiting element:
[0165] as diode or diode chain in silicon [0166] as single diode
n-type portion connected to the p-type zone of the body mesa diode
and the p-type portion connected to the source (if the field
electrode voltage becomes < source voltage, diode opens, and if
the field electrode voltage becomes > the breakdown voltage (to
be defined > zener diode), the voltage can be upwardly limited)
[0167] can possibly be combined with an NMOS transistor as
pull-down (see above)
[0168] as diode or diode chain in poly [0169] requires the
integration of a polydiode into the technology
[0170] as NMOS transistor in the trench directly in the body
substrate diode structure [0171] The gate of the transistor would
have to be at DMOS gate potential. [0172] In the off-state case,
therefore, the gate oxide of the transistor is loaded with the full
field plate voltage. [0173] A thick oxide transistor is thus
necessary. [0174] The body substrate diode must contain a source
with source-bulk short circuit. [0175] The field plate-substrate
capacitance is charged from drain during the switch-on operation.
[0176] Possible problem: bipolar parasitic in the body substrate
diode. However: diode is only connected to field plate and,
therefore, cannot carry an unlimited current in any case.
[0177] as field electrode-source capacitor [0178] For the
capacitive decoupling of field electrodes and gate in the cell
array, it may be necessary in any case to introduce an additional
central (third) field plate at source potential. [0179] Given
suitable setting of the capacitance ratio between substrate and
lower field plate and between lower field plate and central
(source) plate, the use of a separate voltage limiting element may
be unnecessary. [0180] Problem: geometrically given capacitance
ratio approximately 3:1.
[0181] Detailed description of the realization of the pull-down
element:
[0182] as body resistance in mesa
[0183] as gate poly resistance in trench or as poly meander on FOX
(field electrode oxide)
[0184] as FP poly resistance in trench as PMOS transistor: [0185]
Variants: trench bottom, trench sidewall, silicon surface. [0186]
Problem: bulk control [0187] Gate must be connected to source. In
the switched-off state of the DMOS, the PMOS transistor is turned
on to the greatest extent. Transistor can hardly take up the
discharge current of the field plate during switch-off.
Consequence: field plate control exhibits an overshoot during
turn-off.
[0188] as NMOS transistor: lateral thick oxide transistor in the
trench. [0189] Gate voltage=field plate voltage. [0190] Possibly a
plurality of transistors in series required: N+ to body breakdown
limits FP voltage. If a separately lightly doped extended source
implantation exists in the technology, it could be used to achieve
a diode with a sufficiently high breakdown voltage. [0191]
Transistor chain may simultaneously serve as a zener diode chain
which limits the field electrode voltage in respect of a negative
value. [0192] Advantage: diode chain can accept the discharge
current of the field plate in the avalanche mode during switch-off.
[0193] Problem: in the case of overvoltage, a large current flows
via this path. Therefore, either the same diode chain must also be
used as gate zener ring, or the breakdown voltage of the DMOS must
be reliably less than the breakdown voltage of the diode chain.
[0194] Problem: Transistor drifting due to avalanche mode. [0195]
Necessary: shallow contact hole, since N+ must be connected
separately from P+.
[0196] as NMOS depletion-mode transistor with gate oxide [0197] In
this case, too: transistor chain required owing to breakdown
voltage N+ to body [0198] Local interconnection of the gate
possible, therefore gate oxide [0199] Likewise required: shallow
contact hole.
[0200] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that a variety of alternate and/or equivalent
implementations may be substituted for the specific embodiments
shown and described without departing from the scope of the present
invention. This application is intended to cover any adaptations or
variations of the specific embodiments discussed herein. Therefore,
it is intended that this invention be limited only by the claims
and the equivalents thereof.
* * * * *