U.S. patent application number 11/459475 was filed with the patent office on 2007-02-08 for semiconductor memory device and method of operating the same.
Invention is credited to Yukio FUKUZO, Hermann RUCKERBAUER, Dominique SAVIGNAC, Ralf SCHLEDZ, Christian SICHERT.
Application Number | 20070033489 11/459475 |
Document ID | / |
Family ID | 37609641 |
Filed Date | 2007-02-08 |
United States Patent
Application |
20070033489 |
Kind Code |
A1 |
RUCKERBAUER; Hermann ; et
al. |
February 8, 2007 |
Semiconductor Memory Device and Method of Operating the Same
Abstract
A semiconductor memory device includes semiconductor memory
cells with at least one memory cell capable of acting either in a
first mode, wherein it functions as a storage device for ECC
information, or in a second mode, wherein it functions as either as
a redundant memory cell or a as a cell storing ordinary
information. The semiconductor memory device further includes a
signal control device for signaling if the at least one memory cell
is to be used either in the first mode or in the second mode. A
method of operating a semiconductor memory device is also provided
including the steps of registering a status of a signal device and,
depending on the status of the signal device, operating the at
least one memory cell either in the first mode or in either of the
selected second modes.
Inventors: |
RUCKERBAUER; Hermann; (Moos,
DE) ; SAVIGNAC; Dominique; (Ismaning, DE) ;
SCHLEDZ; Ralf; (Zolling, DE) ; SICHERT;
Christian; (Munchen, DE) ; FUKUZO; Yukio;
(Munchen, DE) |
Correspondence
Address: |
EDELL, SHAPIRO & FINNAN, LLC
1901 RESEARCH BLVD.
SUITE 400
ROCKVILLE
MD
20850
US
|
Family ID: |
37609641 |
Appl. No.: |
11/459475 |
Filed: |
July 24, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11182063 |
Jul 15, 2005 |
|
|
|
11459475 |
Jul 24, 2006 |
|
|
|
Current U.S.
Class: |
714/763 ;
714/E11.05 |
Current CPC
Class: |
G11C 29/42 20130101;
G11C 7/1006 20130101; G06F 11/1052 20130101; G11C 2207/104
20130101 |
Class at
Publication: |
714/763 |
International
Class: |
G11C 29/00 20060101
G11C029/00 |
Claims
1. A semiconductor memory device comprising; a plurality of
semiconductor memory cells including at least one memory cell
capable of operating in a first mode, in which the at least one
memory cell functions as a storage device for Error Correction Code
information, and in a second mode, in which the at least one memory
cell functions as a storage device for information being different
from Error Correction Code information; and a signal control device
operable to signal that the at least one memory cell is to operate
in the first mode or in the second mode.
2. The semiconductor memory device of claim 1, wherein in said
second mode the at least one memory cell functions as a redundant
memory cell.
3. The semiconductor memory device of claim 1, wherein in said
second mode the at least one memory cell functions as a memory cell
for storing ordinary information.
4. The semiconductor memory device of claim 1, wherein the
semiconductor memory device is a semiconductor memory component
comprising the signal control device.
5. The semiconductor memory device of claim 1 further comprising a
plurality of semiconductor memory components.
6. The semiconductor memory device of claim 5, wherein the signal
control device is common to each of the semiconductor memory
components.
7. The semiconductor memory device of claim 1, wherein the signal
control device is a fuse.
8. The semiconductor memory device of claim 1, wherein the signal
control device is a reprogrammable signal control device.
9. The semiconductor memory device of claim 1, wherein a status of
the signal control device can be determined by a technical
device.
10. The semiconductor memory device of claim 2 further comprising a
redundancy device operable to replace a defective memory cell when
the at least one memory cell operates in the second mode as a
redundant memory cell.
11. A method of operating the semiconductor memory device of claim
1, the method comprising the steps of: registering a status of the
signal control device and, depending on the status of the signal
device, either operating the at least one memory cell in the first
mode, in which it acts as a storage device for ECC information, or
operating the at least one memory cell in the second mode.
12. A semiconductor memory device comprising; a plurality of
semiconductor memory cells including at least one memory cell
capable of operating in a first mode, in which the at least one
memory cell functions as a storage device for Error Correction Code
information, and in a second mode, in which the at least one memory
cell functions as either as a redundant memory cell or as a memory
cell for storing ordinary information; and a signal control device
operable to signal that the at least one memory cell is to operate
in the first mode or in the second mode.
13. The semiconductor memory device of claim 1, wherein, in the
second mode, the at least one memory cell functions as a redundant
memory cell.
14. The semiconductor memory device of claim 1, wherein, in the
second mode, the at least one memory cell functions as a memory
cell for storing ordinary information.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority under 35 U.S.C. .sctn. 120
to U.S. patent application Ser. No. 11/182,063 filed 15 Jul. 2005
and entitled "Semiconductor Memory Device and Method of Operating
the Same", the disclosure of which is hereby incorporated by
reference in its entirety
FIELD OF THE INVENTION
[0002] The invention relates to a semiconductor memory device and
to a method of operating a semiconductor memory device.
BACKGROUND
[0003] Most memory components (e.g., integrated circuits such as
DRAMs) are generally fabricated with 1 bit-, 4 bit-, or 8 bit-wide
input/output lines. In any of these configurations, the components
cannot operate as memories having an error correction code (ECC).
There are, however, memory components fabricated with 5 bit- or 9
bit-wide input/output lines. These components operate as memories
having an ECC, with the 5.sup.th (or the 9.sup.th) line used as an
ECC line.
[0004] Memory modules (e.g., DIMMs (Dual Inline Memory Modules) or
SIMMs (Single Inline Memory Modules)) comprise, among other
components, a plurality of memory components. These memory modules
may include memory components equipped with only 1 bit-, 4 bit-, or
8 bit-wide input/output lines; consequently, no ECC mode can be run
on the memory module. To provide an ECC function, an extra memory
component is provided that operates exclusively as an ECC,
cooperating with memory components comprising 1 bit-, 4 bit-, or 8
bit-wide input/output lines. Alternatively, memory modules may
include memory components equipped with 5 bit- or 9 bit-wide
input/output lines. In this case, ECC operation is available with
each of the memory components.
[0005] The use of such memory components is
exclusive--semiconductor memory components or semiconductor memory
modules equipped with ECC capability can only be used in an ECC
computer system and not in a computer system lacking ECC
functionality. Conversely, individual memory components or modules
not equipped with an ECC capability can only be used in systems
having no ECC functionality (i.e., they cannot be used in
ECC-capable systems).
SUMMARY AND OBJECTS OF INVENTION
[0006] Accordingly, it is an object of the present invention to
provide a semiconductor memory device configured to operate within
both an ECC computer system and a computer system not having ECC
capability.
[0007] It is a further object of the present invention to provide a
method for operating a semiconductor memory device having multiple
operational modes including an ECC mode.
[0008] The aforementioned objects may be achieved individually
and/or in combination, and it is not intended that the present
invention be construed as requiring two or more of the objects to
be combined unless expressly required by the claims attached
hereto.
[0009] According to the present invention, a semiconductor memory
device including a plurality of semiconductor memory cells is
provided. The semiconductor memory cells include at least one
memory cell configured to selectively operate in either a first
mode or in a second mode. In the first mode, the memory cell
functions as a storing device for ECC information. In the second
mode, the at least one memory cell may either function as a
redundant memory cell or may function as a memory cell for storing
ordinary information. The semiconductor memory device may further
include a controller (also called a signal control device) for
signaling if the at least one memory cell is to operate in the
first mode or in the second mode. In a first embodiment, the
semiconductor memory device is a semiconductor memory component
(e.g., an integrated circuit) comprising the signal control device.
In a second embodiment, the semiconductor memory device may include
a plurality of semiconductor memory components and the signal
control device. The signal control device may be common to each of
the semiconductor memory components of the semiconductor memory
device. By way of example, the signal control device may be a fuse
(e.g., a laser-fuse or an electronic fuse). The signal control
device, moreover, may be reprogrammable. An electronic or optical
read-back device may be provided to determine the status of the
signal control device. The semiconductor memory device may further
include a redundancy device adapted to replace defective memory
cells by redundant memory cells being part of the at least one
memory cell.
[0010] Further provided is a method of operating a semiconductor
memory device having a plurality of semiconductor memory cells
including at least one memory cell capable of operating in a first
mode or in a second mode. The method includes the steps of
registering the status of a signal control device and, depending on
the status registered, either operating the at least one memory
cell in the first mode such that it stores or reads ECC information
therein, or operating the at least one memory cell in the second
mode, acting either as a redundant memory cell or as a memory cell
storing ordinary information.
[0011] The above and further objects, features, and advantages of
the present invention will become apparent upon consideration of
the following detailed description of specific embodiments thereof,
particularly when taken in conjunction with the accompanying
drawings, wherein like reference numerals in the various figures
are utilized to designate like components.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 illustrates a top plan view of a semiconductor memory
device according to an embodiment of the invention, showing a
plurality of memory cells and a signal control device.
[0013] FIG. 2 illustrates a top plan view of a semiconductor memory
device according to another embodiment of the invention, showing a
plurality of semiconductor memory components in communication with
a signal control device.
[0014] FIG. 3 illustrates a top plan view of a semiconductor memory
device according to another embodiment of the invention, showing a
plurality of memory cells and a signal control device.
DETAILED DESCRIPTION
[0015] FIG. 1 shows a semiconductor memory device MM comprising a
plurality of memory cells MC (for clarity, only three of the memory
cells MC are shown). The type of memory cells MC includes, but is
not limited to, DRAM memory cells arranged in a matrix. In this
embodiment, the semiconductor memory device MM is a component type
device, e.g., an individual integrated circuit. At least one of the
plurality memory cells MC is a dual mode memory cell--it is adapted
to operate in either a first mode, in which it capable of storing
and/or reading Error Correction Code (ECC) information, or in a
second mode, in which it functions as a either redundant memory
cell, replacing defective memory cells (and, in particular,
individual memory cells that are defective), or as a memory cell
for storing ordinary information. In operation, each mode is
exclusive of the other--the memory cells MC do not function in both
modes concurrently. So, in an operating status, the at least one
memory cell MC can either (1) be operated as a memory cell that
either (1) stores and/or reads ECC information or (2) be operated
to (a) replace defective memory cells out of the number of
remaining memory cells MC (especially individual defective memory
cells MC) or (b) to store ordinary information.
[0016] In the embodiment of FIG. 1, the at least one memory cell MC
is configured to function as a redundant memory cell. As shown, the
semiconductor memory device MM includes a 0 MB tag, a 256 MB tag,
and a 288 MB tag. These tags represent, just as an example,
boundaries of memory field areas within a 256 MB DRAM. Each of the
memory field areas comprises a plurality of memory cells MC. In the
illustrated embodiment, 0 MB represents the beginning of a first
memory field area of the DRAM. The tag 256 MB represents the edge
between a memory field area including only single-mode memory cells
MC (i.e., the field does not include the dual mode memory cell) and
a memory field area 1 including the dual mode memory cell (i.e.,
the at least one memory cell capable of operating in either the
first or second functional mode). The 288 MB tag represents the
other edge of the memory field area 1 including the dual mode
memory cells. Consequently, the at least one memory cell MC may
include a plurality of cells MC, capable of operating in either the
first or second functional mode, wherein the plurality is
completely contained within the separate memory field area 1.
[0017] Additionally, the first embodiment (integrated circuit
component) of the semiconductor memory device includes a signal
control device CTRL for signaling in which mode (ECC operation or
redundant memory cell operation) the dual mode memory cell MC of a
particular semiconductor memory device MM can be operated. As
illustrated, the signal control device CTRL is arranged outside of
the memory field areas. The signal control device CTRL may include,
but is not limited to, a fuse (a laser fuse or an electronic fuse
such as a Mode-Control Register Set). With this configuration, if
the semiconductor memory device MM is to operate the dual mode
memory cell MC in the ECC mode, the fuse may remain intact (i.e.,
it may not "blow the fuse"). A conventional controller involved
with operating semiconductor memories may read back the status of
the signal control device CTRL ("not blown" in this example) and,
according to the status it reads, will operate the semiconductor
memory device MM as a memory including, among other memory cells
MC, memory cells MC intended for usage in connection with the ECC
mode. However, if the fuse is not intact (i.e., if the fuse is
blown), the controller may read back the status of the signal
control device CTRL as "blown" and, accordingly, operate the dual
mode memory cell MC as a redundant memory cell.
[0018] The signal control device CTRL may further include a
reprogrammable device. This enables the status of the device (e.g.,
"blown" and "not blown") to be changed several times. The signal
control device CTRL may also be integrated into a Mode-Control
Register Set. The status of such a Register Set can be changed, as
well known, at least within every power-up procedure.
[0019] FIG. 2 shows a semiconductor memory device MM according to a
second embodiment of the invention. This embodiment may be of more
interest for the industry than the first embodiment just described
because, with this second embodiment, the semiconductor memory
device MM is represented by a memory board such as a DIMM or SIMM
board. In other words, the semiconductor memory device MM of the
second embodiment includes a plurality of individual memory
components Comp.
[0020] Each of the plurality of memory components Comp comprises
memory cells MC arranged in a matrix (for clarity, only a few cells
are illustrated in FIG. 2). Similar to the first embodiment, the
memory cells MC include at least one dual mode memory cell
MC--i.e., a memory cell capable of operating either in a first
mode, in which it functions as a storage device for ECC
information, or in a second mode. For the purposes of clarity, in
the embodiment of FIG. 2, it is assumed that in the second mode,
the at least one dual mode memory cell MC operates as a redundant
memory cell. However, this second mode may be, in a further,
different embodiment, operable to store ordinary data in the at
least one dual mode memory cell MC (as described below). When the
second mode of the memory components Comp operates as redundant
memory cell, the memory components Comp of the second embodiment
are similar to the semiconductor memory device MM of the first
embodiment with respect to the functional arrangement and to the
operational capability of the memory cells MC.
[0021] A single signal control device CTRL is also provided in the
semiconductor memory device MM. This single signal control device
CTRL may be arranged with any of the memory components Comp of the
second embodiment; however, is preferable to arrange the single
signal control device CTRL separately on the DIMM or SIMM board or,
generally, on the semiconductor memory device MM. The signal
control device CTRL may comprise devices similar to those described
above (e.g., a fuse, a reprogrammable device, etc).
[0022] As in the above-described embodiment, the controller that
controls the semiconductor memory device MM and the memory
components Comp may be operable to read back the status of the
signal control device CTRL (e.g., "blown" or "not blown") and, as a
result of the status read, the dual mode memory cells MC are
operated accordingly. With this configuration, the semiconductor
memory device MM is controlled to either operate as a memory device
comprising memory cells MC functioning in an ECC mode (the first
mode) or as a memory device comprising memory cells MC functioning
in the second mode, which may be a redundant memory cell mode, if
redundancy is required, or which may be an ordinary information
storing mode (discussed in greater detail below).
[0023] Preferably, a respective memory component Comp, i.e., either
an individual memory component Comp like that of the first
embodiment or a plurality of components Comp as disclosed in the
second embodiment, may further include a redundancy device such as
a redundancy decoder, a fuse etc. (which are generally known) to
enable full operation of the memory cells MC as redundant memory
cells.
[0024] FIG. 3 shows yet another semiconductor memory device MM
including a plurality of memory cells MC (for clarity, only three
of the memory cells MC are shown). The type of memory cells MC
includes, but is not limited to, DRAM memory cells arranged in a
matrix. Similar to the embodiment of FIG. 1, the semiconductor
memory device MM may be a component type device, e.g., an
individual integrated circuit. At least one of the plurality memory
cells MC may be a dual mode memory cell adapted to operate in
either a first mode (in which it is capable of storing and/or
reading Error Correction Code (ECC) information), or in a second
mode.
[0025] In this embodiment, the at least one memory cell MC, in its
second mode, now functions as a memory cell for storing ordinary
information. In other words: in the embodiment of FIG. 3, the at
least one memory cell MC functions, when being operated in the
second mode, in the same way as the other memory cells MC of the
semiconductor memory device MM function, which are not capable of
being operated in two different modes (i.e., they are single-mode
memory cells). In operation, each mode is exclusive of the
other--the at least one memory cell MC does not function in both
modes concurrently. So the at least one memory cell MC can either
be operated as a memory cell storing ECC information or it can be
operated as a memory cell storing ordinary information.
[0026] As shown in FIG. 3, the semiconductor memory device MM may
include a 0 MB tag, a 244 MB tag, and a 256 MB tag. These tags
represent, for example, boundaries of memory field areas within a
256 MB DRAM. Each of the memory field areas includes a plurality of
memory cells MC. In the illustrated embodiment, 0 MB represents the
beginning of a first memory field area of the DRAM. The tag 244 MB
represents the edge between a memory field area including only
single-mode memory cells (i.e., the field does not include any of
the dual mode memory cells) and a memory field area 1 including the
at least one dual mode memory cells MC (i.e., the at least one
memory cell MC capable of operating in either the first or second
functional mode). The 256 MB tag represents the other edge of the
memory field area 1 including the dual mode memory cells.
Consequently, as illustrated in FIG. 3, the at least one memory
cell MC capable of operating in either the first or second
functional mode are completely contained within a separate memory
field area 1.
[0027] In addition, this embodiment of the semiconductor memory
device (the integrated circuit component embodiment) includes,
similar to the embodiment of FIG. 1, a signal control device CTRL
for signaling in which mode (ECC operation or operation of storing
ordinary information) the dual mode memory cell MC of a particular
semiconductor memory device MM can be operated. As illustrated, the
signal control device CTRL is arranged outside of the memory field
areas. Also with this embodiment, the signal control device CTRL
may include, but is not limited to, a fuse (a laser fuse or an
electronic fuse such as a Mode-Control Register Set). With this
configuration, if the semiconductor memory device MM is to operate
the dual mode memory cell MC in the ECC mode, the fuse may remain
intact (i.e., it may not "blow the fuse"). A conventional
controller involved with operating semiconductor memories may read
back the status of the signal control device CTRL ("not blown" in
this example) and, according to the status it reads, will operate
the semiconductor memory device MM as a memory comprising, among
other memory cells MC, memory cells MC intended for usage in
connection with the ECC mode. However, if the fuse is not intact
(i.e., if the fuse is blown), the controller may read back the
status of the signal control device CTRL as "blown" and,
accordingly, operate the dual mode memory cell MC as a memory cell
storing ordinary information.
[0028] The signal control device CTRL may further include a
reprogrammable device. This enables the status of the device (e.g.,
"blown" and "not blown") to be changed several times. The signal
control device CTRL may also be integrated into a Mode-Control
Register Set. The status of such a Register Set can be changed, as
well known, at least within every power-up procedure.
[0029] In another embodiment of the invention, an arrangement
similar to the embodiment of FIG. 2 may be provided wherein the at
least one memory cell MC functions in the second mode as a storage
device for storing ordinary information.
[0030] According to the invention, the following method of
operating a semiconductor memory device MM is advantageous,
provided that there is available a semiconductor memory device MM
including a plurality of semiconductor memory cells MC, and that
the plurality of semiconductor memory cells MC includes at least
one memory cell MC adapted to operate in either a first mode, in
which it is capable of storing and/or reading Error Correction Code
(ECC) information, or in a second mode, in which is adapted to
selectively function as either a redundant memory cell, replacing
defective memory cells (and, in particular, individual memory cells
that are defective), or as a storage device for storing ordinary
information. In operation, the status of a signal control device
CTRL is registered (or read back). Once registered, the at least
one memory cell MC capable of operating in the first or second mode
is operated to either function in the first mode (i.e., as storage
device for ECC information) or in the second mode (i.e., either as
a redundant cell or as a storage device for storing ordinary
information).
[0031] A semiconductor memory device according to the present
invention provides several advantages. For example, it is possible
(depending on the status of the signal control device CTRL) to use
such a semiconductor memory device not only in a system equipped
with ECC operation, but also in a system without the ECC operation
capability. In the latter case, moreover, it is possible to use the
at least one memory cell MC as redundancy memory cells, or to use
it as a storage device for storing ordinary information. These
varying usages are achieved by the fact that the number of
connection pins of the semiconductor memory device is always the
same, whether or not the device is used within an ECC system. In
contrast, in semiconductor memory devices of the prior art adapted
for usage within an ECC system, the number of connection pins is
always different from the number of connection pins of a
semiconductor memory device not adapted for usage within an ECC
system.
[0032] Additionally, the cost of producing the semiconductor memory
device of the present invention is less that the cost of producing
the semiconductor memory devices of the prior art because when a
semiconductor memory device shows defective memory cells,
especially single defective memory cells (e.g., in the cell
field(s) outside the area of the dual mode memory cell), it is
possible to use the dual mode memory cells as redundant memory
cells in case that in the second mode the dual mode memory cells
function as redundant memory cells. Without this possibility of
replacing memory cells, the integrity of the semiconductor memory
device would diminish.
[0033] In the embodiment, where, in the second mode, the at least
one memory cell MC functions as a storing device for storing
ordinary information, the invention has the additional advantage
that the number of pins can also be kept the same regardless
whether the semiconductor memory device is operated in the first
mode or in the second mode. Again, the aspect of "cost of
production" applies since there is no need to produce different
types of memory devices depending on the purpose of their
application (ECC information or ordinary information). Different
types of memory devices reduce the number of memory devices needed
for the first mode of operation and also the number of memory
devices needed for the second mode of operation. Such a reduction
results in higher cost per memory device. However, producing a
respective larger number of memory devices capable of being
operated in both modes reduces the cost of production.
[0034] While the invention has been described in detail and with
reference to specific embodiments thereof, it will be apparent to
one skilled in the art that various changes and modifications can
be made therein without departing from the spirit and scope
thereof. Accordingly, it is intended that the present invention
covers the modifications and variations of this invention provided
they come within the scope of the appended claims and their
equivalents.
* * * * *