U.S. patent application number 11/492253 was filed with the patent office on 2007-02-08 for high permeability layered films to reduce noise in high speed interconnects.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Kie Y. Ahn, Salman Akram, Leonard Forbes.
Application Number | 20070029645 11/492253 |
Document ID | / |
Family ID | 28039535 |
Filed Date | 2007-02-08 |
United States Patent
Application |
20070029645 |
Kind Code |
A1 |
Forbes; Leonard ; et
al. |
February 8, 2007 |
High permeability layered films to reduce noise in high speed
interconnects
Abstract
An electronic system includes apparatus having a transmission
line circuit with an associated high permeability material. The
high permeability material may include a layered structure of a
nickel iron compound.
Inventors: |
Forbes; Leonard; (Corvallis,
OR) ; Ahn; Kie Y.; (Chappaqua, NY) ; Akram;
Salman; (Boise, ID) |
Correspondence
Address: |
Schwegman, Lundberg, Woessner & Kluth, P.A.;Attn: Edward J. Brooks, III
P.O. Box 2938
Minneapolis
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
28039535 |
Appl. No.: |
11/492253 |
Filed: |
July 25, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10930657 |
Aug 31, 2004 |
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11492253 |
Jul 25, 2006 |
|
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10099217 |
Mar 13, 2002 |
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10930657 |
Aug 31, 2004 |
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Current U.S.
Class: |
257/659 ;
257/662; 257/664; 257/758; 257/766; 257/E23.144; 257/E23.157 |
Current CPC
Class: |
H01L 2223/6627 20130101;
H01L 23/66 20130101; H01L 2924/00 20130101; H01L 23/53209 20130101;
H01L 2924/0002 20130101; H01L 2924/1903 20130101; H01L 23/5222
20130101; H01L 23/5225 20130101; G11C 5/063 20130101; H01L
2924/3011 20130101; H01L 2924/0002 20130101 |
Class at
Publication: |
257/659 ;
257/766; 257/758; 257/664; 257/662 |
International
Class: |
H01L 23/552 20060101
H01L023/552; H01L 23/48 20060101 H01L023/48; H01L 23/52 20060101
H01L023/52; H01L 29/40 20060101 H01L029/40; H01L 39/00 20060101
H01L039/00 |
Claims
1. An electronic system comprising: a processor; and an integrated
circuit coupled to the processor, the integrated circuit including:
a layer of insulating material disposed above a substrate; a number
of transmission lines on the layer of insulating material; and a
number of shielding lines on the layer of insulating material, the
transmission lines interposed between and parallel with the
shielding lines, wherein at least one of the transmission lines, at
least one of the shielding lines, or at least one of both the
transmission lines and the shielding lines include a layered film
of a high permeability material.
2. The electronic system of claim 1, wherein the layered film of
the high permeability material includes a layered film having a
layer of a nickel iron compound and a layer of an electrically
conductive material, the layers of the nickel iron compound and the
electrically conductive material arranged as alternating
layers.
3. The electronic system of claim 1, wherein the layered film of
the high permeability material includes a layered film having a
layer of a nickel iron compound, a layer of an electrically
conductive material, and a layer of another nickel iron compound,
the layers of the nickel iron compounds and the electrically
conductive material arranged as alternating layers.
4. The electronic system of claim 1, wherein the layered film of
the high permeability material includes permalloy and
Ni.sub.45Fe.sub.55.
5. The electronic system of claim 1, wherein a conductive plane is
disposed on a dielectric layer, the dielectric disposed on the
transmission lines and the shielding lines above the layer of
insulating material such that the transmission lines and the
shielding lines are situated between the conductive plane and the
substrate.
6. The electronic system of claim 5, wherein the insulating
material and the dielectric layer have a common composition.
7. The electronic system of claim 1, wherein a conductive plane is
disposed between the substrate and the layer of insulating
material.
8. The electronic system of claim 1, wherein each transmission line
has a width that is greater than a thickness of the transmission
line.
9. The electronic system of claim 1, wherein the transmission lines
include the layered film of the high permeability material.
10. The electronic system of claim 8, wherein the layered film of
the high permeability material includes permalloy and
Ni.sub.45Fe.sub.55.
11. The electronic system of claim 1, wherein the shielding lines
include the layered film of the high permeability material.
12. The electronic system of claim 10, wherein the layered film of
the high permeability material includes permalloy and
Ni.sub.45Fe.sub.55.
13. The electronic system of claim 1, wherein the integrated
circuit includes a driver circuit coupled to at least one of the
transmission lines, the at least one transmission line coupled to a
termination circuit, the at least one transmission line having an
impedance and the termination having a termination impedance such
that the impedance of the transmission line is matched to the
termination impedance.
14. An electronic system comprising: a processor; and an integrated
circuit coupled to the processor, the integrated circuit including:
a first conductive plane on a substrate; a first layer of
insulating material disposed above the substrate and on the first
conductive plane; a number of shielding lines on the first layer of
insulating material, wherein the shielding lines include a layered
film of a high permeability material; a number of transmission
lines on the first layer of insulating material, the transmission
lines interposed between and parallel with the shielding lines; a
second layer of insulating material on the number of transmission
lines and the number of shielding lines; and a second conductive
plane on the second layer of insulating material.
15. The electronic system of claim 14, wherein the layered film of
the high permeability material includes a layered film having
layers of the high permeability material and layers of an
electrically conductive material such that a set of the layers of
the high permeability material and the electrically conductive
material are disposed substantially perpendicular with a surface of
the first conductive plane and another set of the layers of the
high permeability material and the electrically conductive material
are disposed substantially perpendicular with a surface of the
first conductive plane.
16. The electronic system of claim 15, wherein the shielding lines
are coupled to ground.
17. The electronic system of claim 14, wherein the layered film of
the high permeability material includes a layered film having a
layer of the high permeability material and a layer of an
electrically conductive material.
18. The electronic system of claim 17, wherein the layers of the
high permeability material and the electrically conductive material
are disposed substantially parallel with a surface of the first
conductive plane.
19. The electronic system of claim 17, wherein the layers of the
high permeability material and the electrically conductive material
are disposed substantially perpendicular with a surface of the
first conductive plane.
20. The electronic system of claim 17, wherein the second
conductive plane includes a layered structure having a layer of a
second high permeability material and a layer of a second
electrically conductive material.
21. The electronic system of claim 20, wherein the layered
structure is disposed on and contacting the second layer of
insulating material.
22. The electronic system of claim 20, wherein the second
conductive plane includes a ground plane separated from the second
layer of insulating material by the layered structure.
23. The electronic system of claim 20, wherein the layered
structure includes a layer of the second high permeability material
separated from a layer of a third high permeability material by the
layer of the second electrically conductive material.
24. The electronic system of claim 23, wherein the second high
permeability material includes permalloy and the third high
permeability material includes Ni.sub.45Fe.sub.55.
25. The electronic system of claim 17, wherein the first conductive
plane includes a first layered structure having a layer of a second
high permeability material and a layer of a second electrically
conductive material and the second conductive plane includes a
second layered structure having a layer of a third high
permeability material and a layer of a third electrically
conductive material.
26. The electronic system of claim 25, wherein the first layered
structure is disposed in contact with the first layer of insulating
material and the second layered structure is disposed in contact
with the second layer of insulating material.
27. The electronic system of claim 25, wherein the first layered
structure includes the layer of the second high permeability
material separated from a layer of a fourth high permeability
material by the layer of the second electrically conductive
material and the second layered structure includes the layer of the
third high permeability material separated from a layer of a fifth
high permeability material by the layer of the third electrically
conductive material.
28. The electronic system of claim 27, wherein the second and third
high permeability materials each includes permalloy and the fourth
and fifth high permeability materials each includes
Ni.sub.45Fe.sub.55.
29. The electronic system of claim 14, wherein the integrated
circuit is a memory.
30. An electronic system comprising: a processor; and an integrated
circuit coupled to the processor, the integrated circuit including:
a first conductive plane on a substrate; a first layer of
insulating material disposed above the substrate and on the first
conductive plane; a number of shielding lines on the first layer of
insulating material; a number of transmission lines on the first
layer of insulating material, the transmission lines interposed
between and parallel with the shielding lines, wherein the
transmission lines include a layered film of a high permeability
material; a second layer of insulating material on the number of
transmission lines and the number of shielding lines; and a second
conductive plane on the second layer of insulating material.
31. The electronic system of claim 30, wherein the layered film of
the high permeability material includes a layered film having
layers of the high permeability material and layers of an
electrically conductive material such that a set of layers of the
high permeability material and the electrically conductive material
are disposed substantially perpendicular with a surface of the
first conductive plane and another set of layers of the high
permeability material and the electrically conductive material are
disposed substantially perpendicular with a surface of the first
conductive plane.
32. The electronic system of claim 31, wherein the shielding lines
are electrically conductive lines coupled to ground.
33. The electronic system of claim 30, wherein the layered film of
the transmission lines includes a layer of the high permeability
material and a layer of the electrically conductive material, and
the shielding lines include a second layered film having a layer of
a second high permeability material and a layer of a second
electrically conductive material.
34. The electronic system of claim 33, wherein the second layered
film includes a layered film having layers of the second high
permeability material and layers of the second electrically
conductive material such that a set of the layers of the second
high permeability material and the second electrically conductive
material are disposed substantially perpendicular with a surface of
the first conductive plane and another set of the layers of the
second high permeability material and the second electrically
conductive material are disposed substantially perpendicular with
the surface of the first conductive plane.
35. The electronic system of claim 33, wherein the layers of the
second high permeability material and the second electrically
conductive material of the shielding lines are disposed
substantially perpendicular with a surface of the first conductive
plane.
36. The electronic system of claim 35, wherein the layers of the
high permeability material and the electrically conductive material
of the transmission lines disposed substantially parallel with the
surface of the first conductive plane.
37. The electronic system of claim 30, wherein the layered film of
the transmission lines includes a layer of the high permeability
material and a layer of the electrically conductive material, and
the second conductive plane includes a layered structure having a
layer of a second high permeability material and a layer of a
second electrically conductive material.
38. The electronic system of claim 37, wherein the layered
structure is disposed on and contacting the second layer of
insulating material.
39. The electronic system of claim 37, wherein the second
conductive plane includes a ground plane separated from the second
layer of insulating material by the layered structure.
40. The electronic system of claim 37, wherein the layered
structure includes a layer of the second high permeability material
separated from a layer of a third high permeability material by the
layer of the second electrically conductive material.
41. The electronic system of claim 30, wherein the second high
permeability material includes permalloy and the third high
permeability material includes Ni.sub.45Fe.sub.55.
42. The electronic system of claim 30, wherein the first conductive
plane includes a first layered structure having a layer of a second
high permeability material and a layer of a second electrically
conductive material and the second conductive plane includes a
second layered structure having a layer of a third high
permeability material and a layer of a third electrically
conductive material.
43. The electronic system of claim 42, wherein the first layered
structure is disposed in contact with the first layer of insulating
material and the second layered structure is disposed in contact
with the second layer of insulating material.
44. The electronic system of claim 42, wherein the first layered
structure includes the layer of the second high permeability
material separated from a layer of a fourth high permeability
material by the layer of the second electrically conductive
material and the second layered structure includes the layer of the
third high permeability material separated from a layer of a fifth
high permeability material by the layer of the third electrically
conductive material.
45. The electronic system of claim 44, wherein the second and third
high permeability materials each includes permalloy and the fourth
and fifth high permeability materials each includes
Ni.sub.45Fe.sub.55.
46. The electronic system of claim 44, wherein the first conductive
plane includes a ground plane separated from the first layer of
insulating material by the first layered structure.
47. The electronic system of claim 30, wherein the integrated
circuit is a memory.
48. An electronic system comprising: a processor; and an integrated
circuit coupled to the processor, the integrated circuit including:
a layer of insulating material disposed above a substrate; a number
of transmission lines on the layer of insulating material; and a
number of shielding lines on the layer of insulating material, the
shielding lines being electrically conductive lines, the
transmission lines interposed between and parallel with the
shielding lines, wherein at least one of the transmission lines and
the conductive lines includes a layered film of a high permeability
material, the layered film of a high permeability material being a
layered film a first nickel iron compound and a second nickel iron
compound.
49. The electronic system of claim 48, wherein the first nickel
iron compound is permalloy and the second nickel iron compound is
Ni.sub.45Fe.sub.55.
50. The electronic system of claim 48, wherein a conductive plane
is disposed on the layer of insulating material such that the
transmission lines and the conductive lines are situated between
the conductive plane and the substrate.
51. The electronic system of claim 48, wherein a conductive plane
is disposed between the substrate and the layer of insulating
material.
52. The electronic system of claim 48, wherein the transmission
lines include the layered film of the first nickel iron compound
and the second nickel iron compound.
53. The electronic system of claim 52, wherein the first nickel
iron compound is permalloy and the second nickel iron compound is
Ni.sub.45Fe.sub.55.
54. The electronic system of claim 48, wherein the conductive lines
include the layered film of the first nickel iron compound and the
second nickel iron compound.
55. The electronic system of claim 54, wherein the first nickel
iron compound is permalloy and the second nickel iron compound is
Ni.sub.45Fe.sub.55.
56. The electronic system of claim 48, wherein the integrated
circuit is a memory.
57. An electronic system comprising: a processor; and an integrated
circuit coupled to the processor, the integrated circuit including:
a first layer of insulating material above a substrate; a number of
shielding lines on the first layer of insulating material, the
shielding lines being electrically conductive lines; a number of
transmission lines on the first layer of insulating material, the
number of transmission lines spaced between and parallel with the
number of electrically conductive lines, wherein the number of
transmission lines include a layered film of a high permeability
material, the layered film of a high permeability material being a
layered permalloy and Ni.sub.45Fe.sub.55 film; and a second layer
of insulating material on the number of transmission lines and the
number of shielding lines.
58. The electronic system of claim 57, wherein the first layer of
insulating material is formed on a first conductive plane.
59. The electronic system of claim 58, wherein the system includes
a second conductive plane formed on the second layer of insulating
material.
60. The electronic system of claim 59, wherein the first and the
second conductive planes have a thickness of approximately 3 to 5
micrometers (.mu.m).
61. The electronic system of claim 59, wherein the second
conductive plane is coupled to a power supply.
62. The electronic system of claim 57, wherein the substrate
includes an insulator material.
63. The electronic system of claim 57, wherein the number of
shielding lines include a layered permalloy and Ni.sub.45Fe.sub.55
film.
64. The electronic system of claim 63, wherein the number of
transmission lines having a layered permalloy and
Ni.sub.45Fe.sub.55 film includes a layered permalloy and
Ni.sub.45Fe.sub.55 film on at least two sides of the number of
transmission lines, the two sides being on opposing surfaces and at
least one of the two side being adjacent to the substrate.
65. The electronic system of claim 57, wherein the integrated
circuit is a memory.
66. The electronic system of claim 65, wherein the memory is a
Dynamic Random Access Memory (DRAM).
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a Divisional of U.S. Ser. No.
10/930,657, filed Aug. 31, 2004, which is a Divisional of U.S. Ser.
No. 10/099,217 filed on Mar. 13, 2002, which applications are
herein incorporated by reference.
FIELD OF THE INVENTION
[0002] The present invention relates generally to integrated
circuits. More particularly, it pertains to structure and methods
for improved transmission line interconnections.
BACKGROUND OF THE INVENTION
[0003] The metal lines over insulators and ground planes, or metal
lines buried in close proximity to dielectric insulators and used
for integrated circuit interconnects are in reality transmission
lines or strip lines. The use of coaxial interconnection lines for
interconnections through the substrate in CMOS integrated circuits
can also be termed transmission lines or strip lines.
Interconnection lines on interposers or printed circuit boards can
also be described as transmission lines.
[0004] The low characteristic impedance of any of these lines,
transmission, strip lines or coaxial lines results in part from the
low characteristic impedance of free space,
Zo=(.mu..sub.o/.epsilon..sub.o).sup.1/2=377 ohms, and in part from
the dielectric material used for electrical insulation in the lines
which has a higher dielectric permittivity than free space. Most
commonly used coaxial lines have an impedance of 50 ohms or 75
ohms, it is difficult to achieve larger values. In the past these
effects have not received much consideration on the integrated
circuits themselves since the propagation speed with oxide
insulators is 15 cm/ns and switching speeds on integrated circuits
of the size of a centimeter have been slower than 1/15 ns or 70
picoseconds. Transmission line effects only become important if the
switching time is of the same order as the signal propagation time.
Switching times in CMOS circuits have been limited by the ability
to switch the capacitive loads of long lines and buffers, and
charge these capacitances over large voltage swings to yield a
voltage step signal.
[0005] Most current CMOS integrated circuit interconnections rely
on the transmission of a voltage step or signal from one location
to another. FIG. 1 illustrates R-C limited, short high impedance
interconnections with capacitive loads. The driver may simply be a
CMOS inverter as shown in FIG. 1 and the receiver a simple CMOS
amplifier, differential amplifier, or comparator.
[0006] As shown in FIG. 1, the CMOS receiver presents a high
impedance termination or load to the interconnection line. This is
problematic in that:
[0007] (i) the switching time response or signal delay is
determined mainly by the ability of the driver to charge up the
capacitance of the line and the load capacitance,
[0008] (ii) the line is not terminated by its characteristic
impedance resulting in reflections and ringing,
[0009] (iii) large noise voltages may be induced on the signal
transmission line due to capacitive coupling and large voltage
swing switching on adjacent lines, the noise voltage can be a large
fraction of the signal voltage.
[0010] The transmission of voltage step signals only works well if
the interconnection line is short so that the stray capacitance of
the line is small. Long lines result is slow switching speeds and
excessive noise due to capacitive coupling between lines.
[0011] FIG. 1 shows the commonly used signal interconnection in
CMOS integrated circuits, where voltage signals are transmitted
from one location to another. This is problematic in that the
interconnection lines are normally loaded with the capacitive input
of the next CMOS stage and the large stray capacitance of the line
itself. The response time is normally slow due to the limited
ability of the line drivers to supply the large currents needed to
charge these capacitances over large voltage swings. These times
are usually much larger than the signal transmission time down the
line so a lumped circuit model can be used to find the signal
delay, as shown in FIG. 1.
[0012] In the example here the output impedance of the source
follower is 1 /gm=1000 ohms, and a line 0.1 cm long will have a
capacitance of about 0.2 pF if the dimensions of the line are about
1 micron by 1 micron and the insulator or oxide thickness under the
line is 1 micron. This results in a time constant of 200 pS and it
takes about 400 pS to charge the line from 10% to 90% of the final
voltage value. This is a relatively slow response.
[0013] Furthermore, if two interconnection wires are in close
proximity then the voltage swing on one line can induce a large
voltage swing or noise voltage on the adjacent line as shown in
FIG. 1. The noise voltage is just determined by the capacitance
ratios, or ratio of interwire capacitance, Cint, to the capacitance
of the interconnection wire, C.
[0014] In prior art these can be comparable, as shown, and depend
on the insulator thickness under the wires and the spacing between
the wires. Therefore, the noise voltage can be a large fraction of
the signal voltage if the wires are in close proximity and far
removed from the substrate by being over thick insulators. The
emphasis in prior art has always been in trying to minimize the
capacitance of the interconnection line, C, by using thick
insulators and low dielectric constant materials.
[0015] Thus, there is a need to provide a solution for these types
of problems for CMOS-scaled integrated circuits. Due to the
continued reduction in scaling and increases in frequency for
transmission lines in integrated circuits such solutions remain a
difficult hurdle. For these and other reasons there is a need to
reduce noise in high speed interconnections.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 shows the commonly used signal interconnection in
CMOS integrated circuits, where voltage signals are transmitted
from one location to another.
[0017] FIG. 2 illustrates one technique to minimize the interwire
capacitance, Cint, by using an intermediate line at ground for
shielding.
[0018] FIG. 3A illustrates signal transmission using correctly
terminated transmission lines and current sense amplifiers,
according to the teachings of the present invention.
[0019] FIG. 3B illustrates two interconnection lines in close
proximity and the interwire capacitance between these lines and the
mutual inductance coupling between the lines.
[0020] FIG. 4 is a perspective view illustrating a pair of
neighboring transmission lines above a conductive substrate,
according to the teachings of the present invention.
[0021] FIG. 5 is a schematic diagram for an interconnection on an
integrated circuit according to the teachings of the present
invention.
[0022] FIG. 6 illustrates one embodiment for a pair of neighboring
transmission lines, according to the teachings of the present
invention.
[0023] FIG. 7 illustrates another embodiment for a pair of
neighboring transmission lines, according to the teachings of the
present invention.
[0024] FIG. 8 illustrates another embodiment for a pair of
neighboring transmission lines, according to the teachings of the
present invention.
[0025] FIG. 9 illustrates another embodiment for a pair of
neighboring transmission lines, according to the teachings of the
present invention.
[0026] FIG. 10 illustrates another embodiment for a pair of
neighboring transmission lines, according to the teachings of the
present invention.
[0027] FIG. 11 illustrates another embodiment for a pair of
neighboring transmission lines, according to the teachings of the
present invention.
[0028] FIG. 12 illustrates another embodiment for a pair of
neighboring transmission lines, according to the teachings of the
present invention.
[0029] FIG. 13 is a block diagram which illustrates an embodiment
of a system using line signaling according to teachings of the
present invention.
[0030] FIG. 14 is a block diagram which illustrates another
embodiment of a system according to teaching of the present
invention.
DETAILED DESCRIPTION
[0031] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention.
[0032] The terms wafer and substrate used in the following
description include any structure having an exposed surface with
which to form the integrated circuit (IC) structure of the
invention. The term substrate is understood to include
semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other
layers that have been fabricated thereupon. Both wafer and
substrate include doped and undoped semiconductors, epitaxial
semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator is defined to include any
material that is less electrically conductive than the materials
referred to as conductors. The following detailed description is,
therefore, not to be taken in a limiting sense, and the scope of
the present invention is defined only by the appended claims, along
with the full scope of equivalents to which such claims are
entitled.
[0033] FIG. 2 illustrates one technique to minimize the interwire
capacitance, Cint, by using an intermediate line at ground for
shielding. This technique is disclosed in a co-pending application
by a common inventor, Dr. Leonard Forbes, entitled "Novel
Transmission Lines for CMOS Integrated Circuits," Ser. No.
09/364199. The same is incorporated herein by reference.
[0034] Also, as disclosed in issued U.S. Pat. No. 6,255,852 by Dr.
Leonard Forbes, entitled "Current Mode Interconnects on CMOS
Integrated Circuits," low impedance transmission lines such as
those which exist on CMOS integrated circuits are more amenable to
signal current interconnections over longer interconnection lines.
U.S. Pat. No. 6,255,852 is incorporated herein by reference. These
longer interconnection lines may be on the CMOS integrated circuit
itself, an interconnection line between integrated circuits mounted
in a module as for instance a memory module, an interposer upon
which these integrated circuits are mounted, or on a printed
circuit board upon which the integrated circuits are mounted. If
the line is terminated with a low input impedance current sense
amplifier then the line can be regarded as a transmission line
terminated with the characteristic impedance of the interconnection
line. This is advantageous in that:
[0035] (i) the signal delay depends only on the velocity of light
on the line and is easily predictable and reproducible, eliminating
or allowing for compensation for signal and/or clock skew,
[0036] (ii) there are no reflections at the receiving end of the
line and this minimizes ringing,
[0037] (iii) noise signals will be smaller due to weaker coupling
between lines resulting in better signal to noise ratios, the noise
current will only be a small fraction of the signal current. The
transmission of current signals rather than voltage signals is more
desirable at high speeds, and in high speed or high clock rate
circuits over longer interconnection lines. A CMOS circuit might
for instance use a combination of techniques, conventional voltage
signals over short interconnections with little coupling between
lines and current signals over longer interconnections and where
lines might be in close proximity.
[0038] FIG. 3A illustrates capacitive coupling between low
impedance terminated interconnection lines. FIG. 3A illustrates
signal transmission using correctly terminated transmission lines
and current sense amplifiers, such as those disclosed in issued
U.S. Pat. No. 6,255,852 by Dr. Leonard Forbes, entitled "Current
Mode Interconnects on CMOS Integrated Circuits." The signal
interconnection or transmission line is terminated by the matching
impedance of the current sense amplifier. This means the impedance
looking into the sending end of the transmission line will just be
the characteristic impedance of the line and the signal delay down
the line will just be the small propagation delay down the line.
The response time of the source follower being used as a line
driver will be determined primarily by the longer rise time of the
input voltage. This driver will supply a signal current whose rise
time is basically just that of the input voltage signal.
[0039] FIG. 3A also illustrates the coupling to another signal line
in close proximity, in this case the coupling will be both magnetic
through the induced magnetic fields and mutual inductance and
capacitive coupling. The noise current induced will be shown to be
only a fraction of the signal current or the signal to noise ratio
is high. Once received this signal current is converted back to a
signal voltage by the current sense amplifier at the receiving end
of the line. Since the signal propagation time is small, the signal
delay time will in practice be limited by the rise time of the
signal to the gate of the source follower. Since the gate
capacitance of the source follower is small this can be very
fast.
[0040] Other methods to minimize capacitive coupling between lines
use low dielectric constant materials or insulators, or ground
shields, such as shown in FIG. 2. In the present invention, it is
desirable to use very low impedance lines, it is also desirable to
keep the capacitive coupling between lines small and the magnitude
of voltage steps on the interconnection lines small. The current
step will induce a voltage step at the load which is the magnitude
of the load impedance times this current step. This voltage step
while small, 1 mA times Zin in this example, still can induce a
capacitively coupled noise signal on an adjacent line.
[0041] FIG. 3A shows an integrated circuit 300 in which a first
transmission line, strip line, or coaxial line 301A interconnects
circuit components, e.g. a driver 310 to a receiver 320. FIG. 3A
illustrates a first transmission line 301A over a conductive
substrate 305. Conventionally, a voltage signal (i.e. a 5 volt
signal swing) is provided by the driver 310 to the transmission
line 301A. The schematic illustrations in FIG. 3A demonstrate that
the transmission line 301A includes a small resistance, shown
generally by resistor symbols 302A, 302B, . . . , 302N. Also, the
transmission line 301A includes a distributed inductance (L) which
is represented generally by inductor symbols 303A, 303B, . . . ,
303N. In one embodiment, the driver 310 may be an inverter 310 and
the receiver 320 may be an amplifier 320. Capacitor plate symbols
304 (C) are used to schematically represent the capacitive coupling
which occurs between the transmission line 301A and the conducting
substrate 305. In FIG. 3A, a second transmission line 301B is
shown. Capacitor plate symbols 306 are used to schematically
represent the capacitive coupling (Cint) which similarly occurs
between the first transmission line 301A and neighboring
transmission lines, e.g. second transmission line 301B.
[0042] FIG. 3B illustrates two interconnection lines in close
proximity and the interwire capacitance between these lines and the
mutual inductance coupling between the lines. (See generally, H.
Johnson, "High-Speed Digital Circuits: A Handbook of Black Magic,"
Prentice-Hall, 1993; and S. Ramo, J. R. Whinnery and T. Van Duzer,
"Fields and Waves in Communication Electronics, 3rd Ed.," John
Wiley, New York, 1994). Although the interconnection lines on
integrated circuits might tend to be more square than round, the
concepts involved can be most conveniently described and formulas
approximated by assuming for simplicity that the lines are round or
circular. Approximate formulas have been developed describing round
wires over conductive planes or two wires in close proximity, in
this case they are interconnection wires on a CMOS integrated
circuit, interposer, or printed circuit board.
[0043] In FIG. 3B the illustrated pair of interconnect, or
transmission lines, 301A and 301B, displayed in a perspective view,
are separated from a conducting substrate 305. The transmission
lines, 301A and 301B are spaced a distance (h) from the conducting
substrate 305 and a distance (s) from one another. The transmission
lines, 301A and 301B, are shown in a circular geometry, each with a
diameter (a). Some general characterizations can be made about the
transmission lines, 301A and 301B, in an environment floating or
suspended in air. First, each transmission line, 301A and 301B,
will have a characteristic impedance in air (Z.sub.0) approximately
or generally given by Z.sub.0.apprxeq.60 ln (4h/a). Second, each
transmission line, 301A and 301B, has a inductance (L) which is
L.apprxeq.5.08.times.10.sup.-9.times.ln (4h/a) Henrys/inch
(H/inch). Additionally, the two transmission lines, 301A and 301B,
will exhibit an interwire mutual inductance (M) which is given by
M=L.times.{1/[1+(s/h).sup.2]}. Third, an interwire capacitive
coupling (Cint) exists between the two transmission lines, 301A and
301B, and is expressed as Cint=.pi..epsilon./cosh.sup.-1(s/a).
Using the trigonometric relationship of cosh.sup.-1(y)=ln(2y), the
interwire capacitive coupling can similarly be expressed as
Cint=.pi..epsilon./ln(2s/a). Thus, in this environment, the two
transmission lines, 301A and 301B, exhibit an interline capacitance
(Cint) given by Cint={0.7/[ln(2 s/a)]} pico Farads/inch (pF/inch).
Lastly, each transmission line, 301A and 301B, will further exhibit
capacitive coupling C with the conducting substrate 305.
[0044] Again, in FIG. 3B the transmission lines, 301A and 301B, are
spaced a distance (h) from the conducting substrate 305. Using the
method of images and the interwire capacitive relationship,
Cint=.pi..epsilon./ln(2 s/a), a single transmission line, 301A,
over a conducting substrate is given by C=2.pi..epsilon./ln(4h/a)
pF/inch where h=s/2. Thus, in this environment, the two
transmission lines, 301A and 301B, exhibit a capacitance, or
capacitive coupling C with the conductive substrate 305 which is
C={1.41/[ln(4h/a)]} pF/inch. The above equations have been
presented by assuming that the transmission lines have round or
circular geometries. Actual transmission lines on integrated
circuits might tend to be more square or rectangular than round due
to present lithography techniques. Nevertheless, due to the actual
physical size of transmission lines, determined according to
minimum lithographic feature techniques, the formulas scale well to
square, rectangular or other physical cross sectional geometries
for the transmission lines.
[0045] The signal rise time (trise) in conventional voltage
signaling is normally slow due to the limited ability of the
transmission line drivers to supply the large currents needed to
charge these capacitances over large voltage swings. The signal
rise times are usually much larger than the signal transmission
time down the line (tprop). Additionally, if two transmission lines
are in close proximity then the voltage swing on one transmission
line can induce a large voltage swing or noise voltage on the
adjacent transmission line. The noise voltage is determined by the
capacitance ratios of interwire capacitance, Cint, to the
capacitance of the transmission line with the substrate, C. In
other words, the noise voltage is determined according to the ratio
Cint/C, Cint/C=1/2[ln(4h/a)/ln(2s/a)].
[0046] The values of Cint and C can be comparable, dependant upon
the insulator thickness (h) under the transmission lines and the
spacing between the transmission lines. Emphasis in prior art is
placed upon minimizing the capacitance of the transmission line, C,
by using thick insulators and low dielectric constant materials.
Emphasis is also to some extent placed upon minimizing the
interwire capacitance, Cint. Thus, the approach in the prior art
results in a noise voltage which can be a large fraction of the
signal voltage if the transmission lines are in close proximity and
far removed from the substrate by being over thick insulators.
[0047] FIG. 4 is a perspective view illustrating a pair of
neighboring transmission lines, 401A and 401B, above a conductive
substrate 405 according to the teachings of the present invention.
The present invention is designed to use current signaling across
low impedance transmission lines, 401A and 401B, to reduce signal
transmission delay and to improve signaling performance over longer
transmission lines. Under conventional voltage signaling the
current provided in the transmission lines is too weak to provide
clean, accurately detectable current signal. In order to obtain
better current signals in the transmission lines the signal to
noise ratio of the transmission lines must be improved.
[0048] To improve the signal to noise ratio of the transmission
lines, 401A and 401B, the capacitance coupling between the
transmission lines, 401A and 401B, and the conductive substrate
405, is made large. The characteristic impedance (Zo) of the
transmission lines, 401A and 401 B, can be expressed as Z.sub.0=
{square root over (L/C)}. Thus, making C large makes the
characteristic impedance Zo=Zin, small and similarly makes the
voltage division ratio for capacitive coupling small. In the
present invention, C increases as the insulator 407 thickness (h)
separating the transmission lines, 401A and 401B, from the ground
plane, or substrate 405 is decreased. In FIG. 4, the transmission
lines, 401A and 401B, are separated a distance (h) from the
conducting substrate 405 by an insulating layer 407. In one
embodiment, the insulating layer 407 is an oxide layer 407. The
capacitive coupling C between the transmission lines, 401A and
401B, and the conducting substrate 405 separated by an oxide layer
407 is given as C.apprxeq.1.66/[ln(4h/a)] pF/cm. Additionally, the
inductance (L) for the transmission lines, 401A and 401B, over the
oxide layer 407 is L.apprxeq.2.times.ln(4h/a) nanoHenrys/centimeter
(nH/cm). The transmission lines, 401A and 401B, are shown in a
square geometry having a width (a). The insulator 407 has a
thickness (b) separating the transmission lines, 401A and 401B from
the substrate. 405. According to one embodiment of the present
invention, the insulator thickness (b) is made thinner than the
thickness (t) of the transmission lines, 401A and 401B. The center
of the transmission lines, 401A and 401B, are a distance (h) above
the conducting substrate 405.
[0049] According to the teachings of the present invention, in one
embodiment the thickness (b) of the insulator is equal to or less
than 1.0 micrometers (.mu.m). In one embodiment, the thickness (t)
of the of the transmission lines, 401A and 401B is approximately
equal to 1.0 micrometers (.mu.m). In one embodiment, the thickness
(t) of the transmission lines, 401A and 401B is less than 1.0
(.mu.m). In one embodiment, the width (a) of the transmission
lines, 401A and 401B is approximately 1.0 micrometers (.mu.m). As
one of ordinary skill in the art will appreciate upon reading the
present disclosure, one embodiment of the present invention
includes transmission lines 401A and 401B formed according to the
above described dimensions and separated from the substrate 405 by
an insulator having a thickness (b) of less than 1.0 micrometers
(.mu.m). In one exemplary embodiment, the transmission lines 401A
and 401B have an input impedance (Z.sub.0) approximately equal to
50 ohms.
[0050] A co-pending application, by the same inventors, entitled
"Capacitive Techniques to Reduce Noise in High Speed
Interconnections," application Ser. No. 10/060,801, filed 30 Jan.
2002, describes minimizing interwire coupling capacitance, and
making the insulator thickness over the group plane small,
minimizing Zo. The same is incorporated herein by reference.
According to the teachings described therein, a characteristic
impedance of 50 ohms is easily realizable.
[0051] FIG. 5 is a schematic diagram for an interconnection on an
integrated circuit 500 according to the teachings of the present
invention. The interconnection on the integrated circuit 500
includes a pair of transmission lines, 501A and 501B, in close
proximity. The first transmission line 501A is separated by a
distance (s) from the second transmission line 501B. The first
transmission line 501A and the second transmission line 501B each
have a first end, 505A and 505B respectively. In one embodiment,
the first end 505A for the first transmission line 501A is coupled
to a driver 503. The first transmission line 501A and the second
transmission line 501 B each have a second end, 506A and 506B
respectively. In one embodiment, the second end 506A is coupled to
a termination 504 formed using a complementary metal oxide
semiconductor (CMOS) process.
[0052] Reference to FIG. 5 is useful in explaining the reduced
amount of noise current between two transmission lines, 501A and
501B, using the current signaling technique of the present
invention. In one embodiment of the present invention, transmission
lines, 501A and 501B, have a low characteristic impedances Zo. In
one embodiment, the input impedance (Zin) seen by the driver 503
coupling to the first transmission line 501A (in this example the
"driven line") is just the characteristic impedance Zo for the
first transmission line 501A. In other words, the CMOS termination
504 is impedance matched to the characteristic impedance Zo of the
transmission line 501A.
[0053] In one embodiment, the first transmission line 501A is
separated by approximately 3 .mu.m from the second transmission
line 501B and the transmission lines have a length (l) of at least
500 .mu.m. In another embodiment the transmission lines, 501A and
501B, have a length (l) of at least 0.1 cm, or 1000 .mu.m. As in
FIGS. 4 and 5, the transmission lines, 501A and 501B, are separated
from a conducting substrate by an insulating layer. In one
embodiment, the insulating layer is an oxide layer. In this
embodiment, the capacitive coupling C between the transmission
lines, 501A and 501B, and the conducting substrate is given as
C.apprxeq.1.66/[ln(4h/a)] pF/cm. In one exemplary embodiment, each
transmission line, 501A and 501B, has a length (l) of 0.1 cm or
1000 .mu.m, each has a width (a) of approximately 1.0 .mu.m, and
the insulator layer thickness (b) is approximately 0.2 .mu.m. In
this embodiment, the ln(4h/a) will be approximately 1. Thus,
C.apprxeq.1.66/[ln(4h/a)] pF/cm and for a line 0.1 cm long will
produce a C.apprxeq.0.2 pF. In the same embodiment, the inductance
(L) for the transmission lines, 501A and 501B, over the oxide layer
is L.apprxeq.2.times.ln(4h/a) nH/cm, or L=0.2 nH for a line 0.1 cm
long. In this embodiment, a 1 milli Ampere (niA) current step,
i.sub.i(t), is applied to the gate 502 of a transistor driver 503.
In one embodiment, the driver is an n-channel source follower
driver 503. In this embodiment, the rise time (trise) on the gate
502 of the driver 503 is approximately 100 ps. This is the limiting
time on the system response since the signal delay (tprop) down a
the transmission line is proportional to {square root over (LC)}.
For a 0.1 cm transmission line, 501A or 501B, tprop is only 7 ps. A
current, di.sub.1(t)/dt, of approximately 1.times.10.sup.7 A/sec is
then produced on the first transmission line 501A.
[0054] The noise current i.sub.2(t) induced on the second
transmission line 501B by interwire capacitive coupling (Cint) is
calculated as approximately
i.sub.2(t)=(Cint).times.(V.sub.1step/trise). The interwire
capacitive coupling (Cint) between the transmission lines, 501A and
501B, separated by an oxide dielectric can be expressed as
Cint=0.46 pF/cm. Again, for a 0.1 cm transmission line, 501A or
501B, Cint.apprxeq.0.05 pF. As described in connection with FIG. 5,
a 1 mA current provided to the first transmission line 501A having
a low characteristic impedance Zo of approximately 30 Ohms will
result in a corresponding 30 mV Voltage step (V.sub.1step) on the
first transmission line 501A. Therefore, if trise is 100 ps a noise
current, i.sub.2(t), of approximately 0.015 mA is produced on the
second, neighboring, transmission line 501B. This noise current,
i.sub.2(t), induced in the second transmission line 501B is a very
small percentage, or about 1%, of the signal current i.sub.1(t)
provided to the first transmission line 501A. Hence, the signal to
noise ratio (SNR) will be large. It can be shown, in general, that
a signal to noise ratio (SNR) for the present invention, due to
capacitive coupling is of the order (C/Cint) (trise/tprop); where,
trise, is the rise time for the current signal and, tprop, the
signal propagation time down the first transmission line 501A. The
rise time on the signal current, i.sub.1(t), in the first
transmission line 501A is fast and just follows the rise time
(trise) on the input signal, or 100 ps. The response time of this
system utilizing current signals is thus much faster than those
using voltage signals.
[0055] Reference to FIG. 5 is similarly useful to illustrate the
noise voltage signal from magnetic coupling induced in the second
transmission line 501B by the signal current in the first
transmission line 501A. As shown in FIG. 5, a voltage will be
induced in the second transmission line 501B which has a magnitude
that depends on the trise, di.sub.1(t)/dt, of the current
i.sub.1(t) in the driven transmission line 501A, and the mutual
inductance coupling (M) between neighboring transmission lines,
e.g. 501A and 501B. Each transmission line, 501A and 501B, has an
inductance (L). As stated above, L.apprxeq.0.2 nH for a 0.1 cm
transmission line, 501A and 501B. In one exemplary embodiment, the
current i.sub.1(t) in the first transmission line, 501A (in this
example the "driven line") rises to 1 mA in 100 ps. A current,
di.sub.1(t)/dt, of approximately 1.times.10.sup.7 A/sec is then
produced on the first transmission line 501A. As presented above in
connection with FIGS. 3A and 3B, the mutual inductance coupling (M)
can be expressed as M=L.times.{1/[1+(s/h)2]}. In one exemplary
embodiment, s is approximately equal to 3 .mu.m, and h is
approximately equal to 0.7 .mu.m. In this embodiment, M will equate
to approximately M=0.02 nano Henrys (nH).
[0056] Using the relationship that the induced voltage
(Vind)=M.times.di.sub.1(t)/dt, Vind is approximately equal to 0.2
mV. During this 100 ps time period the induced voltage traveling
down the second transmission line 501B just sees the characteristic
impedance Zo of the second transmission line 501B. In one
embodiment Zo is approximately 30 Ohms, so here, the current
induced i.sub.2(t) in the second transmission line is
i.sub.2(t)=Vind/Zo or 0.007 mA. This low value current is only
approximately one percent (1%) of the signal current i.sub.1(t) on
the first transmission line, 501A. Hence, a large signal to noise
ratio (SNR) results. In contrast, under the prior technology, if
high impedance capacitive loads had been used on high
characteristic impedance lines and conventional voltage signaling
employed there is typically a large noise voltage between the
neighboring transmission lines, 501A and 501B. In the prior
technology, the large noise voltage can be about one half as big as
signal voltages.
[0057] The second transmission line 501B has an equivalently rapid
time constant, (L/R) to that of the first transmission line 501A.
In the embodiment presented above, the time constant is
approximately 7 pico seconds (ps). The noise current i.sub.2(t) in
the second transmission line 501B will reach a steady state in that
time constant. The noise current stays at this steady state value
until the end of trise, in this embodiment 100 ps, at which point
i.sub.1(t) stops changing. After this, the noise current in the
second line decays away very quickly. Again, when the input
impedance seen by the driver 503 is matched to the characteristic
impedance Zo of the first transmission line 501A, the signal to
noise ratio (SNR) due to inductive coupling between the first
transmission line 501A and the second, or neighboring, transmission
line 501B is of the order, (L/M) (trise/tprop). In other
embodiments, the actual mutual inductance and self inductances may
vary from these given values without departing from the scope of
the invention.
[0058] Inductive effects which become important at high speeds
include not only the self inductance of the interconnection lines,
L, but also the mutual inductance between lines, M. As shown with
respect to FIG. 5, previously the signal-to-noise ratio due to
inductive coupling between lines is of the order,
(L/M)(trise/tprop). Any technique which will minimize the mutual
inductance between lines will improve the signal-to-noise ratio on
long interconnection lines in integrated circuits with high
switching speeds.
[0059] The present invention, as described further below, provides
structures and methods through which inductive coupling on high
speed interconnects can be further reduced thus increasing the
signal to noise ratio across the same.
[0060] According to the teachings of the present invention,
inductive coupling can be minimized by: [0061] (i) magnetic shields
above and below the lines [0062] (ii) magnetic shields between
lines
[0063] These magnetic shields may be: [0064] (i) good conductors
with a thickness greater than the skin depth, the conventional
approach, but one which may not be possible or practical with
interconnection lines of sub-micron dimensions [0065] (ii) shields
with high permeability metals to minimize the mutual coupling or
inductance between lines
[0066] High speed interconnections are provided which accord
exemplary performance. That is, the invention described here
provides an improved and efficiently fabricated technique for high
speed transmission lines on CMOS integrated circuits. In addition,
the novel low input impedance CMOS circuit offers the following
advantages: (1) the signal delay depends only on the velocity of
light on the line and is easily predictable and reproducible,
eliminating or allowing for compensation for signal and/or clock
skew, (2) there are no reflections at the receiving end of the line
and this minimizes ringing, and (3) noise signals will be smaller
due to weaker coupling between lines resulting in better signal to
noise ratios, the noise current will only be a small fraction of
the signal current.
[0067] One embodiment of the invention includes a method for
forming transmission lines in an integrated circuit. The method
includes forming a first layer of electrically conductive material
on a substrate. A first layer of insulating material is formed on
the first layer of the electrically conductive material. A pair of
layered high permeability shielding lines are formed on the first
layer of insulating material. The pair of layered high permeability
shielding lines include layered perm alloy and Ni.sub.45Fe.sub.55
films. A transmission line is formed on the first layer of
insulating material and between and parallel with the pair of
layered high permeability shielding lines. A second layer of
insulating material is formed on the transmission line and the pair
of layered high permeability shielding lines. And, the method
includes forming a second layer of electrically conductive material
on the second layer of insulating material.
[0068] One embodiment of the invention, as discussed further below
in connection with FIG. 6, is a structure where an interconnection
line is located between a ground buss and a power supply buss
(which for the AC signal is AC ground) and as such constitutes a
low impedance transmission line interconnection. If the ground and
power supply busses are thicker than the skin depth at the
frequency of interest, the electric and magnetic fields will be
shielded and confined to the area between these plates. As shown in
the embodiment of FIG. 6, a layered high permeability shielding
line is placed between interconnection lines to distort the
magnetic fields and shield the lines.
[0069] Other possible configurations are shown in FIGS. 7-12. These
configurations highlight the fact that a single metal might not
have all the suitable properties for a given or desired
implementation by systems designed for low noise operation. For
example, two materials might be necessary, one which has the
desired magnetic properties to confine magnetic fields and one to
confine the electric fields. Accordingly, FIGS. 8-12 illustrate
various alternative embodiments of the present invention as can be
best suited to a particular system designed for low noise
operation. These embodiments make use of a sandwich layer of both a
high permeability material, well suited for magnetic shielding, as
well as a low resistive conductive material that is well suited for
electrical shielding. By placing even a thin layer of the high
permeability material, a considerable amount of the magnetic field
can be contained.
[0070] FIG. 6 illustrates one embodiment for a pair of neighboring
transmission lines, 601A and 601B, according to the teachings of
the present invention. FIG. 6 illustrates one or more transmission
lines, shown as 601A and 601B. The one or more transmission lines,
601A and 601B, are spaced between a pair of electrically conductive
planes 604 and 605. As one of ordinary skill in the art will
understand upon reading this disclosure, in one embodiment at least
one of the electrically conductive planes is formed on a substrate.
As one of ordinary skill in the art will understand upon reading
this disclosure, the substrate-can include an insulator, a
semiconductor material, silicon on insulator material, or other
materials. The invention is not so limited.
[0071] As shown in FIG. 6, the invention includes a number of
layered high permeability shielding lines, shown in this embodiment
as 602A and 602B. According to the teachings of the present
invention, the number of layered high permeability shielding lines,
602A and 602B, consist of alternating layers of high permeability
metal 670 and a low resistive conductive material 671. According to
the teachings of the present invention, the layers of high
permeability metal 670 include permalloy and Ni.sub.45Fe.sub.55
films. As shown in FIG. 6, the number of layered high permeability
shielding lines, 602A and 602B are interspaced between the one or
more transmission lines, 601A and 601B. In one embodiment of the
present invention, the one or more transmission lines, 601A and 601
B, and the number or layered high permeability shielding lines,
602A and 602B, are spaced parallel to one another and are oriented
lengthwise perpendicular to the plane of the page illustrated in
FIG. 6. In the invention, the one or more transmission lines, 601A
and 601B, and the number or layered high permeability shielding
lines, 602A and 602B, are separated from one another and from the
pair of electrically conductive planes 604 and 605 by an insulator
material 606. In one embodiment of the present invention, the
insulator material 606 includes an oxide.
[0072] In one embodiment as shown in FIG. 6, the pair of
electrically conductive planes 604 and 605 include metal ground
planes 604 and 605. In the invention, the electrically conductive
planes, 604 and 605, can be independently coupled to a ground
source and/or a power supply bus as the same will be known and
understood by one of ordinary skill in the art. In the embodiment
shown in FIG. 6, at least one of the pair of electrically
conductive planes, 604 and 605, is formed to a thickness (t) which
is greater than a skin depth (sd) penetrable by electrically
induced magnetic field lines.
[0073] As one of ordinary skill in the art will understand upon
reading this disclosure, an electrical signal transmitted across
the one or more transmission lines, 601A and 601B will induce a
magnetic field surrounding the one or more transmission lines, 601A
and 601B. In the embodiment of FIG. 6 such a magnetic field is
illustrated by magnetic field lines 611. According to the teachings
of the present invention, the number of layered high permeability
shielding lines, 602A and 602B, and the electrically conductive
planes, 604 and 605, provide magnetic shielding to reduce the
amount of magnetically induced noise on neighboring transmission
lines, e.g. 601A and 601B.
[0074] FIG. 7 illustrates another embodiment for a pair of
neighboring transmission lines, 701-1 and 701-2, according to the
teachings of the present invention. FIG. 7 illustrates one or more
transmission lines, shown as 701-1 and 701-2. The one or more
transmission lines, 701-1 and 701-2, are spaced between a pair of
electrically conductive planes 704 and 705. As one of ordinary
skill in the art will understand upon reading this disclosure, any
number of transmission lines, 701-1, . . . , 701-N, can be spaced
between the conductive planes 704 and 705. As one of ordinary skill
in the art will understand upon reading this disclosure, in one
embodiment at least one of the electrically conductive planes is
formed on a substrate. As one of ordinary skill in the art will
understand upon reading this disclosure, the substrate can include
an insulator, a semiconductor material, silicon on insulator
material, or other materials. The invention is not so limited.
[0075] As shown in FIG. 7, the invention includes a number of
layered high permeability shielding lines, shown in this embodiment
as 702-1 and 702-2. According to the teachings of the present
invention, the number of layered high permeability shielding lines,
702-1 and 702-2, consist of alternating layers of high permeability
metal 770 and a low resistive conductive material 771. According to
the teachings of the present invention, the layers of high
permeability metal 770 include permalloy and Ni.sub.45Fe.sub.55
films. As shown in FIG. 7, the number of layered high permeability
shielding lines, 702-1 and 702-2 are interspaced between the one or
more transmission lines, 701 -1 and 701-2. In one embodiment of the
present invention, the one or more transmission lines, 701-1 and
701-2, and the number or layered high permeability shielding lines,
702-1 and 702-2, are spaced parallel to one another and are
oriented lengthwise perpendicular to the plane of the page
illustrated in FIG. 7. As one of ordinary skill in the art will
understand upon reading this disclosure, any number of transmission
lines, 701-1, . . . , 701-N can be spaced between any number of
number layered high permeability shielding lines, 702-1, . . . ,
702-N. That is, one or more layered high permeability shielding
lines, 702-1, . . . , 702-N will separate one or more transmission
lines, 701-1, . . . , 701-N. In the invention, the one or more
transmission lines, 701-1 and 701-2, and the number or layered high
permeability shielding lines, 702-1 and 702-2, are separated from
one another and from the pair of electrically conductive planes 704
and 705 by an insulator material 706. In one embodiment of the
present invention, the insulator material 706 includes an
oxide.
[0076] In one embodiment as shown in FIG. 7, the pair of
electrically conductive planes 704 and 705 each include two
portions, 704A, 704B and 705A and 705B. In this embodiment, a first
portion, 704A and 705A respectively, include metal ground planes. A
second portion or surface portion, 704B and 705B respectively,
consist of alternating layers of high permeability metal 780 and a
low resistive conductive material 781. According to the teachings
of the present invention, the layers of high permeability metal 780
include permalloy and Ni.sub.45Fe.sub.55 films. That is, the second
portion or surface portion having the layers of high permeability
metal 780, adjacent to the one or more transmission lines, 701-1
and 701-2, and the number of layered high permeability shielding
lines 702-1 and 702-2, include layered permalloy and
Ni.sub.45Fe.sub.55 films. As one of ordinary skill in the art will
understand upon reading the present disclosure, the electrically
conductive planes, 704 and 705, can be independently coupled to a
ground source and/or a power supply bus.
[0077] As one of ordinary skill in the art will understand upon
reading this disclosure, an electrical signal transmitted across
the one or more transmission lines, 701-1 and 701-2 will induce a
magnetic field surrounding the one or more transmission lines,
701-1 and 701-2. In the embodiment of FIG. 7 such a magnetic field
is illustrated by magnetic field lines 711. According to the
teachings of the present invention, the number of layered high
permeability shielding lines, 702-1 and 702-2, and the electrically
conductive planes, 704 and 705, provide magnetic shielding to
reduce the amount of magnetically induced noise on neighboring
transmission lines, e.g. 701-1 and 701-2.
[0078] As shown in FIG. 7, the second portion or surface portion,
adjacent to the one or more transmission lines, 701-1 and 701-2,
and the number of layered high permeability shielding lines 702-1
and 702-2, each consisting of alternating layers of high
permeability metal 780, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 781, serve to shield
the one or more transmission lines, 701-1 and 701-2, from such
electrically induced magnetic fields. The magnetic field lines 711
shown in FIG. 7, illustrates the magnetic shielding effect provided
by the number of layered high permeability shielding lines, 702-1
and 702-2, and the second portion or surface portion 704B and 705B,
from magnetic fields produces by a current transmitted in the one
or more transmission lines, 701-1 and 701-2. As one of ordinary
skill in the art will understand upon reading this disclosure, the
first portion, 704A and 705A respectively, of the electrically
conductive planes, 704 and 705, provide a lower resistance such
that there is very little resistance to the path of the return
current.
[0079] As shown in the embodiment of FIG. 7 and other embodiments
below, the alternating layers of high permeability metal 780, e.g.
magnetic material permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 781 are formed on the inside of the
conductive planes 704 and 705, also referred to as the Vss or
ground, adjacent to the one or more transmission lines, 701 -1 and
701-2. However as one of ordinary skill in the art will understand
upon reading this disclosure, the alternating layers of high
permeability metal 780, e.g. magnetic material permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
781 can also be placed on the outside of the conductive planes 704
and 705. As one of ordinary skill in the art will understand upon
reading this disclosure, the alternating layers of high
permeability metal 780, e.g. magnetic material permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
781 confine both the electric and magnetic fields in both the x and
y direction.
[0080] FIG. 8 illustrates another embodiment for a pair of
neighboring transmission lines, 801-1 and 801-2, according to the
teachings of the present invention. FIG. 8 illustrates one or more
integrated circuit lines, or transmission lines, shown as 801-1 and
801-2. The one or more transmission lines, 801-1 and 801-2, are
spaced between a pair of electrically conductive planes 804 and
805. As one of ordinary skill in the art will understand upon
reading this disclosure, any number of transmission lines, 801-1, .
. . , 801-N, can be spaced between the conductive planes 804 and
805. As one of ordinary skill in the art will understand upon
reading this disclosure, in one embodiment at least one of the
electrically conductive planes is formed on a substrate. As one of
ordinary skill in the art will understand upon reading this
disclosure, the substrate can include an insulator, a semiconductor
material, silicon on insulator material, or other materials. The
invention is not so limited.
[0081] As shown in FIG. 8, the invention includes a number of
layered high permeability shielding lines, shown in this embodiment
as 802-1 and 802-2. In contrast to the embodiment of FIG. 7, the
number of layered high permeability shielding lines, 802-1 and
802-2 are layered vertically rather than horizontally. As shown in
FIG. 8, the number of layered high permeability shielding lines,
802-1 and 802-2 include alternating layers of high permeability
metal 870, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 871. As shown in FIG. 8, the number
of layered high permeability shielding lines, 802-1 and 802-2 are
interspaced between the one or more transmission lines, 801-1 and
801-2. In one embodiment of the present invention, the one or more
transmission lines, 801-1 and 801-2, and the number of layered high
permeability shielding lines, 802-1 and 802-2, are spaced parallel
to one another and are oriented lengthwise perpendicular to the
plane of the page illustrated in FIG. 8. As one of ordinary skill
in the art will understand upon reading this disclosure, any number
of transmission lines, 801-1, . . . , 801-N can be spaced between
any number of layered high permeability shielding lines, 802-1 and
802-N. That is, one or more layered high permeability shielding
lines, 802-1 and 802-2 will separate one or more transmission
lines, 801-1, . . . , 801-N. In the invention, the one or more
transmission lines, 801-1 and 801-2, and the number of layered high
permeability shielding lines, 802-1 and 802-2, are separated from
one another and from the pair of electrically conductive planes 804
and 805 by an insulator material 806. In one embodiment of the
present invention, the insulator material 806 includes an
oxide.
[0082] In one embodiment as shown in FIG. 8, the pair of
electrically conductive planes 804 and 805 each include two
portions, 804A, 804B and 805A and 805B. In this embodiment, a first
layer, 804A and 805A respectively, include metal ground planes. A
second layer or surface layer, 804B and 805B respectively, is
formed of alternating layers of high permeability metal 880, e.g.
permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 881. That is, the second layer or surface
layer, adjacent to the one or more transmission lines, 801-1 and
801-2, and the number of layered high permeability shielding lines,
802-1 and 802-2, are formed of alternating layers of high
permeability metal, e.g. permalloy and Ni.sub.45Fe.sub.55 films,
and a low resistive conductive material. As one of ordinary skill
in the art will understand upon reading the present disclosure, the
electrically conductive planes, 804 and 805, can be independently
coupled to a ground source and/or a power supply bus.
[0083] As one of ordinary skill in the art will understand upon
reading this disclosure, an electrical signal transmitted across
the one or more transmission lines, 801-1 and 801-2 will induce a
magnetic field surrounding the one or more transmission lines,
801-1 and 801-2. In the embodiment of FIG. 8 such a magnetic field
is illustrated by magnetic field lines 811. According to the
teachings of the present invention, the number of layered high
permeability shielding lines, 802-1 and 802-2 and the electrically
conductive planes, 804 and 805, provide magnetic shielding to
reduce the amount of magnetically induced noise on neighboring
transmission lines, e.g. 801-1 and 801-2.
[0084] As shown in FIG. 8, the second layer or surface portion 804B
and 805B, adjacent to the one or more transmission lines, 801-1 and
801-2, and the number of layered high permeability shielding lines,
802-1 and 802-2, each consisting of alternating layers of high
permeability metal, e.g. permalloy and Ni.sub.45Fe.sub.55 films,
and a low resistive conductive material, serve to shield the one or
more transmission lines, 801-1 and 801-2, from such electrically
induced magnetic fields. The magnetic field lines 811 shown in FIG.
8, illustrates the magnetic shielding effect provided by the number
of layered high permeability shielding lines, 802-1 and 802-2 and
the second layer or surface layer 804B and 805B, from magnetic
fields produces by a current transmitted in the one or more
transmission lines, 801-1 and 801-2. As one of ordinary skill in
the art will understand upon reading this disclosure, the first
layer, 804A and 805B respectively, of the electrically conductive
planes, 804 and 805, provide a lower resistance such that there is
very little resistance to the path of the return current.
[0085] In the embodiment shown in FIG. 8 both the electric and
magnetic fields are confined in both the x and y direction. Here
the conductors are separated by not only a high permeability
magnetic material but a sandwich of both a very low resistive
ground plane which acts as a low resistive return path for induced
currents and high permeability magnetic material.
[0086] FIG. 9 illustrates another embodiment for neighboring
transmission lines, 901 -1 and 901-2, according to the teachings of
the present invention. FIG. 9 illustrates one or more integrated
circuit lines, or transmission lines, shown as 901-1 and 901-2. The
one or more transmission lines, 901-1 and 901-2, are spaced between
a pair of electrically conductive planes 904 and 905. As one of
ordinary skill in the art will understand upon reading this
disclosure, any number of transmission lines, 901-1, . . . , 901-N,
can be spaced between the conductive planes 904 and 905. As one of
ordinary skill in the art will understand upon reading this
disclosure, in one embodiment at least one of the electrically
conductive planes is formed on a substrate. As one of ordinary
skill in the art will understand upon reading this disclosure, the
substrate can include an insulator, a semiconductor material,
silicon on insulator material, or other materials. The invention is
not so limited.
[0087] As shown in FIG. 9, the invention includes a number of
electrically conductive lines, 902-1 and 902-2. According to the
teachings of the present invention, the one or more transmission
lines, 901-1 and 901-2, include alternating layers of high
permeability metal 970, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 971. As shown in the
embodiment of FIG. 9, the alternating layers of high permeability
metal 970, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 971 are formed on the one or more
transmission lines, 901 -1 and 901-2, on at least three sides of
the number of transmission lines, 901-1 and 901-2. In this
embodiment, the three sides include opposing surfaces adjacent to
the number of electrically conductive lines, 902-1 and 902-2, and
on a side adjacent to the first conductive plane 904. As shown in
FIG. 9, the one or more transmission lines, 901-1 and 901-2, having
alternating layers of high permeability metal 970, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 971, are interspaced between the number or electrically
conductive metal lines, 902-1 and 902-2. In one embodiment of the
present invention, the one or more transmission lines, 901 -1 and
901-2, and the number or electrically conductive metal lines, 902-1
and 902-2, are spaced parallel to one another and are oriented
lengthwise perpendicular to the plane of the page illustrated in
FIG. 9. As one of ordinary skill in the art will understand upon
reading this disclosure, any number of transmission lines, 901-1, .
. . , 901-N, having alternating layers of high permeability metal
970, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 971, can be spaced between any number
of number electrically conductive metal lines, 902-1, . . . ,
902-N. That is, one or more electrically conductive metal lines,
902-1, . . . , 902-N will separate one or more transmission lines,
901-1, . . . , 901-N. In the invention, the one or more
transmission lines, 901-1 and 901-2, and the number or electrically
conductive metal lines, 902-1 and 902-2, are separated from one
another and from the pair of electrically conductive planes 904 and
905 by an insulator material 906. In one embodiment of the present
invention, the insulator material 906 includes an oxide.
[0088] In one embodiment as shown in FIG. 9, the at least one of
the pair of electrically conductive planes 904 and 905 includes two
portions. In the embodiment shown in FIG. 9, conductive plane 905
includes two portions, 905A and 905B. In this embodiment,
conductive plane 904, and a first layer 905A for conductive plane
905, include metal ground planes. In conductive plane 905 a second
layer or surface layer 905B, is formed of alternating layers of
high permeability metal 980, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 981. That is, the
second layer or surface layer, 905B adjacent to the one or more
transmission lines, 901-1 and 901-2, and the number of electrically
conductive metal lines 902-1 and 902-2, both include alternating
layers of high permeability metal, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material.
As one of ordinary skill in the art will understand upon reading
the present disclosure, the electrically conductive planes, 904 and
905, can be independently coupled to a ground source and/or a power
supply bus.
[0089] As one of ordinary skill in the art will understand upon
reading this disclosure, an electrical signal transmitted across
the one or more transmission lines, 901-1 and 901-2 will induce a
magnetic field surrounding the one or more transmission lines,
901-1 and 901-2. In the embodiment of FIG. 9 such a magnetic field
is illustrated by magnetic field lines 911. According to the
teachings of the present invention, the one or more transmission
lines, 901-1 and 901-2, having alternating layers of high
permeability metal 970, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 971, the number of
electrically conductive metal lines 902-1 and 902-2, and the
electrically conductive planes, 904 and 905, provide magnetic
shielding to reduce the amount of magnetically induced noise on
neighboring transmission lines, e.g. 901-1 and 901-2.
[0090] As shown in FIG. 9, the second layer or surface layer 905B,
adjacent to the one or more transmission lines, 901 -1 and 901-2,
having alternating layers of high permeability metal 970, e.g.
permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 971, the electrically conductive planes, 904
and 905, and the number of electrically conductive metal lines
902-1 and 902-2, serve to shield the one or more transmission
lines, 901-1 and 901-2, from such electrically induced magnetic
fields. The magnetic field lines 911 shown in FIG. 9, illustrates
the magnetic shielding effect provided by the one or more
transmission lines, 901-1 and 901-2, having alternating layers of
high permeability metal 970, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 971, the number of
electrically conductive metal lines 902-1 and 902-2 and the second
layer or surface layer 905B, from magnetic fields produced by a
current transmitted in the one or more transmission lines, 901-1
and 901-2. As one of ordinary skill in the art will understand upon
reading this disclosure, conductive plane 904 and the first layer
905A of conductive plane 905 provide a lower resistance such that
there is very little resistance to the path of the return
current.
[0091] The embodiment provided in FIG. 9 is easy to manufacture.
Here the current carrying low resistive conductors or metal lines,
e.g. 901-1 and 901-2 are encased on three sides by a high
permeability magnetic material and separated from one another by
low resistive metal lines 902-1 and 902-2 that are grounded. To
provide magnetic field confinement in the Y direction, a sandwich
layer is used at the top of the conductors as provided by second
layer 905B. This sandwich layer is composed of both a low resistive
component as well as a high permeability component. The bottom
side, e.g. conductive plane 904, of the embedded metal lines or
conductors 901-1 and 901-2 contain only a ground plane. This
provides complete electric and magnetic field confinement.
[0092] FIG. 10 illustrates another embodiment for neighboring
transmission lines, 1001-1 and 1001-2, according to the teachings
of the present invention. FIG. 10 illustrates one or more
integrated circuit lines, or transmission lines, shown as 1001-1
and 1001-2 having alternating layers of high permeability metal
1070, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 1071. The one or more transmission
lines, 1001-1 and 1001-2, are spaced between a pair of electrically
conductive planes 1004 and 1005. As one of ordinary skill in the
art will understand upon reading this disclosure, any number of
transmission lines, 1001-1, . . . , 1001-N, can be spaced between
the conductive planes 1004 and 1005. As one of ordinary skill in
the art will understand upon reading this disclosure, in one
embodiment at least one of the electrically conductive planes is
formed on a substrate. As one of ordinary skill in the art will
understand upon reading this disclosure, the substrate can include
an insulator, a semiconductor material, silicon on insulator
material, or other materials. The invention is not so limited.
[0093] As shown in FIG. 10, the invention includes a number of
electrically conductive metal lines, 1002-1 and 1002-2, alternating
layers of high permeability metal 1090, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
1091. As shown in the embodiment of FIG. 10, the alternating layers
of high permeability metal 1090, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
1091 are formed on the number of electrically conductive metal
lines, 1002-1 and 1002-2, on at least three sides of the number of
electrically conductive metal lines, 1002-1 and 1002-2. In this
embodiment, the three sides include opposing surfaces adjacent to
the one or more transmission lines, 1001-1 and 1001-2, and on a
side adjacent to the first conductive plane 1004. As shown in FIG.
10, the number of electrically conductive metal lines, 1002-1 and
1002-2, having alternating layers of high permeability metal 1090,
e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 1091, are interspaced between the one or more
transmission lines, 1001-1 and 1001-2. Further, in this embodiment,
the one or more transmission lines, 1001-1 and 1001-2, include
alternating layers of high permeability metal 1070, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1071. As shown in the embodiment of FIG. 10, the
alternating layers of high permeability metal 1070, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1071 are formed on the one or more transmission lines,
1001-1 and 1001-2, on at least three sides of the number of
transmission lines, 1001-1 and 1001-2. In this embodiment, the
three sides include opposing surfaces adjacent to the number of
electrically conductive lines, 1002-1 and 1002-2, and on a side
adjacent to the first conductive plane 1004. As shown in FIG. 10,
the one or more transmission lines, 1001-1 and 1001-2, having
alternating layers of high permeability metal 1070, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1071, are interspaced between the number or electrically
conductive metal lines, 1002-1 and 1002-2 also having alternating
layers of high permeability metal 1090, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
1091. In one embodiment of the present invention, the one or more
transmission lines, 1001-1 and 1001-2, and the number or
electrically conductive metal lines, 1002-1 and 1002-2, are spaced
parallel to one another and are oriented lengthwise perpendicular
to the plane of the page illustrated in FIG. 10. As one of ordinary
skill in the art will understand upon reading this disclosure, any
number of transmission lines, 1001-1, . . . , 1001-N, having
alternating layers of high permeability metal 1070, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1071, can be spaced between any number of number
electrically conductive metal lines, 1002-1, . . . , 1002-N also
having alternating layers of high permeability metal 1090, e.g.
permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 1091. That is, one or more electrically
conductive metal lines, 1002-1, . . . , 1002-N will separate one or
more transmission lines, 1001-1, . . . , 1001-N. In the invention,
the one or more transmission lines, 1001-1 and 1001-2, and the
number or electrically conductive metal lines, 1002-1 and 1002-2,
are separated from one another and from the pair of electrically
conductive planes 1004 and 1005 by an insulator material 1006. In
one embodiment of the present invention, the insulator material
1006 includes an oxide.
[0094] In one embodiment as shown in FIG. 10, at least one of the
pair of electrically conductive planes 1004 and 1005 includes two
portions. In the embodiment shown in FIG. 10, conductive plane 1005
includes two portions, 1005A and 1005B. In this embodiment,
conductive plane 1004, and a first layer 1005A for conductive plane
1005, include metal ground planes. In conductive plane 1005 a
second layer or surface layer 1005B, is formed of alternating
layers of high permeability metal 1080, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
1081. As one of ordinary skill in the art will understand upon
reading the present disclosure, the electrically conductive planes,
1004 and 1005, can be independently coupled to a ground source
and/or a power supply bus.
[0095] As one of ordinary skill in the art will understand upon
reading this disclosure, an electrical signal transmitted across
the one or more transmission lines, 1001-1 and 1001-2 will induce a
magnetic field surrounding the one or more transmission lines,
1001-1 and 1001-2. In the embodiment of FIG. 10 such a magnetic
field is illustrated by magnetic field lines 1011. According to the
teachings of the present invention, the one or more transmission
lines, 1001-1 and 1001-2, having alternating layers of high
permeability metal 1070, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1071, the number of
electrically conductive metal lines 1002-1 and 1002-2 also having
alternating layers of high permeability metal 1090, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1091, and the electrically conductive planes, 1004 and
1005, provide magnetic shielding to reduce the amount of
magnetically induced noise on neighboring transmission lines, e.g.
1001-1 and 1001-2.
[0096] As shown in FIG. 10, the one or more transmission lines,
1001-1 and 1001-2, having alternating layers of high permeability
metal 1070, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 1071, the electrically conductive
planes, 1004 and 1005, and the number of electrically conductive
metal lines 1002-1 and 1002-2 also having alternating layers of
high permeability metal 1090, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1091, serve to
shield the one or more transmission lines, 1001-1 and 1001-2, from
such electrically induced magnetic fields. The magnetic field lines
1011 shown in FIG. 10, illustrates the magnetic shielding effect
provided by the one or more transmission lines, 1001-1 and 1001-2,
having alternating layers of high permeability metal 1070, e.g.
permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 1071, the number of electrically conductive
metal lines 1002-1 and 1002-2 also having alternating layers of
high permeability metal 1090, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1091, and the second
layer or surface layer 1005B, from magnetic fields produced by a
current transmitted in the one or more transmission lines, 1001-1
and 1001-2. As one of ordinary skill in the art will understand
upon reading this disclosure, conductive plane 1004 and the first
layer 1005A provide a lower resistance such that there is very
little resistance to the path of the return current.
[0097] FIG. 10 is another embodiment that is very easy to
manufacture. The main difference in the embodiment of FIG. 10 from
the embodiment provided in FIG. 9 is that in this case the number
of electrically conductive metal lines 1002-1 and 1002-2, which
where previously used only for electric field confinement can also
be used for magnetic field confinement. An alternate configuration
to that shown in FIG. 10 is shown in FIG. 12. In FIG. 12,
conductors 1201-1 and 1201-2 do not have a magnetic material around
them.
[0098] FIG. 11 illustrates another embodiment for neighboring
transmission lines, 1101-1 and 1101-2, according to the teachings
of the present invention. FIG. 11 illustrates one or more
integrated circuit lines, or transmission lines, shown as 1101-1
and 1101 -2, having alternating layers of high permeability metal
1170, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 1171. The one or more transmission
lines, 1101-1 and 1101-2, are spaced between a pair of electrically
conductive planes 1104 and 1105. As one of ordinary skill in the
art will understand upon reading this disclosure, any number of
transmission lines, 1101-1, . . . , 1101-N, can be spaced between
the conductive planes 1104 and 1105. As one of ordinary skill in
the art will understand upon reading this disclosure, in one
embodiment at least one of the electrically conductive planes is
formed on a substrate. As one of ordinary skill in the art will
understand upon reading this disclosure, the substrate can include
an insulator, a semiconductor material, silicon on insulator
material, or other materials. The invention is not so limited.
[0099] As shown in FIG. 11, the invention includes a number of
layered high permeability shielding lines, shown in this embodiment
as 1102-1 and 1102-2. According to the teachings of the present
invention, the number of layered high permeability shielding lines,
1102-1 and 1102-2, are formed of alternating layers of high
permeability metal 1190, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1191. As shown in
FIG. 1 1, the number of layered high permeability shielding lines,
1102-1 and 1102-2 are interspaced between the one or more
transmission lines, 1101-1 and 1101-2. In one embodiment of the
present invention, the one or more transmission lines, 1101-1 and
1101-2, and the number or layered high permeability shielding
lines, 1102-1 and 1102-2, are spaced parallel to one another and
are oriented lengthwise perpendicular to the plane of the page
illustrated in FIG. 11. As shown in the embodiment of FIG. 11, the
alternating layers of high permeability metal 1170, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1 171 are formed on the one or more transmission lines,
1101-1 and 1101-2, in an orientation parallel to the first and the
second conductive planes 1104 and 1105. As shown in FIG. 11, the
one or more transmission lines, 1101-1 and 1101-2, having at least
one surface layer 1115 formed of a layered perm alloy and
Ni.sub.45Fe.sub.55 film, are interspaced between the number layered
high permeability shielding lines, 1102-1 and 1102-2. In one
embodiment of the present invention, the one or more transmission
lines, 1101-1 and 1101-2, and the number or layered high
permeability shielding lines, 1102-1 and 1102-2, are spaced
parallel to one another and are oriented lengthwise perpendicular
to the plane of the page illustrated in FIG. 11. As one of ordinary
skill in the art will understand upon reading this disclosure, any
number of transmission lines, 1101-1, . . . , 1101-N, having at
least one surface layer 1115 formed of a layered permalloy and
Ni.sub.45Fe.sub.55 film, can be spaced between any number of number
layered high permeability shielding lines, 1102-1, . . . , 1102-N.
That is, one or more layered high permeability shielding lines,
1102-1, . . . , 1102-N will separate one or more transmission
lines, 1101-1, . . . , 1101-N. In the invention, the one or more
transmission lines, 1101-1 and 1101-2, and the number or layered
high permeability shielding lines, 1102-1 and 1102-2, are separated
from one another and from the pair of electrically conductive
planes 1104 and 1105 by an insulator material 1106. In one
embodiment of the present invention, the insulator material 1106
includes an oxide. In an alternative embodiment, the one or more
transmission lines, 1101-1 and 1101-2, having alternating layers of
high permeability metal 1170, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1171, and the number
or layered high permeability shielding lines, 1102-1 and 1102-2, do
not have to be located between the pair of electrically conductive
planes 1104 and 1105, but are still encapsulated by an insulator
material 1106. As one of ordinary skill in the art will understand
upon reading the present disclosure, the high permeability planes,
1104 and 1105, can be independently coupled to a ground source
and/or a power supply bus.
[0100] As one of ordinary skill in the art will understand upon
reading this disclosure, an electrical signal transmitted across
the one or more transmission lines, 1101-1 and 1101-2 will induce a
magnetic field surrounding the one or more transmission lines,
1101-1 and 1101-2. In the embodiment of FIG. 11 such a magnetic
field is illustrated by magnetic field lines 1111. According to the
teachings of the present invention, the one or more transmission
lines, 1101-1 and 1101-2, having alternating layers of high
permeability metal 1170, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1171, the number of
layered high permeability shielding lines 1102-1 and 1102-2, having
alternating layers of high permeability metal 1190, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1191, and the electrically conductive planes, 1104 and
1105, provide magnetic shielding to reduce the amount of
magnetically induced noise on neighboring transmission lines, e.g.
1101-1 and 1101-2.
[0101] As shown in FIG. 11, the one or more transmission lines,
1101-1 and 1101-2, having alternating layers of high permeability
metal 1170, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 1171, the electrically conductive
planes, 1104 and 1105, and the number of layered high permeability
shielding lines 1102-1 and 1102-2 having alternating layers of high
permeability metal 1190, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1191, serve to
shield the one or more transmission lines, 1101-1 and 1101-2, from
such electrically induced magnetic fields. The magnetic field lines
1111 shown in FIG. 11, illustrates the magnetic shielding effect
provided by the one or more transmission lines, 1101-1 and 1101-2,
having alternating layers of high permeability metal 1170, e.g.
permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 1171, the electrically conductive planes, 1104
and 1105, and the number of layered high permeability shielding
lines 1102-1 and 1102-2 having alternating layers of high
permeability metal 1190, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1191, from magnetic
fields produced by a current transmitted in the one or more
transmission lines, 1101-1 and 1101-2. As one of ordinary skill in
the art will understand upon reading this disclosure, the
electrically conductive planes, 1104 and 1105, provide a lower
resistance such that there is very little resistance to the path of
the return current.
[0102] The embodiment provided in FIG. 11 is another possibility
that provides for magnetic confinement in all directions, but in
this case, the magnetic material is only placed at the top and
bottom of conductors 1101-1 and 1101-2. These conductors are
separated by a high permeability magnetic material. In the
embodiment of FIG. 11, the one or more transmission lines 1101-1
and 1101-2 are enclosed by low resistive metals, e.g. conductive
planes 1104 and 1105 on both sides.
[0103] FIG. 12 illustrates another embodiment for neighboring
transmission lines, 1201-1 and 1201-2, according to the teachings
of the present invention. FIG. 12 illustrates one or more
integrated circuit lines, or transmission lines, shown as 1201-1
and 1201-2. The one or more transmission lines, 1201-1 and 1201-2,
are spaced between a pair of electrically conductive planes 1204
and 1205. As one of ordinary skill in the art will understand upon
reading this disclosure, any number of transmission lines, 1201-1,
. . . , 1201-N, can be spaced between the conductive planes 1204
and 1205. As one of ordinary skill in the art will understand upon
reading this disclosure, in one embodiment at least one of the
electrically conductive planes is formed on a substrate. As one of
ordinary skill in the art will understand upon reading this
disclosure, the substrate can include an insulator, a semiconductor
material, silicon on insulator material, or other materials. The
invention is not so limited.
[0104] As shown in FIG. 12, the invention includes a number of
electrically conductive metal lines, shown in this embodiment as
1202-1 and 1202-2. According to the teachings of the present
invention, the number of electrically conductive metal lines,
1202-1 and 1202-2, include alternating layers of high permeability
metal 1290, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 1291. As shown in the embodiment of
FIG. 12, the alternating layers of high permeability metal 1290,
e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 1291 are formed on the number of electrically
conductive metal lines, 1202-1 and 1202-2, on at least three sides
of the number of electrically conductive metal lines, 1202-1 and
1202-2. In this embodiment, the three sides include opposing
surfaces adjacent to the one or more transmission lines, 1201-1 and
1201-2, and on a side adjacent to the first conductive plane 1204.
As shown in FIG. 12, the number of electrically conductive metal
lines, 1202-1 and 1202-2, having alternating layers of high
permeability metal 1290, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1291, are
interspaced between the one or more transmission lines, 1201-1 and
1201-2. As shown in FIG. 12, the one or more transmission lines,
1201-1 and 1201-2 are interspaced between the number or
electrically conductive metal lines, 1202-1 and 1202-2 having
alternating layers of high permeability metal 1290, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1291. In one embodiment of the present invention, the one
or more transmission lines, 1201-1 and 1201-2, and the number or
electrically conductive metal lines, 1202-1 and 1202-2, are spaced
parallel to one another and are oriented lengthwise perpendicular
to the plane of the page illustrated in FIG. 12.
[0105] As one of ordinary skill in the art will understand upon
reading this disclosure, any number of transmission lines, 1201-1,
. . . , 1201-N, can be spaced between any number of number
electrically conductive metal lines, 1202-1, . . . , 1202-N having
alternating layers of high permeability metal 1290, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1291. That is, one or more electrically conductive metal
lines, 1202-1, . . . , 1202-N, having alternating layers of high
permeability metal 1290, e.g. permalloy and Ni.sub.45Fe.sub.55
films, and a low resistive conductive material 1291, will separate
one or more transmission lines, 1201-1, . . . , 1201-N. In the
invention, the one or more transmission lines, 1201-1 and 1201-2,
and the number or electrically conductive metal lines, 1202-1 and
1202-2, are separated from one another and from the pair of
electrically conductive planes 1204 and 1205 by an insulator
material 1206. In one embodiment of the present invention, the
insulator material 1206 includes an oxide.
[0106] In one embodiment as shown in FIG. 12, the electrically
conductive planes 1204 and 1205 includes two portions, e.g. 1204A,
1204B, 1205A and 1205B. In this embodiment, a first layer 1204A for
conductive plane 1204, and a first layer 1205A for conductive plane
1205, include metal ground planes. In conductive planes 1204 and
1205 a second layer or surface layer 1204B and 1205B, are formed of
alternating layers of high permeability metal 1280, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1281. As one of ordinary skill in the art will understand
upon reading the present disclosure, the electrically conductive
planes, 1204 and 1205, can be independently coupled to a ground
source and/or a power supply bus.
[0107] As one of ordinary skill in the art will understand upon
reading this disclosure, an electrical signal transmitted across
the one or more transmission lines, 1201-1 and 1201-2 will induce a
magnetic field surrounding the one or more transmission lines,
1201-1 and 1201-2. In the embodiment of FIG. 12 such a magnetic
field is illustrated by magnetic field lines 1211. According to the
teachings of the present invention, the number of electrically
conductive metal lines 1202-1 and 1202-2 having alternating layers
of high permeability metal 1290, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
1291, and the electrically conductive planes, 1204 and 1205 also
having alternating layers of high permeability metal 1280, e.g.
permalloy and Ni.sub.45Fe.sub.55 films, and a low resistive
conductive material 1281, provide magnetic shielding to reduce the
amount of magnetically induced noise on neighboring transmission
lines, e.g. 1201-1 and 1201-2.
[0108] As shown in FIG. 12, the electrically conductive planes,
1204 and 1205, having alternating layers of high permeability metal
1280, e.g. permalloy and Ni.sub.45Fe.sub.55 films, and a low
resistive conductive material 1281, and the number of electrically
conductive metal lines 1202-1 and 1202-2 also having alternating
layers of high permeability metal 1290, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
1291, serve to shield the one or more transmission lines, 1201-1
and 1201-2, from such electrically induced magnetic fields. The
magnetic field lines 1211 shown in FIG. 12, illustrates the
magnetic shielding effect provided by the number of electrically
conductive metal lines 1202-1 and 1202-2 having alternating layers
of high permeability metal 1290, e.g. permalloy and
Ni.sub.45Fe.sub.55 films, and a low resistive conductive material
1291, and the electrically conductive planes, 1204 and 1205, having
alternating layers of high permeability metal 1280, e.g. permalloy
and Ni.sub.45Fe.sub.55 films, and a low resistive conductive
material 1281, from magnetic fields produced by a current
transmitted in the one or more transmission lines, 1201-1 and
1201-2. As one of ordinary skill in the art will understand upon
reading this disclosure, the first layer 1204A of conductive plane
1204 and the first layer 1205A of conductive plane 1205 provide a
lower resistance such that there is very little resistance to the
path of the return current. FIG. 12 highlights a configuration that
is similar to FIG. 10 but allows for more space to be used for
conductors 1201-1 and 1201-2 since they are not encased on magnetic
material.
[0109] FIG. 13 is a block diagram which illustrates an embodiment
of a system 1300 using line signaling according to teachings of the
present invention. The system 1300 includes a low output impedance
driver 1310 having a driver impedance, as is well known in the art.
The low output impedance driver 1310 is coupled to a transmission
line circuit 1320. Embodiments of the transmission line circuit
1320 are described and presented above with reference to FIGS.
6-12. Moreover, the system 1300 includes a termination circuit 1330
having a termination impedance that is matched to the impedance of
the transmission line circuit 1320.
[0110] FIG. 14 is a block diagram which illustrates an embodiment
of a system 1400 according to teaching of the present invention.
The system 1400 includes an integrated circuit 1410. The integrated
circuit 1410 includes the transmission line circuit described and
presented above with reference to FIGS. 6-12. Additionally, the
system 1400 includes a processor 1420 that is operatively coupled
to the integrated circuit 1410. The processor 1420 is coupled to
the integrated circuit 1410 through a system bus 1430. In one
embodiment, the processor 1420 and the integrated circuit 1410 are
on the same semiconductor chip.
High Frequency Permeability Films
[0111] The study of high frequency permeability of thin-film
magnetic stripes under high field excitation is important for the
development of high rate data read heads as discussed in an article
by Yimin Hsu et al. (See generally, J. Appl. Phys., 89, 11, 6808
(2001)). The measurement is conventionally performed by using
permeameters as described in articles by B. C. Webb et al. (See
generally, J. Appl. Phs., 69, 5611 (1991); and IEEE Trans. Magn.,
27, 4876 (1991)). However, it is difficult to perform the
measurement in both high field excitation and at 100 MHz and
beyond. In a recent article, the high field high frequency
permeability of permalloy and Ni.sub.45Fe.sub.55 patterned films is
measured from lithographically defined toroidal devices. (See
generally, Yimin Hsu et al., J. Appl. Phys., 89, 11, 6808 (2001)).
Permeability and rolloff characteristics as the patterned width is
reduced are discussed therein.
[0112] In the above article, test structures were fabricated having
toroidal shapes with widths ranging from 0.5 to 30 .mu.m. Each
toroid consists of two parallel rectangular-shape patterned films
connected by "pedestals" at both ends. The base designed of the
test structure 55 .mu.m long with ten-turn coils. The coils are
embedded in alumina and these devices are fully planarized by the
chemical-mechanical-polish process to avoid undesirable stress
induced by topography. In this experiment, the bottom layers are
2.5 .mu.m thick permalloy and the pedestals are 2.2 .mu.m tall
permalloy. One wafer has 2.5 .mu.m of permalloy and top layers and
other Ni.sub.45Fe.sub.55. The inductance rolloff date of these
structures are measured by using a Hewlett Packard 4291 A impedance
analyzer. The test structures are excited by applying high
frequency current to the pancake coils. The permeability frequency
rolloff characteristics of the magnetic thin films were calculated
from the inductance rolloff data by using the segmental
transmission line method as described in an article by T.
Amoldussen. (See generally, IEEE Trans. Magn., 24, 2482 (1988)).
The simple geometry of these devices minimizes the ambiguity in
permeability calculations.
[0113] Permeability of patterned permalloy and Ni.sub.45Fe.sub.55
films with widths from 30 to 0.5 .mu.m has been studied under high
field up to 5 Oe and frequency up to 500 MHz. It is observed that
the permeability increases as the excitation field increases due to
the increasing flux conduction from wall motion. At frequencies
where wall motion is damped, there is no discernible difference
between high and low field excitation. The data also suggest that
the permeability rolloff measured at low excitation current is
sufficient to predict high frequency write head performance. As the
width of the patterns is reduced, the reduction of effective
rotational permeability results from reduction of the active area
since the edge closure region does not participate in flux
conduction. As the width is reduced to sub-micron range, the
rotational permeability is significantly reduced. The 0.5 .mu.m
wide device has .mu..sub.rot of 80 for the permalloy case and 50
for the Ni.sub.45Fe.sub.55 case.
[0114] A new process has been used in the industry to measure the
high permeability materials at high frequencies, up to 1 GHz. (See
generally, M. Senda, "Permeability measurement of soft magnetic
films at high frequency and multilayering effect," IEEE Translation
of J. of Magnetics in Japan, Vol. 8, No. 3, pp. 161-168, March
1993). An inductance line with a magnetic/conductive/magnetic layer
structure was used to estimate the permeability (to see the details
of the parts, a reader is recommended to see the original text
cited above). The inductance line made it possible to measure the
frequency characteristics of the permeability up to the GHz range
because of a low stray capacitance and high resonance frequency.
The magnetic film pattern was designed so as to eliminate
demagnetizing field effects, and the permeability was estimated
based on analysis of the magnetic circuit. Using this method,
NiFe/SiO.sub.2 and (Fe/SiO.sub.2)/SiO.sub.2 multilayer films were
confirmed to show superior frequency characteristics by a factor of
20 over those of NiFe single-layer film. Also, ferromagnetic
resonance (FMR) was observed in these multilayer films at 650 and
750 MHz.
[0115] A Hewlett Packard HP4191 A was used in impedance
measurements. Specialized tubes (16091-60023) were connected to
both ends of the sample, and these were mounted inside a
cylindrical fixture (16091A) to perform measurements. The sample
impedance ranged from several Ohms to several ten of Ohms between
10 MHz and 1000 MHz, and above several tens of MHz the instrument
measurement error was within several percent.
[0116] The method of measurement was confirmed to operate as
expected, and the high-frequency magnetic characteristics of
multilayer films were evaluated, and the main results are as
follows: [0117] 1. Through this method, the magnetic circuit
composed of an inductance line with a magnetic/conductive/magnetic
films structures was analyzed the basis of its impedance
characteristics, enabling calculation of the relative permeability
of the magnetic material. The inductance line had a stripe shape,
and the stray capacitance was reduced to raise the resonance
frequency, making possible measurements in the GHz range. By
adopting a strip pattern for the magnetic layers, the effect of the
demagnetizing field was avoided. In order to perform still more
accurate measurements, it will probably be necessary to add
improvements to the magnetic circuit analysis and impedance
matching. [0118] 2. It was confirmed that the multilayer structure
including none magnetic layers is an effective means of improving
the frequency characteristic, reducing losses and expanding the
effective magnetic path width. For NiFe/SiO.sub.2 [50-100 nm] and
(Fe/SiO.sub.2)SiO.sub.2 [(7/2.5)/50 nm] multilayer film, an
improvement of some twenty times or so over NiFe single-layer film
was observed. [0119] 3. The high-frequency magnetic properties of
multilayer film are limited by dielectric breakdown of the
insulating layers when the latter are thin, and by eddy current
loss due to formation of an electrical capacitance and/or by
ferromagnetic resonance when the insulating layer are thick.
Ferromagnetic resonance was observed at 650 MHz in the
NiFe/SiO.sub.2, and at 750 MHz in the (Fe/SiO.sub.2)SiO.sub.2
multilayer films.
[0120] These results demonstrate that the characteristics of
multilayer films involving non-magnetic materials as well as NiFe
or Fe magnetic materials have higher effective permeabilities at
higher frequencies than simple layers of magnetic materials by
themselves. This disclosure then describes the use of the
multilayers as magnetic shields to reduce the inductive coupling
between interconnection lines in integrated circuits.
CONCLUSION
[0121] Thus, structures and methods are provided for improved, high
speed transmission lines on integrated circuits. High speed
interconnections are provided which accord exemplary performance.
That is, the invention described here provides an improved and
efficiently fabricated technique for high speed transmission lines
on CMOS integrated circuits. In addition, the novel low input
impedance CMOS circuit offers the following advantages: (1) the
signal delay depends only on the velocity of light on the line and
is easily predictable and reproducible, eliminating or allowing for
compensation for signal and/or clock skew, (2) there are no
reflections at the receiving end of the line and this minimizes
ringing, and (3) noise signals will be smaller due to weaker
coupling between lines resulting in better signal to noise ratios,
the noise current will only be a small fraction of the signal
current.
[0122] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. It is to be understood that the above
description is intended to be illustrative, and not restrictive.
Combinations of the above embodiments, and other embodiments will
be apparent to those of skill in the art upon reviewing the above
description. The scope of the invention includes any other
applications in which the above structures and fabrication methods
are used. The scope of the invention should be determined with
reference to the appended claims, along with the full scope of
equivalents to which such claims are entitled.
* * * * *