U.S. patent application number 11/342287 was filed with the patent office on 2007-01-18 for iii/v-semiconductor.
This patent application is currently assigned to Philips-Universitat Marburg. Invention is credited to Jorg Koch, Bernardette Kunert, Stefan Reinhard, Wolfgang Stolz, Kerstin Volz.
Application Number | 20070012908 11/342287 |
Document ID | / |
Family ID | 36650663 |
Filed Date | 2007-01-18 |
United States Patent
Application |
20070012908 |
Kind Code |
A1 |
Kunert; Bernardette ; et
al. |
January 18, 2007 |
III/V-semiconductor
Abstract
The invention relates to a monolithic integrated semiconductor
structure comprising a carrier layer on the basis of doped Si or
doped GaP and a III/V semiconductor disposed thereupon and having
the composition Ga.sub.xIn.sub.yN.sub.aAs.sub.bP.sub.cSb.sub.d,
wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%,
b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the
total of x and y is always 100 mole-%, wherein the total of a, b, c
and d is always 100 mole-%, and wherein the ratio of the totals of
x and y on the one hand and of a to d on the other hand is
substantially 1:1, to methods for the production thereof, new
semiconductors, the use thereof for the production of luminescence
diodes and laser diodes or also modulator and detector structures,
which are monolithically integrated in integrated circuits on the
basis of the Si or GaP technology.
Inventors: |
Kunert; Bernardette;
(Marburg, DE) ; Koch; Jorg; (Dautphetal, DE)
; Reinhard; Stefan; (Rauschenberg-Bracht, DE) ;
Volz; Kerstin; (Dautphetal, DE) ; Stolz;
Wolfgang; (Marburg, DE) |
Correspondence
Address: |
MAYER & WILLIAMS PC
251 NORTH AVENUE WEST
2ND FLOOR
WESTFIELD
NJ
07090
US
|
Assignee: |
Philips-Universitat Marburg
|
Family ID: |
36650663 |
Appl. No.: |
11/342287 |
Filed: |
January 26, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60647106 |
Jan 26, 2005 |
|
|
|
Current U.S.
Class: |
257/12 ;
257/E21.112; 257/E21.126; 257/E21.127; 257/E29.09; 257/E33.008 |
Current CPC
Class: |
H01S 5/0218 20130101;
B82Y 20/00 20130101; H01L 21/02538 20130101; H01S 5/3434 20130101;
C30B 29/40 20130101; H01L 21/02381 20130101; H01L 21/02502
20130101; H01L 33/06 20130101; H01L 21/02505 20130101; H01S 5/021
20130101; H01L 29/201 20130101; H01S 5/183 20130101; H01L 33/32
20130101; H01S 5/323 20130101; H01L 21/0245 20130101; H01L 21/02461
20130101; H01L 21/0262 20130101; H01L 21/02392 20130101; H01S
5/34333 20130101; C30B 25/02 20130101; H01L 33/26 20130101 |
Class at
Publication: |
257/012 |
International
Class: |
H01L 29/06 20060101
H01L029/06; H01L 31/00 20060101 H01L031/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 26, 2005 |
DE |
102005004582.0 |
Claims
1. A monolithic integrated semiconductor structure comprising the
following layer structure: A) a carrier layer on the basis of doped
or undoped Si or GaP, B) as an option, a first current-conducting
layer composed of doped Si, doped GaP or doped (AlGa) P, C) as an
option, a first adaptation layer, and D) an optically active
element comprising a semiconductor layer formed from a III/V
semiconductor having the composition
Ga.sub.xIn.sub.yN.sub.aAs.sub.bP.sub.cSb.sub.d, wherein x=70-100
mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%,
c=0-39.5 mole-% and d=0-15 mole-%, wherein the total of x and y is
always 100 mole-%, wherein the total of a, b, c and d is always 100
mole-%, and wherein the ratio of the totals of x and y on the one
hand and of a to d on the other hand is substantially 1:1.
2. A semiconductor structure according to claim 1, comprising the
below layer structure following to the layer D): E) optionally a
second adaptation layer, and F) a second current-conducting layer
composed of doped Si, doped GaP or doped (AlGa)P.
3. A semiconductor structure according to claim 1 or 2, wherein the
layer B) is p-doped or n-doped.
4. A semiconductor structure according to one of claims 1 to 3,
wherein y=1 to 30 mole-%.
5. A semiconductor structure according to one of claims 1 to 4,
wherein c=1 to 32.0 mole-%.
6. A semiconductor structure according to one of claims 1 to 5,
wherein the semiconductor is a direct semiconductor.
7. A semiconductor structure according to one of claims 2 to 6,
wherein the layer F) is p-doped, if the layer B) is n-doped, and
wherein the layer F) is n-doped, if the layer B) is p-doped.
8. A semiconductor structure according to one of claims 1 to 7,
wherein the optically active element has a layer structure
(D1-D2-D3).sub.n, wherein the layer D2 is a quantum well layer of
the said semiconductor, wherein the layers D1 and D3 are barrier
layers, and wherein n=1-50, in particular 1-15.
9. A semiconductor structure according to claim 8, wherein
following one of the terminal layers D1 or D3, a barrier layer D4
is provided.
10. A semiconductor structure according to claim 8 or 9, wherein
the barrier layers are semiconductors having the composition
Ga.sub.pIn.sub.qN.sub.r--P.sub.sAs.sub.t, wherein p=85-100 mole-%,
q=0-15 mole-%, r=0-15 mole-%, s=60-100 mole-% and t=0-40 mole-%,
wherein the total of p and q is always 100 mole-%, wherein the
total of r, s and t is always 100 mole-%, wherein the ratio of the
totals of p and q on the one hand and of r to t on the other hand
is substantially 1:1, and wherein the barrier layer has a layer
thickness of preferably 5-50 nm
11. A semiconductor structure according to one of claims 1 to 10,
wherein the first and/or the second adaptation layers are
semiconductors having the composition
Ga.sub.pIn.sub.qN.sub.rP.sub.sAs.sub.t, wherein p=90-100 mole-%,
q=0-10 mole-%, r=0-10 mole-%, s=70-100 mole-% and t=0-30 mole-%,
wherein the total of p and q is always 100 mole-%, wherein the
total of r, s and t is always 100 mole-%, and wherein the ratio of
the totals of p and q on the one hand and of r to t on the other
hand is substantially 1:1, and wherein the adaptation layer has a
layer thickness of preferably 50-500 nm.
12. A semiconductor structure according to one of claims 1 to 11,
wherein a current-conducting layer and/or barrier layer disposed
between the carrier layer and the optically active element is at
the same time an adaptation layer.
13. A semiconductor structure according to one of claims 1 to 12,
wherein underneath and/or above the optically active element, at
least one optical waveguide layer is provided, which is optically
coupled to the optically active element.
14. A semiconductor structure according to one of claims 1 to 13,
wherein between the layers A) and D) and/or outside the layer F),
there is provided at least one periodic reflection structure.
15. A semiconductor structure according to one of claims 1 to 14,
wherein the optically active element has a fundamental emission
wavelength in the range of 700-1,100 nm.
16. A method for the production of a monolithic integrated
semiconductor structure according to one of claims 8 to 15, wherein
on a carrier layer A on the basis of doped or undoped Si or GaP,
optionally a first current-conducting layer B consisting of doped
Si, doped GaP or doped (AlGa)P is epitaxially grown, optionally a
first adaptation layer C is epitaxially grown, and a multi-layer
structure D, which forms an optically active element including a
semiconductor layer comprising a semiconductor according to one of
claims 1 to 6, is epitaxially grown.
17. A method according to claim 16, wherein on the optically active
element optionally a second adaptation layer E is epitaxially
grown, and on the optically active element or the second adaptation
layer a second current-conducting layer F consisting of doped Si or
doped GaP or doped (AlGa)P is epitaxially grown.
18. A method according to claim 16 or 17, wherein the layer B is
p-doped or n-doped.
19. A method according to claim 18, wherein the layer F) is
p-doped, if the layer B) is n-doped, and wherein the layer F) is
n-doped, if the layer B) is p-doped.
20. A method according to one of claims 16 to 19, wherein the
optical element is formed by epitaxial growth of layers D1, D2 and
D3, wherein the order of the epitaxial steps is performed such that
the layer structure is (D1-D2-D3).sub.n, wherein the layer D2 is a
quantum well layer of a semiconductor according to one of claims 1
to 4, wherein the layers D1 and D3 are barrier layers, and wherein
n=1-50, in particular 1-15.
21. A method according to claim 20, wherein following one of the
terminal layers D1 or D3, a barrier layer D4 is epitaxially
grown.
22. A method according to claim 20 or 21, wherein the barrier
layers are semiconductors having the composition
Ga.sub.pIn.sub.qN.sub.rP.sub.sAs.sub.t, wherein p=85-100 mole-%,
q=0-15 mole-%, r=0-15 mole-%, s=60-100 mole-% and t=0-40 mole-%,
wherein the total of p and q is always 100 mole-%, wherein the
total of r, s and t is always 100 mole-%, wherein the ratio of the
totals of p and q on the one hand and of r to t on the other hand
is substantially 1:1, and wherein the barrier layer has a layer
thickness of preferably 5-50 nm.
23. A method according to one of claims 16 to 22, wherein the first
and/or second adaptation layers are semiconductors having the
composition Ga.sub.pIn.sub.qN.sub.rP.sub.sAs.sub.t, wherein
p=90-100 mole-%, q=0-10 mole-%, r=0-10 mole-%, s=70-100 mole-% and
t=0-30 mole-%, wherein the total of p and q is always 100 mole-%,
wherein the total of r, s and t is always 100 mole-%, wherein the
ratio of the totals of p and q on the one hand and of r to t on the
other hand is substantially 1:1, and wherein the adaptation layer
has a layer thickness of preferably 50-500 nm.
24. A method according to one of claims 16 to 23, wherein a
current-conducting layer and/or barrier layer disposed between the
carrier layer and the optically active element is at the same time
an adaptation layer.
25. A method according to one of claims 16 to 24, wherein
underneath and/or above the optically active element, at least one
optical waveguide layer is provided, which is optically coupled to
the optically active element.
26. A method according to one of claims 16 to 25, wherein between
the layers A) and D) and/or outside the layer F), there is provided
at least one periodic reflection structure.
27. A method according to one of claims 16 to 26, wherein the
optically active element has a fundamental emission wavelength in
the range of 700-1,100 nm.
28. A III/V semiconductor having the composition
Ga.sub.xIn.sub.yN.sub.aAs.sub.bP.sub.cSb.sub.d, wherein x=70-100
mole-%, y=0-30 mole-%, a=0.5-15 mole-%, b=67.5-99.5 mole-%,
c=0-39.5 mole-% and d=0-15 mole-%, wherein the total of x and y is
always 100 mole-%, wherein the total of a, b, c and d is always 100
mole-%, and wherein the ratio of the totals of x and y on the one
hand and of a to d on the other hand is substantially 1:1.
29. A III/V semiconductor according to claim 28, wherein y=1 to 30
mole-%.
30. A III/V semiconductor according to claim 28 or 29, wherein
c=1-32.0 mole-%.
31. A III/V semiconductor according to one of claims 28 to 30,
wherein the semiconductor is a direct semiconductor.
32. A semiconductor layer comprising a semiconductor according to
one of claims 28 to 31, wherein the layer thickness of the
semiconductor layer is in the range from 1-50 nm, preferably 2-20
nm.
33. The use of a semiconductor according to one of claims 28 to 31
or of a semiconductor layer according to claim 32 for the
production of a luminescence diode, a VCSEL laser diode, a VECSEL
laser diode, a modulator structure or a detector structure.
34. A method for the production of a semiconductor layer according
to claim 33 comprising the following steps: a substrate on the
basis of doped or undoped Si or GaP is brought into a MOVPE
apparatus, optionally a surface of the substrate is provided in at
least one epitaxial coating step first with respectively at least
one adaptation layer, one barrier layer, one current-conducting
layer, one waveguide layer and/or one reflection structure, an
inert carrier gas is loaded with educts in defined concentrations,
the loaded carrier gas is conducted over the surface of the
substrate heated to a temperature in the range of 300.degree. C. to
700.degree. C. or on the surface of the uppermost layer on the
substrate for a defined duration of exposure, and the total
concentration of the educts and the duration of exposure are
adjusted to each other such that the semiconductor layer is
epitaxially formed with a given layer thickness on the surface of
the substrate or on the surface of the uppermost layer on the
substrate.
35. A method according to claim 34, wherein the following educts
are used: C1-C5 trialkylgallium, in particular triethylgallium
(Ga(C.sub.2H.sub.5).sub.3) and/or trimethylgallium
(Ga(CH.sub.3).sub.3), as a Ga educt, optionally C1-C5
trialkylindium, in particular trimethylindium (In(CH.sub.3).sub.3),
as an In educt, ammonia (NH.sub.3), mono(C1-C8)alkylhydrazine, in
particular tertiarybutylhydrazine
(t-(C.sub.4H.sub.9)--NH--NH.sub.2), and/or
1,1-di(C1-C5)alkylhydrazine, in particular 1,1-dimethylhydrazine
((CH.sub.3).sub.2--N--NH.sub.2), as an N educt, arsine (AsH.sub.3)
and/or C1-C5 alkylarsine, in particular tertiarybutylarsine
(t-(C.sub.4H.sub.9)--AsH.sub.2), as an As educt, phosphine
(PH.sub.3) and/or C1-C5 alkylphosphine, in particular
tertiarybutylphosphine (t-(C.sub.4H.sub.9)--PH.sub.2), as a P
educt, and optionally C1-C5 trialkylantimony, in particular
trimethylantimony (Sb(C.sub.2H.sub.5).sub.3) and/or
triethylantimony (Sb(CH.sub.3).sub.3), as an Sb educt, wherein the
C3-C5 alkyl groups may be linear or branched.
36. A method according to claim 35, wherein the educts are employed
in the following molar ratios: As educt/group III educts 5-300, P
educt/group-III educts 0-500, N educt/As educt 0.1-10, optionally
Sb educt/As educt 0-1, wherein the surface temperature of the
substrate is adjusted to the range from 500.degree. C. to
630.degree. C., wherein the total pressure of carrier gas and
educts is adjusted to the range from 10 to 200 hPa, wherein the
ratio of the total of the partial pressures of the educts to the
partial pressure of the carrier gas is between 0.005 and 0.1, and
wherein the deposition rate is 0.1 to 10 .mu.m/h.
37. A semiconductor layer obtainable with a method according to one
of claims 34 to 36.
38. An integrated monolithic semiconductor structure obtainable
with a method according to one of claims 16 to 26.
Description
FIELD OF THE INVENTION
[0001] The invention relates to a new III/V semiconductor, a
semiconductor layer consisting of such a semiconductor, a
monolithically integrated semiconductor structure comprising such a
semiconductor layer, the uses of such a semiconductor or of such a
semiconductor layer, and a method for the production of such a
semiconductor layer.
BACKGROUND OF THE INVENTION AND PRIOR ART
[0002] In the field of computer technology, there is a continuously
growing demand for higher processing and signal conduction
capacities in conjunction with a high reliability and flexibility.
In the past, the chip technology has made a rapid progress with
regard to integration density and working speeds or cycle
frequencies. With this trend further advancing, problems are coming
up for the connection of fast chips. Critical aspects in
conjunction with high-speed connections are reliability, cost,
on-chip driver size and performance, crosstalk, signal distortions
and lack of flexibility in the chip design. Connections between
chips by using optoelectronic components and optical waveguides are
a solution for many connection problems. Optical connections have
an extremely high bandwidth and are comparatively insensitive
against crosstalk and other interferences. By using these
properties of optical connections, it may become possible to
connect high-speed chips with each other by optical channels and to
achieve a considerable improvement with regard to connection
density, current consumption, interferences and crosstalk.
[0003] Usually high-integrated circuits are based on the Si
technology. Silicium is however an indirect semiconductor, and the
production of efficient optoelectronic components using the Si
technology is consequently hardly possible. Efficient
optoelectronic components can however be produced by using the
technology of the III/V semiconductors, for instance the GaAs
technology, since these semiconductors are often direct
semiconductors consequently emitting and absorbing light with a
high efficiency.
[0004] For producing integrated circuits, commonly the epitaxial
process is employed. If now contacts between layers on the basis of
the Si technology and layers on the basis of the technology of the
III/V semiconductor are to be made, it is problematic that the
lattice constants of the respective materials are different (this
also applies to GaP substrates instead of Si substrates). This has
as a consequence that during the epitaxial growth of III/V
semiconductors on Si (or GaP) substrates, dislocations are created.
Such dislocations however disturb the function of the complete
semiconductor structure to a substantial degree, the more since the
functional layer thicknesses are today in the order of atomic
dimensions. In the case of high layer thicknesses, the difference
of the lattice constants even leads to bends of the substrate. The
reason for this is basically that with high deposition temperatures
an epitaxial growth of III/V semiconductors takes place on Si or
GaP semiconductors, however the generation of dislocations begins
already at less high deposition temperatures. If then the
semiconductor structure cools down to ambient temperature, the
differences of the lattice constants caused by the different
thermal expansion coefficients will lead to the above stresses and
dislocations.
[0005] For eliminating the above problems, various approaches
exist. In the document EP 0380815 B1 there is described that GaAs
layers can be deposited on a Si substrate and form defined
microcracks at predetermined positions, thus dislocations of the Si
substrate being avoided, at least however reduced. This technology
is however not suitable for high-integrated circuits because of the
lacking controllability of microcracks in atomic scales.
[0006] The document EP 0297483 describes a hybrid integrated
semiconductor structure, wherein on a Si substrate an integrated
circuit on the basis of the Si technology is applied. Further, an
optically active element in GaAs technology is provided on the Si
substrate. An electrical connection between the integrated circuit
and the optically active element is however not established by a
direct contact or by the Si substrate, but rather by an electrical
wire connection. This technology, too, is not suitable for
applications in high-integrated circuits.
[0007] From the document DE 10355357 it is known, for layer
structures with optically active elements on the basis of III/V
semiconductors, to compensate dislocations caused by lattice
constants for instance by adaptation layers subjected to tensile
stress. By the insofar known measures, a modeling of electronic
properties is also possible, and thus emission wavelengths not
accessible up to now become accessible.
[0008] From the document US 2004/0135136 A1, a multitude of
different III/V semiconductors are known in the art, and they are
always layers, which are not suitable for application on a Si
substrate. Corresponding considerations apply to the documents EP
1257026 A2, U.S. Pat. No. 6,233,264 B1, US 2004/0084667 A2, Merz et
al., IEE Proc.-Optoelectron. 151(5):346-351 (2004), U.S. Pat. No.
6,072,196, EP 1553670 A2, U.S. Pat. No. 5,825,796, Ishizuka et al.,
Journal of Crystal Growth 272:760-764 (2004) and US 2004/0161009
A1.
[0009] In the document EP 0896406 A2 there are described layers of
optically active III/V semiconductors on GaP or Si substrates (and
others), and these layers contain exclusively In as the III
component. In fact, such layers are only suitable for InP
substrates and form undesirably many dislocations and faults on Si
or GaP substrates. The document U.S. Pat. No. 5,937,274 describes
in a very general manner different layers on different
substrates.
[0010] As a result, there continues being a need in particular for
the field of high-integrated circuits to connect subassemblies or
layer sequences on the basis of the Si technology and on the basis
of the III/V semiconductor monolithically with each other.
TECHNICAL OBJECT OF THE INVENTION
[0011] It is a technical object of the invention to propose means
for providing optically active elements on the basis of the III/V
semiconductors on substrates of the Si technology or GaP
technology, wherein the conduction of electrical signals of the Si
based or GaP-based subassemblies to and from the optically active
elements is integrally formed, i.e. by contact of layers, and that
practically free from dislocations forming nonradiative
recombination centers in the III/V semiconductor or at the border
face thereof to the layer underneath. It is further a technical
object of the invention to propose stable luminescence and laser
components on Si substrates or GaP substrates, which are directly
contacted, i.e. by layer contact. It is another technical object of
the invention to provide a monolithically integrated semiconductor
structure, which emits directly, i.e. without wirebound connection
lines, data currents from a Si-technology based processor circuitry
as an optical signal. Further, it is an object of the invention to
propose a monolithically integrated semiconductor structure, by
means of which emitted optical signals can also be modulated and/or
detected.
BASICS OF THE INVENTION AND EMBODIMENTS
[0012] For achieving this technical object, the invention teaches
monolithically integrated semiconductor structures according to
claim 1 with Si or GaP substrates and a III/V semiconductor having
the composition Ga.sub.xIn.sub.yN.sub.aAs.sub.bP.sub.cSb.sub.d,
wherein x=70-100 mole-%, y=0-30 mole-%, a=0.5-15 mole-%,
b=67.5-99.5 mole-%, c=0-32.0 mole-% and d=0-15 mole-%, wherein the
total of x and y is always 100 mole-%, wherein the total of a, b, c
and d is always 100 mole-%, and wherein the ratio of the totals of
x and y on the one hand and of a to d on the other hand is
substantially 1:1. Preferably, y=1-30 mole-%, and c=1-32.0 mole-%,
and such a semiconductor per se.
[0013] In the case of a P-free system, In and/or Sb should be
comprised, since these elements minimize, like P, the local
distortion fields caused by the N-incorporation.
[0014] III/V semiconductors having the following compositions are
particularly preferred: [0015] a) x=70-100 mole-%, y=0-30 mole-%,
a=0.5-10 mole-%, b=70-98.5 mole-%, c=1-29.5 mole-%, or [0016] b)
x=85-99 mole-%, y=1-15 mole-%, a=0.5-10 mole-%, b=70-98.5 mole-%,
c=1-29.5 mole-%, or [0017] c) x=85-99 mole-%, y=1-15 mole-%,
a=0.5-10 mole-%, b=70-98.5 mole-%, c=0-32 mole-% and d=1-10
mole-%.
[0018] In particular, x=>70-100 mole-%, a=>1.3 or >1.7
mole-% (optionally in connection with y>0 or 1 mole-%), c=0-32
mole-% and/or b=60-99.5 mole-%. Preferred is also c= or between 4-8
mole-%. Preferred is also a=4 or 5.5-11 mole-%.
[0019] The semiconductor class according to the invention of the
mixed crystal system GaInNAsPSb is characterized, on the one hand,
by that because of the composition, presumably of the addition of
nitrogen and/phosphorus, layer sequences adapted to the lattice or
compressively stressed can be produced on GaP and/or Si substrates,
without causing dislocations. On the other hand, beginning from a
nitrogen concentration of >0.5 mole-% in conjunction with the
phosphorus content, an interaction of the electronic levels caused
by the incorporation of nitrogen with the conduction band states of
the nitrogen-free mixed crystal system at the .GAMMA. point will
occur, which will lead to an effective red shift of the fundamental
energy gap at the .GAMMA. point and thus strengthen the character
as a direct semiconductor of the GaInNAsPSb material system. For
instance, for a=1-10 mole-%, b=60-95 mole-% and c=2-15 mole-%,
preferably a=3-5 mole-%, b=85-95 mole-% and c=4-8 mole-%, there
will result a fundamental energy gap of distinctly less than 1.8
eV, even down to 1.4 eV and smaller. This makes clear the drastic
influence of the energy gap by the composition of this
semiconductor system according to the invention.
[0020] In detail, the invention relates to a monolithically
integrated semiconductor structure comprising the following layer
structure:
[0021] A) a carrier layer on the basis of doped or undoped Si or
GaP,
[0022] B) as an option, a first current-conducting layer composed
of doped Si, doped GaP or doped (AlGa)P,
[0023] C) as an option, a first adaptation layer, and
[0024] D) an optically active element comprising a semiconductor
layer according to the invention.
[0025] To the layer D), the below layers may follow: E) optionally
a second adaptation layer and F) a second current-conducting layer
composed of doped Si or doped GaP or doped (AlGa)P. In case of the
(AlGa)P, the share of Al may be 20-100 mole-%, and the total of the
shares of Al and Ga is always 100 mole-%. The layer B) may be p or
n-doped. In case that the layer F) is present, the layer F) may be
p-doped, if layer B) is n-doped, and vice versa.
[0026] Normally, the optical element will have a layer structure
(D1-D2-D3).sub.n, wherein the layer D2 is a quantum well layer of a
semiconductor according to the invention, wherein the layers D1 and
D3 are barrier layers, and wherein n=1-15. By such an optically
active element, luminescence diodes as well as laser diodes can be
built up. Following one of the terminal layers D1 or D3, a barrier
layer D4 may be provided. It may be recommended that the barrier
layers are semiconductors having the composition
Ga.sub.p--In.sub.qN.sub.rP.sub.sAs.sub.t, wherein p=85-100 mole-%,
q=0-15 mole-%, r=0-15 mole-%, s=60-100 mole-% and t=0-40 mole-%,
wherein the total of p and q is always 100 mole-%, wherein the
total of r, s and t is always 100 mole-%, and wherein the ratio of
the totals of p and q on the one hand and of r to t on the other
hand is substantially 1:1, and wherein the barrier layer has a
layer thickness of preferably 5-50 nm. Preferred ranges are:
p=90-100 mole-%, q=0-10 mole-%, r=0-10 mole-%, s=70-100 mole-% and
t=0-30 mole-%. For the layer thickness, a range of 2-20 nm is
preferred. An adaptation layer may be a semiconductor having the
composition Ga.sub.pIn.sub.qN.sub.rP.sub.sAs.sub.t, wherein
p=90-100 mole-%, q=0-10 mole-%, r=0-10 mole-%, s=70-100 mole-% and
t=0-30 mole-%, wherein the total of p and q is always 100 mole-%,
wherein the total of r, s and t is always 100 mole-%, and wherein
the ratio of the totals of p and q on the one hand and of r to t on
the other hand is substantially 1:1, and wherein the adaptation
layer has a layer thickness of preferably 50-500 nm.
[0027] In the monolithically integrated semiconductor structure
according to the invention, a current-conducting layer and/or
barrier layer disposed between the carrier layer and the optically
active element may be at the same time an adaptation layer.
[0028] Underneath and/or above the optically active element, at
least one optical waveguide layer may be provided, which is
optically coupled to the optically active element. In this way,
data currents can be guided as optical signals from the emitting
optically active element to an optical receiver at a different
place on the carrier. It is understood that other elements may
additionally or alternatively be used for conducting optical
signals, such as fibers or the like.
[0029] A luminescence diode or also a vertically emitting laser
diode may be produced by that between the layers A) and D) and/or
outside the layer F), there is provided at least one periodic
reflection structure.
[0030] Preferably, the optically active element has a fundamental
emission wavelength in the range of 700-1,100 nm.
[0031] The invention further relates to the use of a semiconductor
according to the invention or a semiconductor layer according to
the invention for the production of a luminescence diode (LED), a
VCSEL (vertical cavity surface emitting laser) laser diode or a
VECSEL (vertical external cavity surface emitting laser) laser
diode and a modulator or a detector structure.
[0032] Finally, the invention relates to a method for the
production of a semiconductor layer according to the invention
comprising the following steps: a substrate on the basis of doped
or undoped Si or GaP is brought into a MOVPE (metal-organic vapor
phase epitaxy) apparatus, optionally a surface of the substrate is
provided in at least one epitaxial coating step first with
respectively at least one adaptation layer, one barrier layer, one
current-conducting layer, one waveguide layer and/or one reflection
structure, a carrier gas is loaded with educts in defined
concentrations, the loaded carrier gas is conducted over the
surface of the substrate heated to a temperature in the range of
300.degree. C. to 700.degree. C. or on the surface of the uppermost
layer on the substrate for a defined duration of exposure, and the
total concentration of the educts and the duration of exposure are
adjusted to each other such that the semiconductor layer is
epitaxially formed with a given layer thickness on the surface of
the substrate or on the surface of the uppermost layer on the
substrate.
[0033] Preferably, the following educts are used for the MOVPE
technology: C1-C5 trialkylgallium, in particular triethylgallium
(Ga(C.sub.2H.sub.5).sub.3) and/or trimethylgallium
(Ga(CH.sub.3).sub.3), as a Ga educt, C1-C5 trialkylindium, in
particular trimethylindium (In(CH.sub.3).sub.3), as an In educt,
ammonia (NH.sub.3), mono(C1-C8)alkylhydrazine, in particular
tertiarybutylhydrazine (t-(C.sub.4H.sub.9)--NH--NH.sub.2), and/or
1,1-di(C1-C5)alkylhydrazine, in particular 1,1-di-methylhydrazine
((CH.sub.3).sub.2--N--NH.sub.2), as an N educt, arsine (AsH.sub.3)
and/or C1-C5 alkylarsine, in particular tertiarybutylarsine
(t-(C.sub.4H.sub.9)--AsH.sub.2), as an As educt, phosphine
(PH.sub.3) and/or C1-C5 alkylphosphine, in particular
tertiarybutylphosphine (t-(C.sub.4H.sub.9)--PH.sub.2), as a P
educt, and C1-C5 trialkylantimony, in particular trimethylantimony
((CH.sub.3).sub.3Sb) and/or triethylantimony
((C.sub.2H.sub.5).sub.3Sb), as an Sb educt, wherein the C3-C5 alkyl
groups may be linear or branched.
[0034] Preferably, the educts are employed in the following molar
ratios: As educt/group III educts 5-300, P educt/group-III educts
0-500, N educt/As educt 0.1-10, optionally Sb educt/As educt 0-1,
wherein the surface temperature of the substrate is adjusted to the
range from 500.degree. C. to 630.degree. C., wherein the total
pressure of carrier gas and educts is adjusted to the range from 10
to 1,000 hPa or to 200 hPa, wherein the ratio of the total of the
partial pressure of all educts to the partial pressure of the
carrier gas is between 0.005 and 0.1, and wherein the deposition
rate is 0.1 to 10 .mu.m/h. In particular the following ratios may
be employed: As educt/group III educts 10-100, for instance 10-30,
P educt/group III educts 1-100, for instance 1-10, N educt/As educt
1-10, for instance 3-8. The surface temperature may preferably be
in the range from 500.degree. C. to 650.degree. C., in particular
550.degree. C. to 600.degree. C. The total pressure of carrier gas
and educts may be in the range from 20 to 100 hPa. The ratio of the
partial pressure of all educts to the partial pressure of the
carrier gas may be in the range from 0.01 to 0.05. The deposition
rate may be between 0.1 and 5 .mu.m/h, in particular 0.5 and 3
.mu.m/h.
[0035] In principle, the precise concentrations of the educts
depend on the thermal decomposition properties of the respective
educts in the MOVPE process. The growth speed of the layer is
determined by the concentrations of the group III educts. On the
basis of various decomposition properties of the Ga and if
applicable In educts, known to the man skilled in the art,
depending on the selected deposition temperature (surface
temperature of the substrate), suitable educt concentrations are
adjusted, which will lead to the desired group III concentrations
of the respective elements in the semiconductor layer according to
the invention. Because of the known temperature-dependent
incongruent vaporization of the group V educts or species of the
growth surface of the III/V semiconductors, the respective group V
educt concentrations in the MOVPE deposition should carefully be
adjusted to the desired concentrations in the semiconductor layer
according to the invention as a function of the selected deposition
temperature in the excess. This is easily achievable for the man
skilled in the art. For higher deposition temperatures or educts
that cannot easily be decomposed, if applicable, higher V/III
ratios, but also higher N/As ratios than mentioned above have to be
selected. For lower deposition temperatures, correspondingly the
reversed behavior applies.
[0036] Alternatively to MOVPE, of course other epitaxial methods
can also be employed, such as MBE (molecular beam epitaxy), also
under inclusion of gas sources in particular for the group V
components (gas source MBE, GS-MBE), CBE (chemical beam epitaxy) or
also MOMBE (metal-organic molecular beam epitaxy). These methods
can be carried out by means of the usual and per se known epitaxy
apparatuses, and the respectively suitable and per se known educts
and sources have to be employed. The respective conditions can
easily be adjusted by the man skilled in the art.
[0037] A method for the production of a semiconductor structure
according to the invention is described in the claims 22 to 33.
DEFINITIONS
[0038] A direct semiconductor is a semiconductor, where in the band
structure the valence band maximum and the conduction band minimum
are located opposite to each other at the same crystal pulse
vector. In contrast thereto, for an indirect semiconductor, the
valence band maximum and the conduction band minimum are not
located opposite to each other at the same crystal pulse vector,
but are located at different crystal pulse vectors.
[0039] A monolithic semiconductor structure is a structure, wherein
an electric contact of different functional semiconductor sections
occurs by (preferably epitaxial) layers immediately connected with
each other. In contrast thereto, in a hybrid semiconductor
structure, an electrical contact of different functional
semiconductor sections is achieved by auxiliary connections, such
as for instance wire connections.
[0040] In an n-doped semiconductor, the electrical conduction is
achieved by electrons because of donor atoms having extra valence
electrons. For the n-doping of silicon, there can for instance be
used nitrogen, phosphorus, arsenic and antimony. For the n-doping
of GaP or (AlGa)P semiconductors, for instance silicon and
tellurium can be used. In a p-doped semiconductor, the electrical
conduction occurs by holes because of the incorporation of acceptor
atoms. Acceptors for silicon are boron, aluminum, gallium and
indium. For GaP or (AlGa)P can be used for instance magnesium, zinc
or carbon as acceptors.
[0041] A semiconductor is typically undoped, if the concentration
of donor or acceptor atoms is below 10.sup.5 cm.sup.-3. Doped
semiconductors usually have concentrations above 10.sup.15
cm.sup.-3.
[0042] A current-conducting layer consists of a semiconductor doped
to such an extent that a conductivity being sufficient for
providing a defined electrical power is given.
[0043] III/V semiconductors according to the invention are
typically compressively stressed. For the purpose of the lattice
adaptation and modeling of the band structure, barrier layers are
provided, which may be tensile-stressed. Thereby, a compensation of
the stress of the III/V semiconductor is achieved.
[0044] An optically active element according to the invention
transforms energy into light radiation and emits the latter,
modulates the light radiation and/or absorbs light radiation and
transforms it into an electrical signal. For laser diodes, the
number of layer periods n is typically 1-5. For luminescence
diodes, n may however be up to 15. For modulators or detector
structures, n may be substantially higher and have values of up to
50 and more.
[0045] An adaptation layer serves for the compensation of stresses
of a semiconductor layer or a semiconductor structure according to
the invention on the basis of III/V semiconductors on Si or GaP
substrates. Adaptation layers do not contribute to light
emission.
[0046] A quantum well layer is also called a quantum film. By the
two-side contact with a barrier layer, the movements of the charge
carriers are confined, and the charge carriers are in the case of
epitaxial layers in a one-dimensional inclusion (movements mainly
in two spatial dimensions). Optically active elements having the
layer structure according to the invention are also called multiple
quantum well (MQW) structures. By epitaxial stresses between the
quantum well layers and the barrier layers, the electronic
properties with regard to the fundamental band gap can be
influenced.
[0047] Optical waveguide layers are widely known from prior art. As
an example only, reference is made to the document "Semiconductor
Optoelectronics: Physics and Technology", J. Singh, McGraw-Hill
Inc., New York (1995).
[0048] Periodic reflection structures are dielectric and/or
epitaxial (.lamda./4) multi-layer mirrors. They are so-called
distributed Bragg reflectors (DBR), reflecting the light emitted by
the optically active element and representing thus the
high-reflective end mirror in the laser resonator. With regard
thereto, reference is made to the document "Vertical-cavity
Surface-emitting Lasers: Design, Fabrication, Characterization and
Application", Eds.: C. Wilmsen et al., Cambridge University Press,
Cambridge (1999). Such periodic reflection structures may also be p
or n-doped for the purpose of current conduction. Then these
periodic reflection structures accept at the same time the function
of a current-conducting layer.
[0049] III/V semiconductors according to the invention are
typically metastable at room temperature or at operating
temperature. This means that because of the thermodynamics of the
situation at the respective temperature, there should not exist a
stable, homogeneous phase, but that a decay into at least two
different phases should occur. This decay is however kinetically
inhibited. For overcoming the kinetic inhibition, a high
temperature would be required to act, and for this reason such
metastable phases can only be epitaxially deposited at
comparatively low substrate temperatures, typically below
700.degree. C. After the deposition at reduced temperatures, an
annealing step of the semiconductor layer according to the
invention may be employed in the temperature range of typically
700.degree. C. to 850.degree. C. for the reduction of nonradiative
recombination centers. There can be performed equilibrium annealing
steps, for instance immediately in a MOVPE reactor, as well as
non-equilibrium methods, such as rapid thermal annealing (RTA). The
respective annealing temperatures are to be selected such that no
decay into different phases is observed.
[0050] The carrier layer used according to the invention is
typically a GaP or Si single crystal. It is understood that the
surface of such a single crystal may be purified in a conventional
manner and prepared for the epitaxial deposition. In this context,
reference is made to the document A. Ishizaka et al., Electrochem.
Soc. 33:666 (1986).
[0051] The term "substantially 1:1" comprises the range of
0.8:1.2-1.2:0.8, in particular 0.9:1.1-1.1:0.9, preferably
0.95:1.05-1.05:0.95, and of course also exactly 1:1.
EMBODIMENTS OF THE INVENTION
EXAMPLE 1
Production of a Semiconductor Layer According to the Invention
[0052] After the usual pretreatment, a Si wafer (manufacturer:
Wacker, Virginia Semiconductor) is placed in a MOVPE apparatus
(type AIX200-GFR, manufacturer Aixtron). First, epitaxial layers
are deposited in a conventional way on the Si wafer, as described
in more detail in the following Examples. On the thus obtained
surface, then a layer of the III/V semiconductor according to the
invention is deposited. For this purpose, an inert gas flow
(H.sub.2) is loaded with the various educts. The following educts
are used: trimethylgallium or triethylgallium, trialkylindium (as
far as applicable), 1,1-dimethylhydrazine, tertiarybutylarsine,
tertiarybutylphosphine and trimethylantimony (as far as
applicable). All these educts are for instance available from Akzo
Nobel HPMO.
[0053] For the production of a semiconductor layer according to the
invention having an exemplary composition
Ga(N.sub.0.037As.sub.0.883P.sub.0.08), the following conditions
were selected with a total reactor pressure of 50 hPa: partial
pressures TEGa (triethylgallium) 0.007 hPa, TBAs
(tertiarybutylarsine) 0.142 hPa, TBP (tertiarybutylphosphine) 0.035
hPa and UDMHy (dimethylhydrazine) 0.85 hPa. Therefrom result the
following ratios: ratio As/Ga 20, ratio P/Ga 5 and ratio N/As
6.
[0054] The loaded H.sub.2 carrier gas having a total pressure of 50
hPa is then conducted for 22 s over the surface of the coated
substrate heated to 575.degree. C. A layer according to the
invention having a thickness of 7.0 nm is obtained. After
expiration of the exposure period for the semiconductor layer
according to the invention, the MOVPE system is adjusted to the
deposition conditions of the respective barrier or adaptation
layer.
EXAMPLE 2
Production of an Optically Active Element
[0055] In the MOVPE apparatus of Example 1, first the layers
described in the following examples are epitaxially grown on a Si
wafer in a conventional manner. Thereafter, alternatingly a barrier
layer and a quantum well layer each are deposited, and the
deposition of a barrier layer represents the completion. This
periodic layer structure comprises in total 5 quantum well layers.
As the quantum well layer, a layer according to Example 1 is used.
All quantum well layers have the same composition. As the barrier
layer, GaP is used. All barrier layers have the same composition.
The quantum well layers have thicknesses between 2 and 20 nm each.
The barrier layers have thicknesses between 5 and 500 nm.
EXAMPLE 3
Monolithic Integrated Semiconductor Structure According to the
Invention
[0056] A monolithic integrated semiconductor structure according to
the invention is shown in FIG. 1. For the production, the layers
B1) to F2) are subsequently epitaxially grown on a Si wafer A. The
layer B1) is p-doped GaP. Zinc or magnesium is used as doping
element. The doping concentration is typically 110.sup.18
cm.sup.-3. The layer thickness of the layer B1) is 5-300 nm. The
layer B1) is a contact layer, which is also current conducting.
Thereafter, the layer B2) is produced, which is formed of p-doped
(AlGa)P. Doping is made with zinc or magnesium in a doping
concentration of typically 110.sup.18 cm.sup.-3. The aluminum
concentration is more than 15 mole-%, referred to the total amount
of group III elements. A typical value is in the range of 15-45
mole-%. Alternatively, p-doped (AlGa)(NP) can also be used, and
with regard to doping and aluminum content the above applies. The
share of nitrogen referred to the total amount of group V elements,
is 0-4 mole-%. The layer thickness is between 500 and 1,500 nm. The
layer B2) is a waveguide layer, which acts at the same time as a
current-conducting layer. The layer C) disposed thereupon is
composed of undoped GaP. The layer thickness is 50-100 nm. It is a
separate confinement heterostructure similar to a barrier layer.
Further, the layer C) acts as an adaptation layer. For better
visibility, the optically active element D) disposed thereupon is
shown as a single layer. In fact, the layer D) is a layer structure
according to Example 2. The layer E) corresponds to the layer C).
Alternatively, both layers can also be adapted as Ga(NP),
(GaIn)(NP) or (GaIn)(NaSP) layers. The nitrogen share referred to
the group V elements may be 0-10 mole-%. In the case of the latter
layer, the share of In referred to the total amount of group III
elements may be 0-15 mole-%. The layer F1) corresponds to the layer
B2), and the layer F2) corresponds to the layer B1), with the
difference that the layers F1) and F2) are n-doped. As the doping
element, tellurium with a doping concentration of typically
210.sup.18 cm.sup.-3 is employed. The layer thicknesses of the
layers E), F1) and F2) correspond to the layer thicknesses of the
layers C), B2) and B1) (in a reflection-symmetric order with regard
to the optically active element).
[0057] For improving the degree of output coupling, for
luminescence diodes as optically active elements, in addition
(AlGa)/P/(AlGa)/P periodic reflection structures (DBR structures)
having different aluminum contents can be incorporated in the
current-conducting layer located under the optically active
element. The aluminum share of successive layers is different and
is, referred to the total amount of group III elements, 0-60 mole-%
or 40-100 mole-%, resp. Alternatively, (AlGa)(NP) individual layers
may also be used for the compensation of stress of these DBR
structures, and the Al contents are to be selected as above, and
the N contents from 0-4 mole-%, referred to the total amount of
group V elements.
[0058] For surface emitting laser diodes (VCSEL) as optically
active elements, the optically active element is enclosed from
below as well as from above by a reflection structure of the above
type. For current supply, either these two DBR mirror structures
may be n-doped or p-doped, or additionally so-called intra cavity
current contacts are introduced in the overall structure, said
contacts permitting to produce the two DBR mirrors in an undoped
condition.
EXAMPLE 4
Fundamental Energy Gap of a Semiconductor According to the
Invention
[0059] A semiconductor layer produced according to Example 1 with 4
mole-% nitrogen, 90 mole-% arsenic and 6 mole-% phosphorus,
referred to the total amount of group V elements, was investigated
by means of the photoluminescence excitation spectroscopy. The
result is shown in FIG. 2. The fundamental energy gap is approx.
1.4 eV. This value is clearly lower than the value of 1.8 eV
modeled without the nitrogen interaction and shows the drastic
influence of the energy gap by the incorporation of nitrogen in
coordination with the further shares of other components in the
semiconductor system according to the invention.
EXAMPLE 5
Dislocation-Free Structure of Optically Active Elements According
to the Invention
[0060] An optically active element produced according to Example 2
was investigated by means of the high-resolution x-ray diffraction
(HR-XRD) and of the transmission electron microscopy (TEM).
[0061] FIG. 3 shows an experimental HR-XRD profile (FIG. 3 top) in
comparison with a theoretical profile according to the dynamic
x-ray diffraction theory (FIG. 3 bottom). The observed sharpness of
the individual diffraction reflexes and the nearly perfect match of
the experimental and theoretical diffraction profiles confirm the
outstanding structural layer quality over a large area without
generation of dislocations.
[0062] FIG. 4 shows a TEM dark field image. There can be seen
pentanary layers according to the invention as dark layers. The
lighter layers are Ga(NP) barrier layers. All three layers are
clearly resolved, and there cannot be seen any large-area defects
in the crystalline structure. In the high-resolution TEM image of
FIG. 5, there are nearly atomically abrupt border faces at the
transition of the (dark) pentanary layer according to the invention
to the barrier layer, said border faces being free from
dislocations and the like.
EXAMPLE 6
Semiconductors with a Particularly Low Fundamental Energy Gap
[0063] Different semiconductor layers produced analogously to
Example, said layers however containing nitrogen in the range of
5.5 to 11 mole-% (as always, referred to the total amount of group
V elements), show in the investigation by means of
photoluminescence spectroscopy at 20.degree. C. a fundamental,
direct energy gap of less than 1.2 eV, even less than 1.1 eV, which
is below the energy gap of silicon (1.124 eV). Semiconductor layers
having an energy gap below that of silicon in particular for the
production of luminescence and laser diodes, which are integrated
with Si/SiO.sub.2-based waveguide structures. In particular for
these emission energies, there will namely be no absorption and
thus attenuation of the light signal in the waveguide
structure.
* * * * *