U.S. patent application number 11/468543 was filed with the patent office on 2006-12-28 for structure and method for collar self-aligned to buried plate.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens.
Application Number | 20060292789 11/468543 |
Document ID | / |
Family ID | 35481178 |
Filed Date | 2006-12-28 |
United States Patent
Application |
20060292789 |
Kind Code |
A1 |
Cheng; Kangguo ; et
al. |
December 28, 2006 |
STRUCTURE AND METHOD FOR COLLAR SELF-ALIGNED TO BURIED PLATE
Abstract
A structure and method are provided for forming a collar
surrounding a portion of a trench in a semiconductor substrate, the
collar having a lower edge self-aligned to a top edge of a buried
plate disposed adjacent to a lower portion of the trench.
Inventors: |
Cheng; Kangguo; (Beacon,
NY) ; Divakaruni; Ramachandra; (Ossining, NY)
; Radens; Carl J.; (LaGrangeville, NY) |
Correspondence
Address: |
INTERNATIONAL BUSINESS MACHINES CORPORATION;DEPT. 18G
BLDG. 300-482
2070 ROUTE 52
HOPEWELL JUNCTION
NY
12533
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
|
Family ID: |
35481178 |
Appl. No.: |
11/468543 |
Filed: |
August 30, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10710061 |
Jun 16, 2004 |
|
|
|
11468543 |
Aug 30, 2006 |
|
|
|
Current U.S.
Class: |
438/243 ;
257/296; 257/E21.232; 257/E21.652; 257/E21.653 |
Current CPC
Class: |
H01L 21/3081 20130101;
H01L 27/10864 20130101; H01L 27/10867 20130101; H01L 27/1087
20130101 |
Class at
Publication: |
438/243 ;
257/296 |
International
Class: |
H01L 21/8242 20060101
H01L021/8242; H01L 29/94 20060101 H01L029/94 |
Claims
1-15. (canceled)
16. A structure including a capacitor formed along a sidewall of a
trench in a semiconductor substrate, the structure including a
collar surrounding a middle portion of the trench, the collar
having a lower edge self-aligned to a top edge of a buried plate
disposed adjacent to a lower portion of the trench.
17. A structure as claimed in claim 16, wherein the collar consists
essentially of an oxide.
18. A structure as claimed in claim 17, wherein the structure
further includes a transistor having a channel region formed in the
semiconductor substrate, the transistor having a conductive
connection to the capacitor.
19. A structure as claimed in claim 18, wherein the channel region
of the transistor extends vertically along a sidewall of the trench
above the collar.
20. A structure as claimed in claim 17, wherein the buried plate is
doped with arsenic.
21. A structure formed inside a semiconductor substrate, said
structure comprising: a trench; a capacitor formed along a sidewall
of said trench; and a collar surrounding a middle portion of said
trench, said collar having a lower edge, said lower edge being
self-aligned to a top edge of a buried plate disposed adjacent to a
lower portion of said trench.
22. The structure according to claim 21, wherein said collar
consists essentially of an oxide.
23. The structure according to claim 22, further comprising a
transistor having a channel region formed in the semiconductor
substrate, the transistor having a conductive connection to the
capacitor.
24. The structure according to claim 23, wherein the channel region
of the transistor extends vertically along a sidewall of the trench
above the collar.
25. The structure according to claim 22, wherein the buried plate
is doped with arsenic.
26. A semiconductor device formed in a substrate, said
semiconductor device comprising: a trench filled at least partially
with a conductive material; a capacitor formed around a lower
portion of said trench; and a collar formed above said lower
portion of said trench, said collar having a lower edge, said lower
edge being self-aligned to a top edge of a buried plate disposed
adjacent to said lower portion of said trench.
27. The semiconductor device according to claim 26, wherein said
buried plate is doped with arsenic.
28. The semiconductor device according to claim 27, wherein said
capacitor comprises said buried plate, said conductive material
filling said trench, and a layer of dielectric material being
disposed between said buried plate and said conductive
material.
29. The semiconductor device according to claim 26, wherein said
collar consists essentially of an oxide.
30. The semiconductor device according to claim 26, further
comprising a transistor having a channel region formed in the
semiconductor substrate, said transistor having a conductive
connection to the capacitor.
31. The semiconductor device according to claim 30, wherein said
channel region of said transistor extends along a sidewall of said
trench above said collar.
32. The semiconductor device according to claim 31, wherein said
transistor has a gate conductor, said gate conductor being isolated
from said capacitor by a trench top oxide.
Description
BACKGROUND OF THE INVENTION
[0001] The invention relates to semiconductor processing, and more
particularly to an improved method for forming a buried plate and a
collar such as in the fabrication of a trench capacitor of an
advanced microelectronic device, e.g., a dynamic random access
memory (DRAM).
[0002] A goal of the semiconductor industry is to increase the
circuit density of integrated circuits ("ICs" or "chips"), most
often by decreasing the size of individual devices and circuit
elements of a chip. Trench capacitors are used in some types of
DRAMs for storing data bits. Often, increasing the circuit density
of such DRAMs requires reducing the size of the trench capacitor,
which, in turn, requires reducing the area of the chip occupied by
the trench capacitor. Achieving such reduction in surface area is
not straightforward, because different components of the storage
capacitor do not scale at the same rate, and some components cannot
be scaled below a certain size.
[0003] One problem of conventional fabrication techniques is that
the buried plate of the trench capacitor is formed in a processing
step which is separate from that in which a collar is formed above
the buried plate. Because of this, the trench capacitor has lower
than desired capacitance when a lower edge of the collar is
disposed too deep, such that the collar covers up a part of the
trench sidewall along which the buried plate is disposed.
Conversely, when the lower edge of the collar is disposed at too
high a location and does not contact the buried plate, undesirably
high leakage current results.
[0004] Therefore, it would be desirable to provide a structure and
method of forming a buried plate of a trench capacitor in which the
lower edge of the collar is self-aligned to the buried plate.
SUMMARY OF THE INVENTION
[0005] According to an aspect of the invention, a method is
provided for making a collar for a trench disposed in a
semiconductor substrate, the collar being self-aligned to a buried
plate disposed adjacent to the trench. In such method, a trench is
formed in a semiconductor substrate. A dopant source layer is
deposited in the trench. The dopant source layer is recessed to a
first depth below a major surface of the semiconductor substrate. A
barrier layer is formed along a portion of the sidewall of the
trench above the first depth. Thereafter, the dopant source layer
is further recessed to a second depth below the first depth to
expose a middle portion of the sidewall of the trench, such that
the dopant source layer remains below the second depth. Annealing
is performed in an oxygen-containing environment to simultaneously
form an oxide collar along the middle portion of the trench
sidewall and form a buried plate in the semiconductor substrate
adjacent to the dopant source layer.
[0006] According to another aspect of the invention, a method is
provided for making a collar for a trench disposed in a
semiconductor substrate, the collar being self-aligned to a buried
plate disposed adjacent to the trench. According to such method, a
trench is etched to a first depth below a major surface of a
semiconductor substrate. A barrier layer is formed along a top
portion of the sidewall of the trench above the first depth.
Thereafter, the trench is etched to a bottom depth below the first
depth. A dopant source layer is deposited in the trench. A top
surface of the dopant source layer is recessed to a second depth
below the first depth to expose a middle portion of the trench
sidewall between the first and second depths, while the dopant
source layer remains in the trench below the second depth.
Annealing is performed in an oxygen-containing environment to
simultaneously form an oxide collar by local oxidation of the
semiconductor substrate along the middle portion of the trench
sidewall and form a buried plate in the semiconductor substrate
adjacent to the dopant source layer.
[0007] According to yet another aspect of the invention, a
structure is provided in which a collar surrounds a middle portion
of a trench in a semiconductor substrate, the collar having a lower
edge self-aligned to a top edge of a buried plate disposed adjacent
to a lower portion of the trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIGS. 1 through 12 are cross-sectional views illustrating
stages of processing according to a first embodiment of the
invention.
[0009] FIGS. 13 through 15 are cross-sectional views illustrating
stages of processing according to a second embodiment of the
invention.
DETAILED DESCRIPTION
[0010] The embodiments of the invention described herein address
problems of the conventional non-self-aligned process of making a
trench capacitor through separate steps for forming the buried
plate and the collar. In a first embodiment described below, a
trench is etched into a semiconductor substrate, after which a
layer of arsenic doped glass (ASG) or other suitable material is
deposited into the trench as a dopant source material and recessed.
A barrier layer is then formed along a top portion of the trench
sidewall above the level of the recessed ASG layer. Thereafter, the
ASG layer is further recessed to expose a middle portion of the
trench sidewall, while the ASG layer remains in place along a lower
portion of the trench sidewall below the middle portion. A cap
layer covering the remaining ASG layer is then formed, after which
etching is performed to clear the material of the cap layer from
the middle portion of the trench sidewall. An anneal is then
performed in an oxygen-containing environment to simultaneously
form the buried plate in the semiconductor substrate adjacent to
the lower portion of the trench sidewall and form an oxide collar
along the middle portion of the trench sidewall.
[0011] In another embodiment of the invention, the trench is etched
initially into the semiconductor substrate only to a first depth,
which is less than the full depth of the trench when completed. A
barrier layer is then formed along the sidewall of the trench that
has been etched only to the first depth. Thereafter, the trench is
etched to the full depth, after which a layer of arsenic doped
glass (ASG) or other suitable material is deposited as a dopant
source layer. The ASG layer is then recessed to expose a middle
portion of the trench sidewall, while the ASG layer remains in
place along a lower portion of the trench sidewall below the middle
portion. As in the above-described embodiment, a cap layer covering
the remaining ASG layer is then formed, after which etching is
performed to clear the material of the cap layer from the middle
portion of the trench sidewall. An anneal is then performed in an
oxygen-containing environment to simultaneously form the buried
plate in the semiconductor substrate along the lower portion of the
trench sidewall and to form an oxide collar along the middle
portion of the trench sidewall.
[0012] FIGS. 1 through 12 illustrate stages in processing according
to the first embodiment of the invention. FIGS. 1 through 3
illustrate a process of patterning a trench. Illustratively, in
this process, the trench is patterned in a semiconductor substrate
400, which typically consists essentially of p-type doped silicon.
Alternatively, the substrate has a semiconductor-on-insulator type
structure, e.g., is a silicon-on-insulator (SOI) substrate. Other
suitable alternative types of substrates include germanium, silicon
germanium, silicon carbide, strained silicon, and those consisting
essentially of one or more III-V compound semiconductors having a
composition defined by the formula
Al.sub.X1Ga.sub.X2In.sub.X3As.sub.Y1P.sub.Y2N.sub.Y3Sb.sub.Y4,
where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative
proportions, each greater than or equal to zero and
X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity).
Other suitable substrates can be formed of II-VI compound
semiconductors having a composition
Zn.sub.A1Cd.sub.A2Se.sub.B1Te.sub.B2, where A1, A2, B1, and B2 are
relative proportions each greater than or equal to zero and
A1+A2+B1+B2=1 (1 being a total mole quantity).
[0013] A variety of methods may be utilized to form the deep
trench. Typically, a mask layer is first formed and patterned on
the substrate, being comprised of a material less susceptible to
etching, such as a hardmask layer of silicon oxide and/or silicon
nitride or other material. FIG. 1 shows one embodiment in which an
oxide layer 405 functions as a hardmask layer, disposed over a pad
stack 430 having a nitride layer 420 and an optional oxide layer
410. The oxide layer 410 is formed between the pad nitride layer
420 and the semiconductor substrate 400 as a buffer layer to
improve the adhesion of the pad nitride layer 420 and to reduce the
interface stress.
[0014] As shown in the cross-sectional depiction of FIG. 2, the
hardmask layer 405 is patterned and etched to create an opening 500
through which the trench will then be formed in the semiconductor
substrate. Patterning can be done by forming a photoresist layer
(not shown) and developed by any suitable process such as optical
lithography, electron beam lithography, x-ray lithography, and ion
beam lithography. The hardmask layer 405, along with the underlying
pad stack 430 can then be etched selective to the photoresist using
any conventional etch process, for example, reactive ion etch
(RIE). The photoresist is stripped after forming opening the
hardmask or after opening the hardmask and the underlying pad
stack.
[0015] Referring to FIG. 3, the substrate 400 then is etched by any
suitable process such as RIE to form deep trench 600. The remaining
hardmask layer is stripped after forming the deep trench. The deep
trench has a small width, typically ranging from 90 nm to 150 nm
according to the current generation of semiconductor devices. The
deep trench is etched to a depth ranging between about 2 microns
(.mu.m) and 10 .mu.m. Etching defines a trench 600 having a
sidewall 620 and a bottom 610. In one embodiment as illustrated in
FIG. 6, the trench 600 is patterned in a manner that aligns an edge
630 of the pad stack 430 to the sidewall 620 of the trench 600.
Hereinafter, references generally to the trench sidewall and to the
lower portion of the trench sidewall shall be understood to include
the trench bottom 610, as well.
[0016] Referring to FIG. 4, a layer of arsenic doped glass (ASG)
700 or other suitable dopant source layer is deposited in the
trench 600 and then recessed to a first depth 710 below the major
surface 720 of the semiconductor substrate 400. The ASG layer 700
is illustratively performed by LPCVD, CVD (chemical vapor
deposition), PECVD (plasma enhanced CVD), atomic layer deposition
(ALD), or other suitable method. Preferably, low-pressure chemical
vapor deposition (LPCVD) is used to deposit one or more relatively
thin, high quality films to form ASG layer 700. In a preferred
embodiment, the ASG deposition is conducted by LPCVD at 700.degree.
C. for about 60 minutes, resulting in the filling of the trench,
after which the ASG layer is recessed to depth 710. Alternatively,
the layer 700 includes a dopant source layer adjacent to the
semiconductor substrate 400 and another material, which is
preferably undoped, to fill the trench 600. The dopant source layer
is preferably an ASG layer and the undoped material is preferably
undoped oxide. In such case, hereinafter, the layer 700 is referred
to as the "ASG layer 700" for simplicity.
[0017] Optionally, a cap layer 730 is preferably formed to cover
the ASG layer 700 within the trench 600. The cap layer 730
preferably consists essentially of an undoped oxide such as silicon
dioxide, and is preferably deposited by a process which deposits
material preferentially onto horizontal surfaces, in preference
over vertical surfaces such as the trench sidewall 620. Preferably,
the cap layer is deposited by high density plasma (HDP) CVD
process. The deposition rate of HDP process is higher in the
vertical direction than in the lateral direction. Thereafter,
etching is performed to remove deposited oxide from the trench
sidewall 620, while preserving the cap layer 730 overlying the ASG
layer 700. The oxide on the trench sidewall is preferably removed
by a timed-etch with a buffered hydrofluoric (BHF) chemistry.
[0018] Thereafter, as shown in FIG. 5, processing is performed to
form a barrier layer 740 along a top portion 750 of the sidewall of
the trench, extending upwardly from the ASG layer 700 or optional
cap 730 formed on the ASG layer 700. The barrier layer 740
preferably consists of a nitride such as silicon nitride, to
facilitate etch selectivity during oxide etching to be performed
later of the oxide cap layer 730 and later formed oxide collar.
Such barrier layer is formed by low-pressure chemical vapor
deposition (LPCVD), chemical vapor deposition (CVD), atomic layer
deposition or other suitable method. Preferably, an oxide liner 760
is first formed on the top portion 750 of the trench sidewall, as
by a brief thermal oxidation, after which silicon nitride is
preferably deposited as the barrier layer by LPCVD at a temperature
of approximately 700.degree. C. Alternatively, the buried layer 740
may include a deposited or in situ formed silicide such as cobalt
silicide, nickel silicide, tungsten silicide, and titanium
silicide. Other alternatives include titanium nitride, tantalum
nitride, silicon carbide, or any other suitable materials. A
reactive ion etch is then performed to clear the deposited material
of the barrier layer 740 from the top surface of the oxide cap
layer 730.
[0019] Thereafter, the oxide cap layer 730 is removed and the ASG
layer is further recessed by etching selective to the material of
the barrier layer 740 to produce the structure as shown in FIG. 6.
As shown therein, the top of the remaining ASG layer 785 is now
recessed to a second depth 770, which is lower than the first depth
710. Optionally, a further cap layer 780 is now formed over the
remaining ASG layer 785, the cap layer 780 preferably consisting
essentially of a material such as silicon nitride, other nitride or
other material which facilitates good etch selectivity relative to
silicon dioxide. The cap layer 780 is formed in a manner similar to
that described above for forming the oxide cap layer 730 (FIG. 5),
except for the material (silicon nitride) of which the cap layer
780 is preferably formed. After forming the cap layer 780, the
semiconductor substrate 400 along the middle portion 765 of the
sidewall of the trench is exposed.
[0020] Thereafter, as shown in FIG. 7, annealing is performed in an
oxygen-containing environment to drive the dopant in the ASG layer
785 into the substrate and thus form a buried plate 790 in the
region of the substrate 400 adjacent to and preferably surrounding
a bottom portion 775 of the trench 600. During this anneal, the
region of the semiconductor substrate 400 along the middle portion
765 of the trench sidewall is also oxidized in the
oxygen-containing environment to form an oxide collar 795.
Annealing is preferably performed at a temperature between about
900.degree. C. and 1150.degree. C., and more preferably at about
1050.degree. C. During this anneal, the cap layer 780 helps protect
against arsenic doping of the semiconductor substrate 400 disposed
along the middle portion 765 and top portion 750 of the trench
sidewall, despite the proximity thereto of the ASG layer 785 in the
trench 600. As a result of the simultaneous formation of the buried
plate 790 and the oxide collar 795, the oxide collar 795 is formed
in a self-aligned manner to the buried plate 790. In other words,
the lower edge 797 of the oxide collar 795 is self-aligned to the
buried plate 790, such that the lower edge 797 of the oxide collar
795 is disposed at the same or essentially the same depth from the
major surface 720 of the substrate as the upper edge 799 of the
buried plate 790.
[0021] The formation of the buried plate 790 and oxide collar 795
are now complete. Further processing is now begun which will result
in removal of the remaining ASG layer 785 and formation of a trench
capacitor and other structures in the trench 600. As shown in FIG.
8, a second barrier layer 800 is formed overlying the previously
formed oxide collar 795 and barrier layer 740. The second barrier
layer 800 is formed by depositing a nitride such as silicon nitride
or other material which facilitates good etch selectivity when
etching oxide, and thereafter etching the deposited barrier layer
material in the vertical direction, as by RIE, to expose the top
surface of the remaining ASG layer 785, as indicated at the second
depth 770.
[0022] Thereafter, as shown in FIG. 9, the remaining ASG layer is
removed by etching selective to the material of the second barrier
layer 800. During this etch, the oxide collar 795 is protected by
the second barrier layer 800 and the portion 910 of the cap layer
that remains. FIG. 10 illustrates results of optional processing
performed thereafter to widen the dimensions of the bottom portion
775 of the trench to form a bottle-shaped trench. The capacitance
of a trench capacitor to be formed thereafter along the bottom
portion of the trench (see FIG. 12 and accompanying description) is
enhanced when the bottom portion is widened. Such processing is
preferably performed by etching the semiconductor substrate 400
selective to the materials of the second barrier layer 800 and
oxide collar 795 to produce a widened bottom portion 775 of the
trench 600 having a widened dimension 1010 which is larger than the
original dimension 1000 of the trench 600, as measured between the
locations 1030 of the original sidewalls of the trench 600. Other
trench capacitance enhancement approaches also may be practiced at
this point in the process, such as formation of hemispherical
silicon grain (HSG) in the bottom potion. The doping concentration
in the buried plate can also be further raised at this time to
increase the trench capacitance by performing gas phase doping
(GPD), liquid phase doping (LPD), plasma doping, plasma immersion
ion implantation (PIII), or any combination of these
approaches.
[0023] FIG. 11 illustrates the results of further processing to
remove the barrier layer and second barrier layer from the trench,
as well as the remaining portion of the cap layer. As a result, the
buried plate 790 and the self-aligned collar 795 remain, and the
top portion 750 of the trench sidewall is cleared of the barrier
layers and oxide liner. Such processing is preferably performed by
isotropic etching selective to the material of the semiconductor
substrate 400 and to oxide.
[0024] FIG. 12 illustrates a stage of processing after further
steps have been performed to complete a trench capacitor 1200 and a
vertical transistor 1250 disposed above the trench capacitor 1200.
As shown in FIG. 12, the trench capacitor 1200 includes the buried
plate 790, a node dielectric 1210 formed on the sidewall 1205 of
the silicon where the buried plate 790 is located, and a node
electrode 1220 disposed on the opposite side of the node dielectric
1210 from the buried plate 790.
[0025] The formation of the vertical transistor 1250 along the top
portion 750 of the trench sidewall is only illustrative. Many other
structures and ways of forming transistors which connect to the
trench capacitor are possible. In the example shown in FIG. 12, the
trench capacitor 1200 is separated from the vertical transistor by
the oxide collar 795. The vertical transistor includes a gate
conductor 1243, a gate dielectric 1245 and a channel region 1230.
The channel region 1230 allows current to pass only when the gate
conductor 1243 is biased at an appropriate voltage. The gate
conductor 1243 is isolated from the node electrode 1220 by a trench
top oxide 1260. The vertical transistor 1250 is electrically
connected to the node electrode 1220 by an n-type buried strap
outdiffusion 1270 formed in the silicon substrate 400 adjacent to
the gate dielectric 1245, by outdiffusion of a dopant from a
deposited buried strap 1265. A drain region 1247 is disposed in the
silicon substrate 400 above the channel region 1230.
[0026] Alternatively, instead of a vertical transistor, a planar
transistor can be formed which connects to the trench capacitor
1200. Alternatively, the trench capacitor 1200 can be simply
connected to circuitry of the chip, such as for use in providing a
source of local capacitance, e.g., for decoupling purposes.
[0027] FIGS. 13 through 15 illustrate processing according to a
second embodiment of the invention, in which the deep trench is
etched in two separate steps, such that the ASG layer need only be
recessed once. In this embodiment, processing is the same as that
shown and described above with reference to FIGS. 1 through 12,
except for differences as noted herein. FIG. 13 illustrates a stage
of processing following that shown in FIG. 2, in which a trench
1300 is etched only to a first depth 1310 which is less than the
full depth of the trench when completed. A barrier layer 1320 is
then formed on the sidewall of the trench, such barrier layer
preferably consisting essentially of a nitride such as silicon
nitride or other material which facilitates good etch selectivity
when etching oxide. Such barrier layer 1320 is preferably formed
over an oxide liner 1330 formed prior thereto on the trench
sidewall. The barrier layer 1320 and oxide liner 1330 are
preferably formed according to the process described above with
reference to FIG. 5. These steps are performed in a manner allowing
the hardmask layer 405 to remain in place.
[0028] Thereafter, as shown in FIG. 14, the trench 1300 is etched
to the full depth 1400, after which the hardmask is stripped from
the structure. FIG. 15 illustrates a subsequent stage in which a
dopant source layer 1500 consisting essentially of a material such
as ASG is deposited and then recessed within the trench 1300 to a
depth 1510. Alternatively, the layer 1500 may include a dopant
source layer adjacent to the semiconductor substrate 400 and a
layer of another material, which is preferably undoped, to fill the
trench. The dopant source layer is preferably an ASG layer and the
undoped material is preferably undoped oxide. In such case,
hereinafter, the layer 1500 is referred to as the "ASG layer 1500"
for simplicity.
[0029] Thereafter, a cap layer 1520 is formed to cover the ASG
layer 1500, the cap layer 1500 preferably consisting essentially of
a nitride such as silicon nitride or other material to facilitate
good etch selectivity relative to oxide. Etching is performed
selective to the material of the semiconductor substrate 400 such
that the middle portion 1530 of the trench sidewall is cleared of
the material of the cap layer 1520. Thereafter, processing proceeds
in the same manner as that shown and described above with reference
to FIGS. 7 through 12 to form a trench capacitor, and optionally, a
transistor having a connection to the trench capacitor.
[0030] Accordingly, the foregoing described embodiments of the
invention address challenges of the prior art through processing in
which the collar is formed simultaneously with the buried plate, in
a self-aligned manner to the buried plate.
[0031] While the invention has been described in accordance with
certain preferred embodiments thereof, those skilled in the art
will understand the many modifications and enhancements which can
be made thereto without departing from the true scope and spirit of
the invention, which is limited only by the claims appended
below.
* * * * *