U.S. patent application number 11/132750 was filed with the patent office on 2006-11-23 for circuits, devices and methods for regulator minimum load control.
This patent application is currently assigned to Texas Instruments Incorporated. Invention is credited to Benjamin L. Amey, John H. JR. Carpenter, Joseph A. Devore, Brett J. Thompsen, Zhihong You.
Application Number | 20060261793 11/132750 |
Document ID | / |
Family ID | 37447747 |
Filed Date | 2006-11-23 |
United States Patent
Application |
20060261793 |
Kind Code |
A1 |
Carpenter; John H. JR. ; et
al. |
November 23, 2006 |
Circuits, devices and methods for regulator minimum load
control
Abstract
Systems, methods and circuits for regulator minimum load
control. In one particular case, a system is provided that includes
a load control circuit and a switched load. The load control
circuit includes a reference current, and a sense current
representative of a load current. In addition, the load control
circuit includes a comparator circuit that drives a control signal
in response to a comparison between the reference current and the
sense current. The switched load is electrically coupled to a load
voltage signal to provide loading to the load voltage signal. The
switched load is operable to switch between a first loading factor
and a second loading factor in response to the control signal.
Inventors: |
Carpenter; John H. JR.;
(Rowlett, TX) ; Thompsen; Brett J.; (Dallas,
TX) ; Amey; Benjamin L.; (Allen, TX) ; You;
Zhihong; (Plano, TX) ; Devore; Joseph A.;
(Richardson, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
US
|
Assignee: |
Texas Instruments
Incorporated
Dallas
TX
75265
|
Family ID: |
37447747 |
Appl. No.: |
11/132750 |
Filed: |
May 18, 2005 |
Current U.S.
Class: |
323/282 |
Current CPC
Class: |
G05F 1/618 20130101 |
Class at
Publication: |
323/282 |
International
Class: |
G05F 1/00 20060101
G05F001/00 |
Claims
1. A circuit for regulator minimum load control, the circuit
comprising: a load control circuit, wherein the load control
circuit includes: a reference current; a sense current
representative of a load current; a comparator circuit, wherein the
comparator circuit drives a control signal in response to a
comparison between the reference current and the sense current; and
a switched load, wherein the switched load is electrically coupled
to a load voltage signal and to the control signal, and wherein the
switched load is operable to switch between a first loading factor
and a second loading factor in response to the control signal.
2. The circuit of claim 1, wherein the circuit further comprises: a
voltage regulator circuit, wherein the voltage regulator circuit
provides the load current and the load voltage signal.
3. The circuit of claim 2, wherein a drive load is electrically
coupled to the load voltage signal, and wherein the load current
includes both current provided to the drive load and current
provided to the switched load.
4. The circuit of claim 1, wherein the switched load comprises a
transistor and a resistor, and wherein the transistor is activated
based on the control signal.
5. The circuit of claim 4, wherein the transistor includes a gate,
a drain, and a source; wherein the gate is electrically coupled to
the control signal; wherein the drain is electrically coupled to a
first end of the resistor, and wherein a second end of the resistor
is electrically coupled to the load voltage signal.
6. The circuit of claim 5, wherein the control signal is a
substantially binary signal transitioning between a logical `1` and
a logical `0` state.
7. The circuit of claim 1, wherein the first loading factor is a
no-load value, and wherein the second loading factor is a minimum
load value.
8. The circuit of claim 7, wherein the circuit further comprises a
voltage regulator circuit, wherein the voltage regulator circuit
provides the load current and the load voltage signal; and wherein
the minimum load value is selected such that the voltage regulator
circuit is maintained in an operationally stable state.
9. The circuit of claim 1, wherein the comparator circuit comprises
a bipolar transistor, wherein the sense current is electrically
coupled to the base of the bipolar transistor, wherein the
reference current is electrically coupled to the collector of the
bipolar transistor, and wherein the control signal is electrically
coupled to the collector of the bipolar transistor.
10. A method for controlling voltage regulator loading, the method
comprising: providing a voltage regulator circuit, wherein the
voltage regulator circuit provides a load current and a load
voltage signal; providing a reference current; providing a switched
load, wherein the switched load is electrically coupled to the load
voltage signal; comparing a representation of the load current with
the reference current; and based at least in part on comparing the
representation of the load current with the reference current,
activating a load control signal; wherein the switched load is
transitioned from a first loading factor to a second loading
factor.
11. The method of claim 10, wherein the load control signal is a
substantially binary signal, wherein activating the load control
signal includes transitioning the load control signal between a
first binary state and a second binary state, wherein the first
binary state corresponds to the first loading factor which is a
no-load value, and wherein the second binary state corresponds to
the second loading factor which is a minimum load value.
12. The method of claim 11, wherein the minimum load value is
selected such that the voltage regulator circuit is maintained in
an operationally stable state.
13. The method of claim 10, wherein the load control signal is a
substantially smooth signal transitioning between three or more
levels, wherein a first of the three or more levels corresponds to
the first loading factor, and wherein a second of the three or more
levels corresponds to the second loading factor.
14. A system for providing regulator minimum load control, the
system comprising: a voltage regulator circuit, wherein the voltage
regulator circuit drives a load voltage signal, and wherein the
voltage regulator circuit provides a load current; a load control
circuit, wherein the load control circuit is operable to sense the
load current; and a switched load, wherein the switched load is
electrically coupled to the load voltage signal; and wherein, based
at least in part on the sensed load current, the load control
circuit is operable to modify the switched load.
15. The system of claim 14, wherein the switched load is a smooth
switched load, and wherein activating the switched load includes
switching the load to one of a plurality of load factors.
16. The system of claim 14, wherein the switched load is a step
switched load, and wherein activating the switched load includes
switching the load between one of a first load factor and a second
load factor.
17. The system of claim 14, wherein the load control circuit drives
a load control signal.
18. The system of claim 17, wherein the switched load comprises a
transistor and a resistor, and wherein the transistor is activated
based on the load control signal.
19. The system of claim 18, wherein the load control signal is a
substantially binary signal transitioning between a logical `1`
level and a logical `0` level.
20. The system of claim 18, wherein the load control signal is a
substantially smooth signal transitioning between three or more
levels.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention is related to voltage regulators. More
particularly, the present invention is related to circuits, systems
and methods for maintaining voltage regulators at a desired loading
condition.
[0002] A prior art regulated system 100 is depicted in FIG. 1.
Regulated system 100 includes a voltage regulator 110 that
regulates an input voltage 102, and outputs a regulated voltage 120
to an overall load 140. Voltage regulator 110 includes an
operational amplifier 112 receiving input voltage 102 and driving a
FET 114. The drain of FET 114 is tied to a voltage source 122, and
the source of FET 114 drives regulated voltage 120. A feedback loop
of operational amplifier 112 is driven by the regulated voltage
signal as divided by resistors 116, 118.
[0003] Overall load 140 includes a drive load 132 and a dummy load
136. Dummy load 136 is a resistive load, and is included to assure
that voltage regulator 110 is always supplying at least some load.
By maintaining at least some loading on voltage regulator 110,
operational amplifier 112 is maintained in a desired range of
operation and regulated voltage 120 is maintained relatively
constant. However, maintaining minimum loading through use of dummy
load 136 is wasteful. In particular, dummy load 136 is always
drawing current from voltage regulator 110 which is dissipated as
heat. Both the heat and the wasted current are undesirable.
[0004] Hence, for at least the aforementioned reasons, there exists
a need in the art for advanced circuits, systems and methods for
regulating voltages.
BRIEF SUMMARY OF THE INVENTION
[0005] The present invention is related to voltage regulators. More
particularly, the present invention is related to circuits, systems
and methods for maintaining voltage regulators at a desired loading
condition.
[0006] Various embodiments of the present invention provide
circuits for regulator minimum load control. The circuits include a
load control circuit and a switched load. The load control circuit
includes a reference current, and a sense current representative of
a load current. In addition, the load control circuit includes a
comparator circuit that drives a control signal in response to a
comparison between the reference current and the sense current. The
switched load is electrically coupled to a load voltage signal and
to the control signal from the load control circuit. The switched
load is operable to switch between a first loading factor and a
second loading factor in response to the control signal.
[0007] As just one of many examples, such a circuit may be used to
selectively load a voltage regulator by asserting/de-asserting the
control signal. In such a case, the circuit may further include a
voltage regulator circuit that provides the load current and the
load voltage signal to the switched load. The load current may
include a drive load component and switched load component. The
drive load component includes current provided to a drive load
attached to the voltage regulator, and the switched load component
includes current provided to the switched load.
[0008] In some instances of the embodiments, the switched load
includes a transistor and a resistor. In such instances, the
transistor is used to selectively control current flow to the
resistor. Thus, the transistor may be used to modify the switched
load between a resistive load approximately equal to the resistor
and a no-load (i.e., open) condition. In one particular instance,
the transistor is controlled by a substantially binary control
signal that transitions between a logical `1` state and a logical
`0` state. As an example, in the logical `1` state the switched
load has a load approximately equal to the resistor, and in the
logical `0` state the switched load looks like an open or no-load.
In some cases, the resistor is selected to provide a minimum load.
This "minimum load" is defined as a load drawing a current
sufficient to maintain the regulator circuit in an operationally
stable, or otherwise desirable state.
[0009] In various instance of the embodiments, the comparator
circuit comprises a bipolar transistor. In such instances, the
sense current may be electrically coupled to the base of the
bipolar transistor, and the reference current may be electrically
coupled to the collector of the bipolar transistor. The control
signal provided by the comparator may also be electrically coupled
to the collector of the bipolar transistor.
[0010] Other embodiments of the present invention provide methods
for controlling voltage regulator loading. Such methods include
providing a voltage regulator circuit, a reference current and a
switched load. The voltage regulator circuit provides a load
current and a load voltage signal, and the switched load is
electrically coupled to the load voltage signal. The methods
further include comparing a representation of the load current with
the reference current. Based at least in part on comparing the
representation of the load current with the reference current, a
load control signal is activated (i.e., asserted). Upon activating
the load control signal, the switched load is transitioned from a
first loading factor to a second loading factor.
[0011] Yet other embodiments of the present invention provide
systems for regulator minimum load control. The systems include a
voltage regulator circuit that drives a load voltage signal and
provides a load current. In addition, the systems include a
switched load and a load control circuit. The switched load is
electrically coupled to the load voltage signal. The load control
circuit is operable to sense the load current, and based thereon,
to modify and/or activate the switched load. In some instances of
the embodiments, the switched load is a smooth switched load
capable of switching between three or more load factors, while in
other instances the switched load is a step switched load capable
of switching between two load factors. In particular instances of
the embodiments, modification of the switched load is performed via
a load control signal. In such cases, the load control signal may
be a substantially binary signal transitioning between an active
state and an inactive state, or a substantially smooth signal
transitioning between three or more distinct levels or states.
[0012] This summary provides only a general outline of some
embodiments of the present invention. Many other objects, features,
advantages and other embodiments of the present invention will
become more fully apparent from the following detailed description,
the appended claims and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In the Figures, similar components and/or features may have
the same reference label. Further, various components of the same
type may be distinguished by following the reference label with a
second label that distinguishes among the similar components. If
only the first reference label is used in the specification, the
description is applicable to any one of the similar components
having the same first reference label irrespective of the second
reference label.
[0014] FIG. 1 depicts a prior art voltage regulator and switch
load;
[0015] FIG. 2A depicts a voltage regulator associated with a load
control circuit and switched load in accordance with various
embodiments of the present invention;
[0016] FIG. 2B illustrates an exemplary comparator circuit useful
in relation to one or more embodiments of the present
invention;
[0017] FIG. 2C is a timing diagram illustrating operation of the
system depicted in FIGS. 2A-2B;
[0018] FIG. 3A depicts a voltage regulator associated with a load
control circuit and switched load in accordance with other
embodiments of the present invention;
[0019] FIG. 3B is a timing diagram illustrating operation of the
system depicted in FIG. 3A; and
[0020] FIG. 3C shows an exemplary amplifier loop circuit that may
be used in relation to the system depicted in FIG. 3A.
DETAILED DESCRIPTION OF THE INVENTION
[0021] The present invention is related to voltage regulators. More
particularly, the present invention is related to circuits, systems
and methods for maintaining voltage regulators at a desired loading
condition.
[0022] Various embodiments of the present invention provide
circuits, systems and methods for regulator load control. Such
embodiments may include a load control circuit and a switched load.
The load control circuit may include a reference current and a
sense current representative of a load current. In addition, the
load control circuit may include a comparator circuit that drives a
load control signal in response to a comparison between the
reference current and the sense current. The load control signal is
operable to switch the switched load between various supported load
factors. As used herein, the term "load factor" is used in its
broadest sense to mean any circuit load. In some cases, the load is
a purely resistive load. In other cases, the load is a purely
capacitive or inductive load, while in other cases, the load is
some combination of resistive, capacitive, and/or inductive
loads.
[0023] As just one of many examples, such embodiments may be used
to selectively load a voltage regulator by asserting/de-asserting
the load control signal. In such a case, the circuit may further
include a voltage regulator circuit that provides the load current
and the load voltage signal to the switched load. The load current
may include a drive load component and switched load component. The
drive load component includes current provided to a drive load
attached to the voltage regulator, and the switched load component
includes current provided to the switched load. As used herein, the
term "drive load" includes any load other than the switched load
that is being driven by the voltage regulator.
[0024] In some cases, the sense current may be a representation of
the load current. For the purposes of this document, the term
"representation" is used in its broadest sense to mean any value
mathematically related to any other value. Thus, as just some
general examples, the sense current may be some percentage of the
load current, the load current plus some offset current, and/or a
combination of the aforementioned. Based on the disclosure provided
herein, one of ordinary skill in the art will appreciate the myriad
of relationships between a sense current and a load current that
are considered a "representation of the load current".
[0025] As used herein, the term "switched load" is used in its
broadest sense to mean any load capable of being switched between
two or more loading factors. There are generally two types of
switched loads: a "step" switched load capable of switching between
two loading factors, and a "smooth" switched load capable of
switching between three or more loading factors. Thus, as will be
appreciated by one of ordinary skill in the art, a smooth switched
load may be switched between three discreet points across a
continuum, between an upper limit (potentially a thousand or more)
of points across the continuum, or between any number of points
between three and the upper limit.
[0026] The load control signal may be a step signal capable of
toggling between two detectable levels. In general, the two levels
are a logical `1` and a logical `0` level. In one case, the logical
`1` level is associated with a supply voltage level and the logical
`0` level is associated with a ground level, however, one of
ordinary skill in the art will appreciate a number of associations
that can correspond with the logical `0` and logical `1` levels.
Alternatively, the load control signal may be a "smooth" signal
capable of transitioning between three or more detectable levels.
Thus, as will be appreciated by one of ordinary skill in the art, a
smooth load control signal may be switched between three discreet
points across a continuum, between an upper limit (potentially a
thousand or more) of points across the continuum, or between any
number of points between three and the upper limit.
[0027] Also, as used herein, the term "electrically coupled" is
used in its broadest sense to mean any type of coupling whereby an
electrical connection is made between two endpoints. Thus, for
example, two devices electrically connected via a wire or other
conductive path are electrically coupled. Alternatively, two end
devices separated by one or more electrically conductive devices
are electrically coupled where there is a signal path capable of
passing some electrical current originating at one end device to
the other end device. It should be noted that not all current
originating at one end device must be received at the other end
device for the devices to be considered electrically coupled.
Rather, only some portion of the current need pass from one end
device to the other end device to be electrically coupled in
accordance with the definition use herein.
[0028] Turning to FIG. 2A, a switched load system 200 in accordance
with various embodiments of the present invention is illustrated.
Switch load system 200 includes a switched load 250 and a load
control circuit 260 coupled to a voltage regulator 210. In
operation, voltage regulator 210 supplies power to a drive load
232. For the purposes of this document, drive load 232 may be any
electrical load receiving current from voltage regulator 210. Thus,
for example, drive load 232 may be as simple as a resistor, or
something more complex such as a microprocessor circuit. In
operation, drive load 232 draws a drive current (I.sub.drive), and
voltage regulator 210 supplies a load current (I.sub.load).
[0029] Voltage regulator circuit 210 includes an operational
amplifier 212 receiving an input voltage (V.sub.in) 204 and driving
a gate 215 of a Field Effect Transistor ("FET") 214. A drain 213 of
FET 214 is connected to a voltage source 222, and a source 217 of
FET 214 is connected to a node 230 exhibiting a regulated voltage
(V.sub.reg). A feedback loop 206 of operational amplifier 212 is
connected to a node 229 exhibiting a V.sub.reg as divided by
resistors 216, 218. A relatively small feedback current (I.sub.fb)
flows through feedback loop 206.
[0030] Operational amplifier outputs a control voltage 211
depending on a difference between input voltage 204 and the voltage
exhibited on feedback loop 206. FET 214 allows I.sub.load to pass
from drain 213 to source 217 depending upon control voltage 211.
When voltage regulator 210 is maintained in a defined operational
range, operational amplifier 212 acts to force the voltage
exhibited on feedback loop 206 to be the same as input voltage 204.
This process results in the desired condition of a stable V.sub.reg
at node 230 across a reasonably wide range of loads. However, when
voltage regulator 210 is unloaded (i.e., no load is coupled to node
230), operational amplifier 212 can become unstable. The
instability of operational amplifier 212 results in undesired
instability of V.sub.reg.
[0031] The combination of switched load 250 and load control
circuit 260 operate to reduce or eliminate the possibility that
operational amplifier 212 will become unstable by assuring that
voltage regulator 210 is always driving at least a minimum load. To
do this, load control circuit 260 monitors the operation of voltage
regulator 210 to determine when drive load 232 is either removed,
or does not present a load factor to voltage regulator 210 that is
sufficient to maintain voltage regulator 212 in an operational
range. Where this situation is detected, load control circuit 260
activates switched load 250 such that voltage regulator 210 is
maintained in a minimum loading situation.
[0032] Load control circuit 260 includes a current source 268 that
provides a reference current (I.sub.ref) to a comparator 266. In
addition, load control circuit 260 includes a FET 262 with a gate
261, a drain 213, and a source 264. Drain 213 of FET 262 is
connected to voltage source 222, and source 264 of FET 262 drives a
sense current (I.sub.sense). As gate 261 of FET 262 is connected to
gate 215 of FET 214, I.sub.sense provided from FET 262 is
representative of the load current provided by FET 214. Based on
the disclosure provided herein, one of ordinary skill in the art
will appreciate a variety of components and/or designs that may be
adopted to create a sense current that tracks or otherwise
represents a load current. As just some examples, the circuit may
be designed such that I.sub.sense is approximately equal to
I.sub.load, or another circuit may be designed such that
I.sub.sense is proportional to, but much less than I.sub.load.
I.sub.sense is provided to comparator 266 that compares I.sub.sense
with I.sub.ref. In response to the comparison, comparator 266
asserts/de-asserts a control signal 242. The following equations
describe the operation of comparator 266: Control Signal=Asserted,
where I.sub.sense<=I.sub.ref, and Control Signal=De-asserted,
wherein I.sub.sense>I.sub.ref. Based on the forgoing equations,
it will be recognized that control signal 242 is a substantially
binary signal transitioning between a logical `1` and a logical `0`
state. As used herein, the term "substantially binary" refers to a
signal that is intended for detection at two different states:
asserted and de-asserted. Such a substantially binary signal may be
a square wave, or a sinusoidal wave passing through distinct
thresholds defining the active and inactive states. Such a signal
is useful in switching a step switched load.
[0033] Switched load 250 includes a resistor 246 connected between
drain 245 of a FET 244 and node 230. Control signal 242 is
connected to a gate 241 of FET 244. Thus, when control signal 242
is asserted, resistor 246 is added as a load to node 230. In this
condition a switch current (I.sub.switch) passes through resistor
246 and FET 244. Conversely, when control signal 242 is de-asserted
FET 244 does not allow current to flow through resistor 246, and
resistor 246 is effectively removed as a load from node 230. The
following equations describe the operation of switched load 250:
Switched Load=Resistor, where Control Signal is asserted; and
Switched Load=Open, where Control Signal is de-asserted. Based on
the forgoing equations, it will be recognized that switched load
250 is a step switched load. In this particular case, the load
values or factors of switched load 250 are finite and open.
[0034] Turning now to FIG. 2B, an exemplary comparator circuit 201
that may be used to perform the functions of comparator 266 is
illustrated. Comparator circuit 201 includes a bipolar transistor
211 with its base connected to source 264 of FET 262 (I.sub.sense),
and its collector connected to current source 268 (I.sub.ref).
Thus, a voltage (V.sub.colletor) defined by I.sub.ref and a
resistor (R1) 283 is applied to the collector of bipolar transistor
211, and another voltage (V.sub.base) defined by I.sub.sense and a
resistor (R2) 221 is applied to the base of bipolar transistor 211.
The following equations describe the voltages where I.sub.sense
varies in proportion to I.sub.load: V.sub.collector=I.sub.ref*R2;
and V.sub.base=I.sub.sense*R1, which is proportional to
I.sub.load*R1. As I.sub.ref is substantially constant,
V.sub.collector is also substantially constant. In contrast,
V.sub.base varies in proportion to the changes in I.sub.load as
represented by I.sub.sense. Thus, where I.sub.load becomes very low
due to a disconnect or other change in drive load 232, V.sub.base
decreases to a point that bipolar transistor turns off, and control
signal 242 is asserted, which in this case is at the level of
V.sub.collector. Alternatively, where I.sub.load increases as
governed by drive load 232, V.sub.base increases and bipolar
transistor 211 turns on, and control signal 242 is de-asserted,
which in this case is approximately ground. Based on the disclosure
provided herein, one of ordinary skill in the art will recognize a
variety of other comparator circuits that maybe used to perform the
functions of comparator 266.
[0035] Turning to FIG. 2C, a graph 251 illustrates the operation of
switched load system 200. Graph 251 illustrates current/voltage
(vertical axis) verses time (horizontal axis). I.sub.load is shown
as solid line 273, I.sub.drive is shown as dashed line 263 which is
coextensive with line 273c, 273b. Control signal 242 is represented
by a dashed line 253, and reference markers 283, 285 indicate the
occurrence of hysteresis.
[0036] Following graph 251, at time T.sub.0 drive load 232 is
disconnected from node 230. In this condition, control signal 242
is asserted (shown as dashed line 253a) causing FET 244 to turn on
and load node 230 with resistor 246. As suggested above, FET 244 is
turned on to apply a minimum load factor to node 230 and assure
that voltage regulator 210 is maintained in an operationally stable
region. With FET 244 turned on and drive load 232 disconnected from
node 230, I.sub.load is equal to I.sub.switch where I.sub.fb is
assumed to be insignificant. This continues until time T.sub.1 when
drive load 232 is coupled to node 230 with a load that is linearly
decreasing from time T.sub.1 to time T.sub.3. As shown by line
263a, I.sub.drive increases as the load presented by drive load 232
decreases. This increasing I.sub.drive is added to I.sub.switch
resulting in I.sub.load depicted as line 273b. At time T.sub.2,
I.sub.load has increased to the extent that comparator 266
de-asserts control signal 242. With control signal 242 de-asserted
(shown as dashed line 253b), FET 244 turns off effectively
detaching the load of resistor 246 from node 230. At this point,
I.sub.load is equal to I.sub.drive where I.sub.fb is assumed to be
insignificant (shown as line 273c).
[0037] Beginning at time T.sub.3, the load presented to node 230 by
drive load 232 is continually increased until time T.sub.5 where
drive load 232 is effectively disconnected from node 230. From time
T.sub.3 until time T.sub.4, the load presented to node 230
increases resulting in a corresponding decrease in I.sub.load
(shown as line 273d), but is sufficient to maintain voltage
regulator 210 in a stable operational region. At time T.sub.4, the
load presented at node 230 by drive load 232 becomes insufficient
to maintain voltage regulator 210 in an operationally stable
condition. At this point, I.sub.load has decreased to the extent
that load control circuit 260 asserts control signal 242 (shown as
dashed line 253c). Assertion of control signal 242 causes FET 244
to turn on, whereby node 230 is loaded with resistor 246. At this
point, I.sub.load (shown as line 273e) is equal to I.sub.drive
(shown as dashed line 263b) plus I.sub.switch. At time T.sub.5,
drive load 232 appears essentially disconnected from node 230 and
I.sub.load is equal to I.sub.switch where I.sub.fb is assumed to be
insignificant (shown as line 273f).
[0038] Graph 251 is contrived to show the effect of transitioning
switched load 250 on switched load system 200. It should be noted
that I.sub.load may assume a number of different wave forms
depending upon the operation of drive load 232 and the transition
levels selected for switching switched load 250. Further, it should
be noted at this juncture that while switched load system 200 is
illustrated with particular components including FETs and
operational amplifiers, one of ordinary skill in the art upon
reading this disclosure will appreciate a variety of other
components may be used to create circuitry capable of performing
the functions of switched load system 200. Thus, for example, where
n-channel FETs are shown it should be recognized that p-channel
FETs or bipolar transistors may be used to create similar
functionality. Also, one of ordinary skill in the art will
recognize that voltage regulator 210 is exemplary of many different
types of voltage regulators known in the art. Based on the
disclosure provided herein, one of ordinary skill in the art will
appreciate that load control circuit 260 and/or switched load 250
may be applied to other types of voltage regulators in accordance
with one or more embodiments of the invention. Yet further, one of
ordinary skill in the art will appreciate functional equivalents of
load control circuit 260 and switched load 250 that may be used in
accordance with various embodiments of the present invention.
[0039] Turning now to FIG. 3A, another switched load system 300 in
accordance with other embodiments of the present invention is
illustrated. Switch load system 300 includes voltage regulator 210
supplying drive load 232 coupled to node 230. In addition, switch
load system 300 includes a smoothly varying load control 360 that
applies a smooth switched load at node 230. This smooth switched
load is applied where drive load 232 becomes insufficient to
maintain voltage regulator 210 in an operationally stable
condition. Thus, in contrast to switched load system 200 that
provided a load current with a step function due to the switching
of switched load 250, switched load system 300 provides a smoothly
varying load to node 230 in such a way that the step transition on
the load current is eliminated.
[0040] The smoothly varying load is produced by an amplifier loop
circuit 366. Amplifier loop circuit 366 receives I.sub.ref and
I.sub.sense. As discussed above, I.sub.sense decreases as drive
load 232 increases. In this case, where I.sub.sense decreases to
equal I.sub.ref, amplifier loop circuit 366 begins applying a load
to node 230. This load is varied such that I.sub.sense holds at a
constant level. Based on the disclosure provided herein, one of
ordinary skill in the art will be capable of designing an amplifier
loop circuit capable of providing the desired loading
condition.
[0041] Turning to FIG. 3B, a graph 351 illustrates the operation of
switched load system 300. Graph 351 illustrates current/switch load
(vertical axis) verses time (horizontal axis). I.sub.load is shown
as solid line 363, I.sub.drive is shown as dashed line 383 which is
coextensive with line 363b, 363c. The switch load applied to node
230 by amplifier loop circuit is shown as line 393.
[0042] Following graph 351, at time T.sub.0 drive load 232 is
disconnected from node 230. In this condition, amplifier loop
circuit 366 provides a constant load to node 230. This results in a
constant I.sub.load (shown as line 363a) which continues until time
T.sub.1. At this time, I.sub.drive is zero, and I.sub.load is equal
to I.sub.switch (shown as line 393a offset from zero for clarity).
At time T.sub.1, drive load 232 is coupled to node 230 and presents
a linearly decreasing load from time T.sub.1 to time T.sub.3, and a
lineraly increasing load from time T.sub.3 to time T.sub.5. As
shown by line 383a, I.sub.drive increases as the load presented by
drive load 232 decreases. Between time T.sub.1 and time T.sub.2,
I.sub.load is approximately equal to I.sub.drive plus I.sub.switch.
To maintain I.sub.load constant, I.sub.switch (shown as line 393b)
is decreasing at a rate complementary to the increase in
I.sub.drive (shown as line 383a). Thus, between time T.sub.1 and
T.sub.2, the load presented by amplifier loop circuit 366 is
increasing. At time T.sub.2, the load presented by amplifier loop
control 366 appears as an open circuit at node 230, and
I.sub.switch is zero (shown as line 393c). Thus, from time T.sub.2
to T.sub.4, I.sub.load is equal to I.sub.drive (shown as lines 363b
and 363c).
[0043] From time T.sub.4 to time T.sub.5, the load presented to
node 230 drops below a defined load value, yet I.sub.load remains
constant (shown as line 363d). During this time, I.sub.drive (shown
as dashed line 383b) is decreasing in relation to the change in
drive load 232, and the load presented by amplifier loop circuit
366 is changing to negate the change in drive load 232. Said
another way, I.sub.switch (shown as line 393d) is increasing at a
rate complementary to the decrease in I.sub.drive (shown as dashed
line 383b). At time T.sub.5, drive load 232 is disconnected from
node 230 and I.sub.drive equals zero. At this time, I.sub.load
(shown as line 363d) equals I.sub.switch (shown as line 393e).
[0044] Turning to FIG. 3C, an exemplary circuit 367 is illustrated.
Exemplary circuit 367 may be used to perform the functions of
amplifier loop control 366 of switched load system 300 depicted in
FIG. 3A. Circuit 367 includes a current input operational amplifier
330 receiving I.sub.sense at a positive input 331, and I.sub.ref at
a negative input 332. An output 333 of current input operational
amplifier 330 is electrically coupled to the gate of a FET 310, and
to the gate of a FET 320. The source of FET 310 and the source of
FET 320 are electrically coupled to I.sub.switch. The drain of FET
320 is electrically coupled to ground, and the drain of FET 310 is
electrically coupled to I.sub.sense. As shown, the size of FET 320
(nY) is "n" times larger than the size of FET 310 (Y). Based on the
disclosure provided herein, one of ordinary skill in the art will
appreciate other circuits that may be utilized to perform the
functions of amplifier loop control 366.
[0045] Operation of circuit 367 is described in relation to
switched load system 300 where circuit 367 takes place of amplifier
loop control 366. In operation, circuit 367 forces
I.sub.drive+I.sub.switch to be greater than or equal to nI.sub.ref.
To do this, FET 310 and FET 320 are switched based on the current
differential across the inputs 331, 332 of current input
operational amplifier 330. Where I.sub.sense is not substantially
less than I.sub.ref, FETs 310, 320 are not switched and
I.sub.switch is approximately equal to zero. In this situation,
I.sub.load is approximately equal to I.sub.drive where the current
through resistor 218 and the feedback loop to operational amplifier
212 is insignificant relative to I.sub.drive. This operation is
depicted as line 363b and line 363c of graph 351.
[0046] In contrast, where I.sub.sense becomes substantially lower
than I.sub.ref as would occur where drive load 232 is removed, a
voltage sufficient to swith FET 310 and FET 320 will exist at
output 333 of current input operational amplifier 330. In this
condition, the following equations approximately describe the
various currents in switched load system 300 where FET 214 is "n"
times larger than FET 262, and FET 320 is "n" times larger than FET
310: I.sub.load=nI.sub.sense; and
I.sub.ref=I.sub.sense+(1/n+1)I.sub.switch From these two equations,
the current supplied (I.sub.load) when drive load 232 is either
disconnected or becomes very large can be derived by solving for
I.sub.load as follows: Solving the preceding equations for
I.sub.load yields: I.sub.load=nI.sub.ref-(n/n+1)I.sub.switch This
current is depicted as line 363a and line 363d of graph 351. Where
n is large, the following equation provides a reasonable
approximation for I.sub.load: I.sub.load=nI.sub.ref This
establishes an approximate minimum current supplied by switched
load system 300 when drive load 232 is removed. As previously
stated, one of ordinary skill in the art will appreciate other
circuits that may be used to perform the functionality of amplifier
loop control 366. Such alternative circuits may provide different
minimum load currents and/or characteristics from those described
above and shown in relation to graph 351.
[0047] The invention has now been described in detail for purposes
of clarity and understanding. However, it will be appreciated that
certain changes and modifications may be practiced within the scope
of the appended claims. Thus, although the invention is described
with reference to specific embodiments and figures thereof, the
embodiments and figures are merely illustrative, and not limiting
of the invention. Rather, the scope of the invention is to be
determined solely by the appended claims.
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