Devore; Joseph A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Devore; Joseph A..The latest application filed is for "circuits, devices and methods for regulator minimum load control".

Company Profile

0.14.4

Devore; Joseph A. - Richardson TX
Devore, Joseph A. - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuits, devices and methods for regulator minimum load control Grant 7,554,309 - Carpenter, Jr. , et al. June 30, 2	2009-06-30
Circuits, devices and methods for regulator minimum load control App 20060261793 - Carpenter; John H. JR. ; et al.	2006-11-23
MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication Grant 6,940,131 - Baldwin , et al. September 6, 2	2005-09-06
MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication App 20050007216 - Baldwin, David John ; et al.	2005-01-13
Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors Grant 6,600,205 - Carpenter, Jr. , et al. July 29, 2	2003-07-29
Internal protection circuit and method for on chip programmable poly fuses Grant 6,469,884 - Carpenter, Jr. , et al. October 22, 2	2002-10-22
Low voltage transistors with increased breakdown voltage to substrate App 20020145173 - Carpenter, John H. JR. ; et al.	2002-10-10
Low voltage transistors with increased breakdown voltage to substrate Grant 6,376,870 - Carpenter, Jr. , et al. April 23, 2	2002-04-23
EEPROM cell using conventional process steps App 20010038120 - Marshall, Andrew ; et al.	2001-11-08
MOSFET predrive circuit with independent control of the output voltage rise and fall time, with improved latch immunity Grant 6,268,755 - Summerlin , et al. July 31, 2	2001-07-31
Heat spreader Grant 6,236,098 - Efland , et al. May 22, 2	2001-05-22
High breakdown-voltage transistor with transient protection Grant 6,169,309 - Teggatz , et al. January 2, 2	2001-01-02
Optimized power output clamping structure Grant 5,812,006 - Teggatz , et al. September 22, 1	1998-09-22
Method for current ballasting and busing over active device area using a multi-level conductor process Grant 5,801,091 - Efland , et al. September 1, 1	1998-09-01
Non-volatile memory in power and linear integrated circuits Grant 5,710,515 - Teggatz , et al. January 20, 1	1998-01-20
Device having current ballasting and busing over active area using a multi-level conductor process Grant 5,665,991 - Efland , et al. September 9, 1	1997-09-09
Reducing the natural current limit in a power MOS device by reducing the gate-source voltage Grant 5,541,799 - Schmidt , et al. July 30, 1	1996-07-30
Sensed current driving device Grant 5,408,141 - Devore , et al. April 18, 1	1995-04-18

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.