U.S. patent application number 11/461031 was filed with the patent office on 2006-11-23 for integrated circuit device with treated perimeter edge.
This patent application is currently assigned to Micron Technology,Inc.. Invention is credited to Aaron Schoenfeld.
Application Number | 20060261445 11/461031 |
Document ID | / |
Family ID | 25166211 |
Filed Date | 2006-11-23 |
United States Patent
Application |
20060261445 |
Kind Code |
A1 |
Schoenfeld; Aaron |
November 23, 2006 |
INTEGRATED CIRCUIT DEVICE WITH TREATED PERIMETER EDGE
Abstract
An integrated circuit die and method of fabricating the same.
The method comprises further grinding, polishing or otherwise
treating one or more perimeter edges of an individual circuit die.
The perimeter edges are treated to remove a substantial portion of
the remaining substrate material layer or scribe therefrom without
exposing the active circuitry of the die. The process reduces the
overall length and width dimensions of a die producing a smaller
circuit die without reducing the amount of circuitry on the
die.
Inventors: |
Schoenfeld; Aaron; (Boise,
ID) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology,Inc.
|
Family ID: |
25166211 |
Appl. No.: |
11/461031 |
Filed: |
July 31, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09785006 |
Feb 16, 2001 |
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11461031 |
Jul 31, 2006 |
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09137521 |
Aug 20, 1998 |
6215172 |
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09785006 |
Feb 16, 2001 |
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08795693 |
Feb 4, 1997 |
6127245 |
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09137521 |
Aug 20, 1998 |
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Current U.S.
Class: |
257/618 |
Current CPC
Class: |
H01L 29/0657 20130101;
H01L 21/02076 20130101; Y10S 438/974 20130101 |
Class at
Publication: |
257/618 |
International
Class: |
H01L 29/06 20060101
H01L029/06 |
Claims
1. An integrated circuit die cut from a wafer of substrate
material, said die comprising: an active surface having a circuit
pattern formed thereon; an inactive surface opposite said active
surface; at least one perimeter edge; a layer of remaining
substrate material on said at least one perimeter edge; and wherein
at least a portion of said layer of remaining substrate material is
removed from said at least one perimeter edge of said integrated
circuit die.
2. The integrated circuit die of claim 1, further including a
bi-level step on said at least one perimeter edge.
3. The integrated circuit die of claim 1, further including a
perimeter edge surface substantially perpendicular to at least one
of the active and inactive surface and entirely contained within
the remaining substrate material, the perimeter edge surface having
a polished surface containing minimal defects and cut marks, and
having at least one portion of the perimeter edge surface within
five microns of at least one portion of the circuit pattern formed
on the active surface.
4. The integrated circuit die of claim 1, wherein said substrate
includes at least one of single crystal silicon, polycrystalline
silicon, amorphous silicon, epitaxial silicon, silicon on sapphire,
silicon on insulator, germanium, silicon-germanium,
gallium-arsenide, a III-V compound, silicon carbide, and
diamond.
5. A known good integrated circuit die cut from a wafer of
substrate material to a first length and first width, said die
comprising: an active surface having a circuit pattern formed
thereon; an inactive surface opposite said active surface; at least
one perimeter edge; a layer of remaining substrate material on said
at least one perimeter edge; and wherein at least a portion of said
layer of remaining substrate material removed from said at least
one perimeter edge of said integrated circuit die results in a
second length and a second width less than the first length and
first width.
6. The known good integrated circuit die of claim 5, further
including a perimeter edge surface substantially perpendicular to
the active surface and entirely contained within the remaining
substrate material, the perimeter edge surface having a polished
smooth surface containing minimal defects and cut marks, and having
at least one portion of the perimeter edge surface within five
microns of at least one portion of the circuit pattern formed on
the active surface.
7. The known good integrated circuit die of claim 6, wherein said
perimeter edge has a bi-level step with an upper portion of the
perimeter having a portion within five microns of the circuit
pattern, and a lower portion having a larger extent and being
further horizontally and vertically from the circuit pattern.
8. An integrated circuit assembly comprising a known good
integrated circuit die cut from a wafer of substrate material and
being mounted to a base, said die and said base encapsulated in a
plastic material, wherein said known good integrated circuit die
comprises: an active surface having a circuit pattern formed
thereon; an inactive surface opposite said active surface; at least
one perimeter edge; a layer of remaining substrate material on said
at least one perimeter edge; and wherein at least a portion of said
layer of remaining substrate material is removed from said at least
one perimeter edge of said integrated circuit die.
9. The integrated circuit assembly of claim 8, further including a
perimeter edge surface perpendicular to at least one of the active
and inactive surface and entirely contained within the remaining
substrate material, the perimeter edge surface having a polished
smooth surface having at least one portion of the perimeter edge
surface within five microns of at least one portion of the circuit
pattern formed on the active surface.
10. The integrated circuit assembly of claim 9, wherein said
perimeter edge has a bi-level step with an upper portion of the
perimeter having a portion within five microns of the circuit
pattern, and a lower portion having a larger extent and being
further horizontally and vertically from the circuit pattern.
11. A semiconductor die, comprising: a substrate that is one of cut
and sawed from a semiconductor wafer, having a first planar surface
having a first pair of orthogonal dimensions, having a first region
with active circuitry thereon having a second pair of orthogonal
dimensions smaller than the first pair, surrounded by an unused
buffer area second region having a first width from an edge of the
substrate to an edge of the first region; a second planar surface
opposite the first planar surface; and one or more planar perimeter
side surfaces disposed in the second region, each planar perimeter
side surface extending continuously perpendicular from the first
planar surface to the second planar surface.
12. The semiconductor die of claim 11, wherein each planar
perimeter side surface of the semiconductor die comprises a flat
polished smooth surface with a top portion of each individual
planar perimeter side surface disposed in the second region and
having a first width of less than five microns from an edge of the
first region to an edge of the substrate.
13. The semiconductor die of claim 11, wherein the semiconductor
die has a substantially rectangular shape.
14. The semiconductor die of claim 11, wherein the second region is
substantially crystal defect free, and the one or more planar
perimeter side surfaces disposed in the second region are smooth as
an unused portion of the top surface of the semiconductor
wafer.
15. A semiconductor die, comprising: a planar surface having a
first region with active circuitry thereon surrounded by an unused
buffer area second region; a plurality of perimeter side surfaces
disposed in the second region, each having two portions extending
perpendicular to the planar surface and having at least one portion
disposed parallel to, but displaced vertically from the planar
surface; and a top portion of an upper one of the two perpendicular
portions disposed within five microns of an edge of a portion of
the active circuitry of the first region.
16. The semiconductor die as recited in claim 15, wherein the
semiconductor die comprises a shape having four substantially right
angles.
17. The semiconductor die as recited in claim 15, wherein a side
surface of the upper one of the two perpendicular portions has a
substantially flat surface with a smoothness equivalent to the
surface smoothness of an unused portion of the top planar
surface.
18. A semiconductor die comprising: a substrate having a
substantially flat and smooth top planar surface having a first
region with active circuitry thereon surrounded by a second region;
a substantially flat bottom planar surface opposite the first
planar surface; four perimeter sides disposed in the second region
extending between the top planar surface and the bottom planar
surface; each perimeter side having two offset perimeter planar
surfaces perpendicular to the top planar surface, where the two
offset perimeter planar surfaces are substantially parallel to each
other and offset in a horizontal direction from one another; each
perimeter side having a top one of the two offset perimeter planar
surfaces extending from the top planar surface to an intermediate
point, the bottom one of the two offset perimeter planar surfaces
extending from the bottom planar surface to the intermediate point,
and each of the offset perimeter planar surfaces is connected to
the other by a third surface oriented in a horizontal direction at
the intermediate point and parallel to the top planar surface.
19. The semiconductor die as recited in claim 18, wherein a top
edge portion of the top of the two offset perimeter planar surfaces
is disposed in the second region within approximately 5 microns of
an edge of the first region.
20. The semiconductor die as recited in claim 18, wherein a top one
of the two offset perimeter planar surfaces has a flat surface with
a surface variation smoothness equivalent to the surface smoothness
of an unused portion of the top planar surface.
21. The semiconductor die as recited in claim 18, wherein both a
top and a bottom one of the two offset perimeter planar surfaces
has a flat surface with a surface variation smoothness equivalent
to the surface smoothness of an unused portion of the top planar
surface.
Description
RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 09/785,006, filed Feb. 16, 2001, which is a continuation of
U.S. application Ser. No. 09/137,521, filed Aug. 20, 1998, now
issued as U.S. Pat. No. 6,215,172, which is division of U.S.
application Ser. No. 08/795,693, filed Feb. 4, 1997, now issued as
U.S. Pat. No. 6,127,245, which applications are incorporated herein
by reference.
TECHNICAL FIELD OF THE INVENTION
[0002] The present invention relates generally to the manufacturing
of integrated circuits and in particular the present invention
relates to a grinding technique for preparing integrated circuit
dies for further assembly process steps.
BACKGROUND OF THE INVENTION
[0003] Fabrication of integrated circuit assemblies involves a
complicated process including many steps. Depending on the desired
product, the steps may vary from manufacturer to manufacturer and
vary for different types of circuits. The basic process includes
producing an ingot of a substrate material such as silicon having a
highly crystalline structure. The ingot is cut into a number of
thin wafers which are further ground and polished producing smooth
and flat surfaces and smooth edges preferably free from defects
such as notches, chips or other surface flaws.
[0004] Each wafer is then subjected to a number of intricate
process steps to form a plurality of the integrated circuit
patterns on one side defining an active circuitry surface. Each
wafer is divided or cut into a large number of circuit dies which
will eventually be added to integrated circuit assemblies during
further process steps. Each die is precisely cut from the wafer to
leave a layer of substrate material or scribe on the edges of the
dies. Individual dies may be back ground to remove some of the
substrate from the inactive surface. The scribe material is left on
the edges to protect the active circuitry from damage during
further processing steps and to prevent short circuits between the
die and another active circuit or lead.
[0005] Today's rapidly advancing technology is producing a need for
ever smaller and more densely packed circuits and circuitry. The
smaller circuits make producing functional and flawless circuits
more difficult. There is a continuing need to improve the process
to provide a flawless, high quality integrated circuit having more
active circuits and to do so in a smaller package.
[0006] For the reasons stated above, and for other reasons stated
below, which will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for an improved process of manufacturing integrated
circuits which are smaller in size and more reliable than
conventionally manufactured components.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a schematic depiction of the typical steps
involved in a conventional integrated circuit manufacturing
process;
[0008] FIG. 2 is a top plan view of an integrated circuit die prior
to undergoing the grinding technique of the invention;
[0009] FIG. 3 is a top plan view of the integrated circuit die of
FIG. 2 after undergoing the grinding technique of the
invention;
[0010] FIG. 4 is an elevated perspective view of an integrated
circuit assembly including the die of FIG. 3 prior to encapsulation
of the assembly in plastic;
[0011] FIG. 5 is an elevated perspective view of the integrated
circuit assembly of FIG. 4 after encapsulation; and
[0012] FIG. 6 is a side view of an integrated circuit die having
bi-level edges produced using grinding techniques of the
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0013] In the following detailed description of the preferred
embodiments, reference is made to the accompanying drawings which
form a part hereof, and in which is shown by way of illustration
specific preferred embodiments in which the inventions may be
practiced. These embodiments are described in sufficient detail to
enable those skilled in the art to practice the invention, and it
is to be understood that other embodiments may be utilized and that
logical, mechanical and electrical changes may be made without
departing from the spirit and scope of the present inventions. The
following detailed description is, therefore, not to be taken in a
limiting sense, and the scope of the present inventions is to be
defined only by the appended claims.
[0014] The basic process for fabricating integrated circuits is
known in the art and is illustrated in the simple schematic
representation of FIG. 1. An ingot of silicon crystal is produced
by refining a raw material, such as quartzite, by a complex
multi-stage process to produce an electronic grade polysilicon
substance. The substance is used to grow single crystal silicon
ingots by one of several known processes. The silicon crystal ingot
is then sliced into a number of very thin wafers producing the
starting substrate for an integrated circuit.
[0015] Each wafer is then ground, polished or otherwise treated to
produce very smooth, flat substrate surfaces and smooth, flawless
edges. One process typically used to finish or treat the wafers is
known as chemical mechanical planarization or CMP which is well
understood in the art. Each wafer is then individually processed
through a number of steps to form the active circuit patterns on
one surface of the wafer. These steps may include adding or
depositing material on the wafer, masking out a pattern on the
wafer, etching a pattern on the wafer and other methods well known
in the art. At the time of this writing, for example, a typical
wafer may be about 150-200 mm (6-8 in) in diameter and about
0.25-0.50 mm (10-20 mils or 0.01-0.02 in) thick.
[0016] The wafers are then evaluated to locate and identify any
flawed or damaged circuits. The wafers may then, as an option, be
further tested to determine which individual dies are "known good
dies" as known to those skilled in the art. Once the active
circuitry is formed, the wafer is sawed or diced into a number of
integrated circuit dies. The functional dies are then picked off of
the wafer and used to produce integrated circuit assemblies. The
dies are bonded to a circuit substrate material, leads are attached
or formed and connected to the circuitry, and the entire assembly
is then further encapsulated in a plastic material to produce a
final integrated circuit assembly. The present invention is
directed to an improved integrated circuit die and a process for
forming the die, the process including the further manufacturing
step of grinding, polishing or otherwise treating one or more of
the perimeter edges of an individual die. The invention enhances
the further integrated circuit process and assembly steps to
produce a more durable die of either a smaller size or having a
denser circuitry with more circuitry per unit volume of die
substrate material.
[0017] Referring now to the drawings, FIG. 2 illustrates a top plan
view of an integrated circuit die after it has been cut or sawed
from a silicon wafer. FIG. 3 illustrates the integrated circuit die
after undergoing the additional manufacturing process steps of the
invention. As shown in FIG. 2, circuit die 10 includes active
circuitry 12 embedded in the silicon material and formed in layers
on an active surface 14 of the die. Die 10 further includes a
bottom or inactive surface 16 (shown in FIG. 6) opposite the active
surface which abuts a surface of a substrate 17 to which the die is
bonded in a later process step. FIGS. 4 and 5 illustrate an
integrated circuit assembly prior to encapsulation (FIG. 4) and
after encapsulation in plastic (FIG. 5). Die 10 also includes at
least one perimeter edge 18 and will likely include four such
edges. As illustrated in FIG. 4, a typical integrated circuit die
10 is generally rectangular.
[0018] As shown in FIG. 2, the active circuitry 12 of die 10
terminates inboard from each perimeter edge 18 of the die. The
circuitry terminates at a last metal interconnect 20 defining the
outer active circuitry limits for the die. A layer of remaining
scribe material 22 is purposely left protecting the active
circuitry 12 on the perimeter edges 18 to prevent open or short
circuits and malfunctions within the circuitry and to protect the
circuitry from damage during further process and assembly steps. As
noted previously, back grinding the die to reduce and flatten the
substrate material layer on the inactive surface 16 is known.
[0019] As is illustrated in FIG. 2, the unused buffer of silicon or
scribe 22 typically has a microscopically rough surface forming a
plurality of chips, nicks or other irregularities 24 on the surface
and edges of the die. The depth and frequency of these
irregularities will depend on many parameters in the formation of
the die. Particularly, the sharpness of the blades used to saw each
wafer from the ingot of silicon material and to saw each die from a
particular wafer has an effect. Other factors which affect the
surface quality of the die include the temperature of the blade
coolant utilized during the cutting operations and also the speed
of the rotating saw blade.
[0020] One problem caused by the irregularities 24 on the perimeter
edges 18 of the die is that they produce weak points in the silicon
or other substrate material. The weak points may ultimately form
cracks in the substrate material as the die undergoes further
process and assembly steps. A crack in the die may produce unwanted
open or short circuits or otherwise damage the active circuitry 12
rendering the die non-functional or defective.
[0021] An additional problem with the remaining scribe 22 is that
it inherently increases the width and length dimensions of each die
10. Another problem with a conventional integrated circuit die as
shown in FIG. 2 is that the perimeter edges 18 do not have an
extremely flat finish which is highly desirable in known good die
applications. Additionally, some substrate materials used to
produce integrated circuits such as gallium arsenide or GaAs are
more susceptible to surface flaws and edge damage than other
substrate materials.
[0022] FIG. 3 illustrates integrated circuit die 10 after
undergoing the additional steps of the invention. The layer of
remaining scribe 22 as it was prior to reduction is illustrated in
phantom view in FIG. 3 (and also in FIG. 6 which is discussed
below). The invention involves further removing the layer of
remaining scribe 22 on the die and also increasing the smoothness
and flatness of the perimeter edges 18 of a die. After separating a
wafer into a plurality of dies, each die is further ground or
polished by the process of the invention to remove a substantial
amount of the remaining scribe 22 and reduce or eliminate any
irregularities 24 in the edges 18. Thus, a die which has a smaller
length and width and which has much smoother and flatter edges is
produced.
[0023] As an illustrative example, a die may have a layer of
material on each edge which is about 25-50 .mu.m (1-2 mils) thick.
This will increase both the length and the width of a die about
50-100 .mu.m (2-4 mils). The process of the invention is intended
to remove most of this layer of material, leaving only enough
material to prevent exposure of the active circuitry of the die. A
size reduction of nearly 100 .mu.m in length and width may be quite
significant in some applications.
[0024] Reducing or eliminating irregularities 24 eliminates or at
least substantially reduces the possibility of cracks forming in
the unused substrate material surrounding the die during further
process and assembly steps. Thus, the occurrence of cracks and open
or short circuits in the active circuitry of the die is also
prevented or substantially reduced.
[0025] Additionally, removing most of the remaining scribe and
reducing the size of the die allows for one of two conditions to be
used to significantly improve integrated circuit assemblies. The
invention may be utilized to produce a slightly smaller die having
the identical circuit density. Typically, very precise design
constraints exist for the outer dimensions of integrated circuit
assemblies and also for the minimum amount of plastic encapsulating
material required to surround an integrated circuit. In some cases,
the integrated circuit die size is nearly as large as the size
limit of the final package design criteria, leaving little room for
the encapsulating plastic material. By removing scribe material via
the process of the invention, more encapsulation material may be
added without increasing the size of the assembly. Thus, a
particular die having the desired circuitry may be utilized in a
package where it would have otherwise been too large.
[0026] Another embodiment of the present invention is illustrated
in FIG. 6. A die 50 is shown having bi-level perimeter edges 52 and
54. The bi-level edge 52 is formed by polishing or grinding down
one portion 56 of the side edge to reduce the layer of material of
that portion. The remaining portion of edge 52 has been left as
initially formed on the die producing the stepped or dual thickness
bi-level edge 52. Bi-level edge 54 is produced by grinding or
polishing an entire edge to reduce the layer of scribe material to
a first level 58 and then further grinding one portion 60 of the
edge more than the remaining portion of the same edge. Bi-level
edge 54 includes the preferred benefit of having the entirety of
each edge subjected to the process of the invention and not just a
portion of each edge.
[0027] The additional step of grinding or polishing an integrated
circuit die 10 according to the invention may be performed using
one of several known processes and methods. For illustration
purposes, the CMP process will be briefly described. A circuit die
may be held by a carrier and forced against a rotary grinding disc
or polishing pad. The pad or disc is typically impregnated with a
chemical or abrasive slurry which contacts the die edge to remove a
portion of the scribe from the edges 18 as the pad or disc rotates.
Alternatively, a mechanical gripping device such as a "tweezer"
type device may be used to hold the die with an edge 18 adjacent
the polishing pad or grinding disc. As will be evident to those
skilled in the art, the invention is not to be limited to a
particular process of performing the grinding technique of the
invention, but only to the steps as described for further removing
some of the remaining scribe from the edges and surfaces of an
integrated circuit die.
[0028] The problems with present wafer manufacturing technology and
other problems are addressed by the present invention and which
will be understood by reading and studying the specification. A
method of producing an integrated circuit die of improved
reliability, durability and dimensional characteristics is
described, which is useful in the process of fabricating integrated
circuit assemblies and the like.
[0029] In particular, one method of an embodiment of the invention
adds an additional step to the conventional manufacturing process
for integrated circuits. A die which has been cut from a wafer is
further ground, polished or otherwise treated to remove a portion
of the remaining substrate or scribe layer on at least a portion of
the edge of the die. Another method of an embodiment of the
invention includes further grinding or polishing the entire
perimeter edge of a particular die to remove a portion of the
remaining scribe layer thereon. Another method of an embodiment of
the invention includes the additional step of grinding or polishing
a bi-level edge on at least a portion of the perimeter edge of a
die. The bi-level edge may be produced in one of two ways. Some of
the remaining scribe material may be removed from part of the die's
perimeter edge to produce the bi-level edge. Alternatively, the
entire edge may be partly ground or polished and then further
grinding or polishing a portion of the scribe to produce the
bi-level edge. This method creates a bi-level or stepped edge on
the die. Such a bi-level edge may be produced on the entire
perimeter edge or just a portion of the perimeter edge.
[0030] The methods disclosed produce an integrated circuit die
which is slightly smaller in length and width than a conventionally
produced die. The method further produces a die which is less
susceptible to damage such as edge chipping or die cracking. A chip
in the edge of a die produces a weak point in its edge which may
cause the die to crack during further processing or assembly steps.
Such a flaw or chip may also cause a short or otherwise damage the
active circuitry of the die.
[0031] The invention may be utilized to produce a slightly smaller
die having the same circuit capacity as a die which has not
undergone the process of the invention. A smaller die may be useful
in applications where one previously would have been too large
taking up too much space within an integrated circuit assembly.
Alternatively, the invention may be used to produce a die having
increased circuit capacity with no size increase. In particular,
some electronic packages require integrated circuit assemblies of a
particular maximum size including the plastic encapsulation
material. A die which has had most of the remaining scribe removed
from the edges saves length and width permitting a die having more
circuit capacity to be used within an application without
increasing the size of the assembly.
[0032] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. Therefore, it is manifestly intended that
this invention be limited only by the claims and the equivalents
thereof
* * * * *