U.S. patent application number 11/487093 was filed with the patent office on 2006-11-09 for method of forming polysilicon layers in a transistor.
This patent application is currently assigned to Hynix Semiconductor, Inc.. Invention is credited to Kai-Cheng Chou, Peter Rabkin, Hsingya Arthur Wang.
Application Number | 20060252193 11/487093 |
Document ID | / |
Family ID | 25540782 |
Filed Date | 2006-11-09 |
United States Patent
Application |
20060252193 |
Kind Code |
A1 |
Rabkin; Peter ; et
al. |
November 9, 2006 |
Method of forming polysilicon layers in a transistor
Abstract
A semiconductor transistor which is not capable of storing data
is formed as follows. An insulating layer is formed over a silicon
region. An undoped polysilicon layer is formed over and in contact
with the insulating layer. A doped polysilicon layer is formed over
and in contact with the undoped polysilicon layer such that at
least two edges of the doped polysilicon layer vertically line up
with corresponding edges of the undoped polysilicon layer to
thereby form sidewalls, and the doped and undoped polysilicon
layers form a gate of the transistor. After the doped polysilicon
layer is formed, source and drain regions are formed in the silicon
region. Dopants from the doped polysilicon layer migrate into the
undoped polysilicon layer thereby doping the undoped polysilicon
layer.
Inventors: |
Rabkin; Peter; (Cupertino,
CA) ; Wang; Hsingya Arthur; (San Jose, CA) ;
Chou; Kai-Cheng; (San Jose, CA) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
Hynix Semiconductor, Inc.
Kyoungki-do
KR
|
Family ID: |
25540782 |
Appl. No.: |
11/487093 |
Filed: |
July 13, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10870285 |
Jun 16, 2004 |
|
|
|
11487093 |
Jul 13, 2006 |
|
|
|
09994545 |
Nov 26, 2001 |
6812515 |
|
|
10870285 |
Jun 16, 2004 |
|
|
|
Current U.S.
Class: |
438/197 ;
257/E21.209; 257/E29.129; 257/E29.154; 438/488; 438/564 |
Current CPC
Class: |
H01L 29/7883 20130101;
H01L 29/4916 20130101; H01L 29/40114 20190801; H01L 29/42324
20130101 |
Class at
Publication: |
438/197 ;
438/488; 438/564 |
International
Class: |
H01L 21/336 20060101
H01L021/336; H01L 21/22 20060101 H01L021/22 |
Claims
1. A method of forming a semiconductor transistor, comprising:
forming an insulating layer over a silicon region; forming an
undoped polysilicon layer over and in contact with the insulating
layer; forming a doped polysilicon layer over and in contact with
the undoped polysilicon layer such that at least two edges of the
doped polysilicon layer vertically line up with corresponding edges
of the undoped polysilicon layer to thereby form sidewalls, the
doped and undoped polysilicon layers forming a gate of the
transistor; and after the doped polysilicon layer forming act,
forming source and drain regions in the silicon region, wherein
dopants from the doped polysilicon layer migrate into the undoped
polysilicon layer thereby doping the undoped polysilicon layer, and
the semiconductor transistor is not capable of storing data.
2. The method of claim 1 wherein the insulating layer is a gate
oxide layer.
3. The method of claim 1 wherein a thickness of the doped
polysilicon layer is greater than a thickness of the undoped
polysilicon layer by a factor in the range of two to four.
4. The method of claim 1 further comprising: forming insulating
spacers along the sidewalls of the doped and undoped polysilicon
layers.
5. The method of claim 1 wherein said doped polysilicon layer
forming act comprises depositing an in-situ doped polysilicon
layer.
6. The method of claim 1 wherein the transistor is any one of a
NMOS transistor, PMOS transistor, enhancement transistor, and
depletion transistor.
7. The method of claim 1 wherein the doped polysilicon layer has a
doping concentration and a thickness greater than a thickness of
the undoped polysilicon layer so as to prevent polysilicon
depletion in the gate.
8. The method of claim 1 further comprising: forming a conductive
layer comprising tungsten over and in contact with the doped
polysilicon layer.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is a division of U.S. application Ser. No.
10/870,285, filed Jun. 16, 2004, which is a division of U.S.
application Ser. No. 09/994,545, filed Nov. 26, 2001, each of which
is incorporated herein by reference in its entirety for all
purposes.
BACKGROUND OF THE INVENTION
[0002] FIG. 1a shows a cross section view of a conventional
stacked-gate non-volatile memory cell 100 at an intermediate
processing stage. Cell 100 has a polysilicon (gate) stack which
includes floating gate 106 and control gate 110 insulated from each
other by a composite oxide-nitride-oxide (ONO) dielectric layer
108. A tungsten layer (WSi.sub.x) 112 overlies control gate 110.
Floating gate 106 is insulated from the underlying silicon
substrate 102 by a tunnel oxide layer 104. FIG. 1b shows a cross
section view of cell 100 after formation of: (a) oxide spacers
116-a, 116-b along sidewalls of the gate stack, and (b) source
region 114-a and drain region 114-b in substrate 102.
[0003] A simplified conventional process sequence to form memory
cell 100 includes: forming tunnel oxide layer over substrate 102;
depositing a first layer polysilicon over the tunnel oxide layer;
forming an interpoly composite ONO dielectric layer over the first
layer polysilicon; depositing a second layer polysilicon over the
ONO dielectric; forming a tungsten silicide layer over the second
layer polysilicon; and self-aligned mask and self-aligned etch
(SAE) to form the gate stack as shown in FIG. 1a. In modern
technologies, the control gate is often formed simultaneously with
the gates of peripheral (CMOS) transistors, followed by cell
self-aligned etch (SAE) of the first layer polysilicon and the ONO
dielectric using the control gate as a mask. After formation of the
gate stack, in some processes, polysilicon re-oxidation is
performed. DDD mask and implant steps are then carried out to form
the cell source DDD region (if for example a source DDD region is
employed) and DDD regions for peripheral high voltage (HV) NMOS and
PMOS transistors. Next, cell source/drain mask and implant steps
are carried out to form cell source and drain regions 114-a, 114-b,
followed by oxidation and anneal cycles. LDD mask and implant steps
may then be carried out to form LDD junctions for the low voltage
(LV) NMOS and PMOS transistors. Spacers (e.g., spacers 16-a, 116-b
in FIG. 1b) are then formed along sidewalls of the gate stack in
the cell and along the side-walls of the gates of the periphery
transistors. This is followed by N.sup.+ and P.sup.+ mask and
implant steps to complete the junction formation of the peripheral
transistors.
[0004] The first and second polysilicon layers are deposited by
means of Chemical Vapor Deposition (CVD). Both first and second
polysilicon layers are in-situ doped (usually by phosphorus P31) to
a relatively high level (e.g., 2.times.10.sup.19 to
5.times.10.sup.20 cm.sup.-3). The level of polysilicon doping is
usually controlled by gas flow rate and pressure of the gas
compound containing P31, such as PH3. An example of a set of
parameters associated with the polysilicon deposition of a
conventional process is provided below. TABLE-US-00001 PH3 flow
Thickness Temperature; SiH4 flow rate; Pressure; Target; .ANG.
.degree. C. rate; sccm sccm mTorr Rs; .OMEGA./.quadrature. 600-1000
580-620 1200-1400 80-120 350-450 200-1000
[0005] There are a number of reasons for the high polysilicon
doping. First, the high doping prevents or minimizes polysilicon
depletion when gate bias is applied to the control gate of the
memory cell or to the gate of the MOS transistor. Polysilicon
depletion decreases gate capacitance thus reducing gate control in
a MOS transistor channel region, and impairs other transistor/cell
electrical characteristics. Second, the high doping helps maintain
a proper value of polysilicon work function which impacts such
important transistor/cell parameters as the threshold voltage.
Third, the high doping reduces the world line resistance in the
memory array, thus improving the memory performance. Fourth, the
high doping reduces time delay associated with the peripheral
transistor gate capacitance and resistance.
[0006] However, there are also drawbacks to the high polysilicon
doping. The high doping leads to higher oxidation rate of
polysilicon crystals. Higher oxidation rate in turn leads to a more
pronounced "smiling" effect, i.e., an increased gate oxide
thickness at the edges of the gate in MOS transistors, and similar
increase of tunnel oxide thickness and ONO dielectric at the edges
of the cell gate stack as shown in FIG. 1b by circles marked by
reference numerals 118 and 120. Although some minimal "smiling"
effect can serve a useful reliability purpose by rounding corners
of polysilicon thus reducing the electric field peak at polysilicon
edges, excessive "smiling" effect impairs gate control of the
channel and the drive current of MOS transistors. In memory cells,
a pronounced "smiling" effect of ONO dielectric impairs gate
coupling ratio, gate channel control, and program, erase, and read
efficiency.
[0007] A further drawback of the high doping is that it leads to a
larger polysilicon grain size which in turn leads to a more rugged
interface between the gate oxide and the polysilicon gate in MOS
transistors, and similarly between each of the tunnel oxide and the
floating gate, bottom of the ONO dielectric and the floating gate,
and top of the ONO dielectric and the control gate in a memory
cell. In extreme cases, it may lead to gate oxide and/or tunnel
oxide pinch-off or otherwise impact the integrity and reliability
characteristics of the gate oxide in MOS transistors and the tunnel
oxide and the ONO dielectric in memory cells.
[0008] In conventional processes, the room to achieve the necessary
trade-off between the desirable and undesirable effects of the
polysilicon doping is limited to only regulating the level of
doping and uniformity of the doping profile across the polysilicon
layers. Achieving the desired trade off thus often proves to be a
difficult task from process and device optimization point of
view.
[0009] Accordingly, there is a need for polysilicon layers
structure and method of forming the same whereby an optimum
polysilicon doping profile can be achieved, the depletion of the
polysilicon and its associated adverse effects are prevented or
minimized, the quality and uniformity of the polysilicon-oxide
interface are improved, while the "smiling" effect in the
dielectric layers interfacing polysilicon is minimized.
BRIEF SUMMARY OF THE INVENTION
[0010] In accordance with an embodiment of the present invention, a
semiconductor transistor which is not capable of storing data is
formed as follows. An insulating layer is formed over a silicon
region. An undoped polysilicon layer is formed over and in contact
with the insulating layer. A doped polysilicon layer is formed over
and in contact with the undoped polysilicon layer such that at
least two edges of the doped polysilicon layer vertically line up
with corresponding edges of the undoped polysilicon layer to
thereby form sidewalls, and the doped and undoped polysilicon
layers form a gate of the transistor. After the doped polysilicon
layer is formed, source and drain regions are formed in the silicon
region. Dopants from the doped polysilicon layer migrate into the
undoped polysilicon layer thereby doping the undoped polysilicon
layer.
[0011] In one embodiment, the insulating layer is a gate oxide
layer.
[0012] In another embodiment, a thickness of the doped polysilicon
layer is greater than a thickness of the undoped polysilicon layer
by a factor in the range of two to four.
[0013] In another embodiment, insulating spacers are formed along
the sidewalls of the doped and undoped polysilicon layers.
[0014] In another embodiment, the doped polysilicon layer is formed
by depositing an in-situ doped polysilicon layer.
[0015] In another embodiment, the transistor is any one of a NMOS
transistor, PMOS transistor, enhancement transistor, and depletion
transistor.
[0016] In yet another embodiment, the doped polysilicon layer has a
doping concentration and a thickness greater than a thickness of
the undoped polysilicon layer so as to prevent polysilicon
depletion in the gate.
[0017] In another embodiment, a conductive layer comprising
tungsten is formed over and in contact with the doped polysilicon
layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIGS. 1a and 1b show cross section views of a conventional
stacked-gate non-volatile memory cell at different processing
stages;
[0019] FIG. 2 shows a cross section view of a stacked-gate
non-volatile memory cell at an intermediate processing stage, in
accordance with one embodiment of the present invention;
[0020] FIG. 3a shows a cross section view of a variation of the
FIG. 2 memory cell structure in accordance with another embodiment
of the present invention;
[0021] FIG. 3b shows a cross section view of the cell structure of
FIG. 3a after source/drain formation, side-wall spacers formation,
and all thermal oxidation and anneal cycles;
[0022] FIGS. 4a, 4b, 4c show cross section views of an MOS
transistor at two different processing stages in accordance with an
embodiment of the present invention; and
[0023] FIG. 5 shows an exemplary doping profile through the
floating gate in FIG. 3a.
DETAILED DESCRIPTION OF THE INVENTION
[0024] In accordance with an embodiment of the present invention,
conventional semiconductor device structures wherein a doped
polysilicon layer comes in contact with an insulating layer, such
as silicon-dioxide, are modified so that the polysilicon layer
comprises a doped and an undoped polysilicon layer with the undoped
polysilicon layer interfacing with the insulating layer. In this
manner, the drawbacks of the prior art structures wherein doped
polysilicon layers are in direct contact with insulating layers are
minimized or eliminated while the advantages of a doped polysilicon
are maintained, as discussed in more detail below.
[0025] FIG. 2 shows a cross section view of a stacked-gate
non-volatile memory cell 200 at an intermediate processing stage,
in accordance with an embodiment of the present invention. Memory
cell 200 includes a tunnel oxide 204 over a silicon substrate 202.
Floating gate 206 which comprises two polysilicon layers 206-a,
206-b overlies tunnel oxide 204. A composite oxide-nitride-oxide
(ONO) dielectric layer 208 insulates floating gate 206 from an
overlying control gate 210. Control gate 210 comprises two
polysilicon layers 210-a, 210-b, and in some processes, is overlaid
by a tungsten (WSi.sub.x) layer 212. As shown, of the two
polysilicon layers forming floating gate 206, the lower layer 206-a
is doped while the upper layer 206-b is undoped, and of the two
polysilicon layers forming control gate 210, the lower layer 210-a
is undoped while the upper layer 210-b is doped. In this manner,
ONO dielectric 208 is sandwiched between two undoped polysilicon
layers 206-b and 210-a.
[0026] In one embodiment, the structure of FIG. 2 is formed as
follows. Tunnel oxide 204 is formed over substrate 202 in
accordance with conventional methods. In forming floating gate 206,
two successive polysilicon deposition steps are carried out. First,
an in-situ doped polysilicon deposition is performed to deposit
doped polysilicon layer 206-a, followed by an undoped polysilicon
deposition step to deposit undoped polysilicon layer 206-b. The
polysilicon doping concentration (using for example phosphorus P31
as the dopant) is controlled by temperature and gas (e.g. PH3) flow
rate and pressure, and the thickness of each polysilicon layer is
controlled by deposition time and temperature.
[0027] After deposition of polysilicon layers 206-a, 206-b,
interpoly ONO dielectric 208 is formed in accordance with
conventional methods. Next, in forming control gate 210, two
successive polysilicon deposition steps are performed. First, an
undoped polysilicon deposition step is carried out, followed by an
in-situ doped polysilicon deposition step.
[0028] The tables below show the temperature, gas flow rate and
pressure, doping concentration, and polysilicon thickness for each
of the doped and undoped polysilicon layers in accordance with an
exemplary embodiment of the present invention. This table reflects
a thickness ratio of doped polysilicon to undoped polysilicon of in
the range of 2:1 to 5:1, with a preferred ratio of 3:1. Note that
the values in these tables are merely illustrative and not intended
to be limiting. Varying these values to achieve the target
parameters and the desired cell performance would be obvious to one
skilled in this art in view of this disclosure. TABLE-US-00002
Doped Polysilicon Thickness Temperature; SiH4 flow PH3 flow
Pressure; Doping con. target; cm.sup.-3 target; .ANG. .degree. C.
rate; sccm rate; sccm mTorr 2 .times. 10.sup.19-1 .times. 10.sup.20
450-750 580-620 1200-1400 50-100 350-450
[0029] TABLE-US-00003 Undoped Polysilicon Thickness Temperature;
SiH4 flow PH3 flow target; .ANG. .degree. C. rate; sccm rate; sccm
Pressure; mTorr 150-250 580-620 1200-1400 0 350-450
[0030] After deposition of the polysilicon layers in forming
control gate 210, a tungsten (WSi.sub.x) layer 212 is optionally
deposited in accordance with conventional methods. In some
processes, an ARC oxynitride layer (not shown) is deposited over
the tungsten layer to complete gate layer formation. This is
followed by gate mask and gate etch to form the control gate of the
memory cell and the gate of peripheral transistors, and then
self-aligned mask and self-aligned etch (SAE) is carried out to
form the gate stack as it appears in FIG. 2. All subsequent steps,
including source/drain formation and side-wall spacer formation,
are carried out in accordance with conventional methods.
[0031] During thermal oxidation and anneal cycles, such as ONO
steam anneal (after ONO deposition), polysilicon re-oxidation after
gate stack formation, and source/drain oxidation cycle(s), the top
and bottom oxide layers in ONO dielectric 208 at the periphery of
the gate stack (side walls) grow at a lower rate due to the lower
oxidation rate of undoped polysilicon layers which interface the
two oxide layers. Thus, ONO dielectric "smiling" effect is
substantially reduced. The tunnel oxide "smiling" effect can
similarly be reduced by including another undoped polysilicon layer
as the bottom polysilicon layer of the floating gate. This is shown
in the FIG. 3a embodiment. An undoped polysilicon layer 306-c forms
the bottom layer of floating gate 306, interfacing tunnel oxide
304.
[0032] Other than the reduction in "smiling" effect, the smaller
grain size of undoped polysilicon yields a polysilicon-oxide
interface which is more uniform leading to improved tunnel oxide
and ONO dielectric quality and integrity. Further, by selecting
proper doping concentration in the doped polysilicon layers and
proper thickness ratio between adjacent doped and undoped
polysilicon layers, by the end of the thermal cycles, a uniform and
high enough doping concentration can be achieved throughout the
whole floating gate and control gate so as to prevent polysilicon
depletion effects.
[0033] By the end of the oxidation/anneal thermocycle, depending on
the thermal budget, the impurity (e.g., phosphorus) profile in the
undoped polysilicon layers may be of diffusion character. FIG. 5
shows an exemplary impurity profile through floating gate 306 in
FIG. 3a. The horizontal axis represents the impurity concentration,
and the vertical axis represents the dimension along the stack,
from top to bottom, of ONO dielectric 308, floating gate 306, and
tunnel oxide 304. Solid lines 510, 512, 514 indicate the impurity
concentration in the respective undoped polysilicon layer 306-b,
undoped polysilicon layer 306-c, and doped polysilicon layer 306-a
before carrying out the thermal cycles. The dashed, curved line 516
shows the impurity profile through the three polysilicon layers
after the thermal cycles. Note that even though polysilicon layers
306-b, 306-c are undoped, they acquire some impurities during their
deposition process. Solid lines 510 and 512 represent this impurity
concentration before the thermal cycles are carried out.
[0034] After the thermal cycles, as shown by dashed line 516, the
impurity concentration is highest in the doped polysilicon layer
306-a and gradually reduces at the boundaries between the doped and
undoped polysilicon layer and through the undoped polysilicon
layers 306-b, 306-c, and reaches its lowest concentration level at
the interface between the undoped polysilicon layers 306-b, 306-c
and the corresponding tunnel oxide 304 and ONO dielectric layer
308. The thickness of the polysilicon layers and the thermocycles
need to be optimized such that the final polysilicon doping
concentration and its gradient at the polysilicon-dielectric
interface is high enough to prevent or minimize polysilicon
depletion effects.
[0035] Note that despite the high final doping concentration at the
polysilicon-dielectric interface, the benefits of using undoped
polysilicon layers are maintained. The diffusion of dopants from
the doped polysilicon layer to the undoped polysilicon layers
occurs slowly during the thermocycles. Thus, because the doping
concentration at the polysilicon-dielectric interface is relatively
low during a significant part of the oxidation processes, a reduced
smiling effect is achieved. At the same time, the undoped
polysilicon layers retain smaller size and more uniform grain
structure, resulting in better uniformity and quality of
polysilicon-dielectric interface.
[0036] FIG. 3b shows the cell structure of FIG. 3a after
source/drain 314-a, 314-b and side-wall spacers 316-a, 316-b
formation and all thermal oxidation and anneal cycles. As shown, by
using multi-layers of doped/undoped polysilicon in both the
floating gate and the control gate, the "smiling" effect (shown by
circles 118 and 120 in FIG. 1b) is reduced.
[0037] Accordingly, by providing a combination of doped and undoped
polysilicon layers in each of the floating gate and the control
gate, a more flexible process is obtained whereby much of the
adverse effects associated with the trade-offs in the polysilicon
doping concentration present in conventional processes is
eliminated. By providing undoped polysilicon at the dielectric
interfaces, an ONO dielectric and a tunnel oxide layer having
uniform thicknesses and improved dielectric quality and integrity
are achieved while a high enough doping concentration in most of
the floating gate and the control gate is maintained. Also, after
all the thermal cycles, a relatively homogeneous polysilicon doping
across the whole floating gate and control gate is obtained.
Further, the tunnel oxide and the ONO dielectric are more uniform
both in terms of their geometrical thickness and in terms of their
dielectric quality and integrity. High uniformity of tunnel oxide
and ONO result in better gate control over the channel, higher
coupling ratio between the control gate and the floating gate,
enhanced program, erase, and read efficiency, tighter erase
distribution, and allow use of lower operating voltages. Further
the improved quality of the ONO dielectric and tunnel oxide results
in improved charge retention characteristics and overall
reliability of the memory cell. Thus, a memory cell with a much
improved electrical and reliability characteristics is
achieved.
[0038] FIGS. 4a, 4b, 4c show cross section views of a MOS
transistor at two different processing stages in accordance with
another embodiment of the present invention. In FIG. 4a, gate oxide
404 is formed over substrate 402 in accordance with conventional
methods. Next, two successive polysilicon deposition steps are
carried out in forming transistor gate 406. First, an undoped
polysilicon layer is deposited in forming undoped polysilicon layer
406-a, followed by an in-situ doped polysilicon deposition step in
forming doped polysilicon layer 406-b. Similar to the above memory
cell embodiments, the polysilicon doping concentration (using for
example phosphorus P31 as the dopant) is controlled by temperature
and gas (e.g. PH3) flow rate and pressure, and the thickness of
each polysilicon layer is controlled by deposition time and
temperature.
[0039] All subsequent processing steps are carried out in
accordance with conventional methods. FIGS. 4b and 4c show two
different cross sections of the transistor structure after
source/drain 408-a, 408-b formation, side-wall spacers 410-a, 410-b
formation, and all thermal oxidation and anneal cycles. FIG. 4b
shows the cross section of the transistor along the gate length of
the transistor, and FIG. 4c shows the cross section of the
transistor along the gate width of the transistor through the
channel region (the transistor width is the size of active area
between two isolation areas).
[0040] As shown, by using the doped/undoped polysilicon layers, the
"smiling" effect is reduced not only at the outer edges of gate
oxide 404 near the drain and source regions (FIG. 4b), but also at
the periphery of the active and isolation areas 440-a, 440-b (FIG.
4c). Although the increase in the thickness of the gate oxide at
the transitional area between the active and isolation regions is
mainly determined by the so called "bird's beak" effect of the
isolation regions (which is stronger for LOCOS isolation and
smaller for shallow trench isolation), high polysilicon doping of
the gate in conventional processes, and the resulting "smiling"
effect, results in an even thicker gate oxide at the transitional
areas. Controlling the polysilicon doping at the gate oxide
interface minimizes the contribution to the thicker gate oxide by
the "smiling" effect, and thus improves transistor performance
(gate control, drive current). This is especially advantageous for
short active width devices. More importantly, the smaller grain
size and uniformity of grain structure in the initially undoped
polysilicon layer helps improve uniformity and quality of
polysilicon-oxide interface and gate oxide thickness, leading to
improved reliability.
[0041] The MOS transistor polysilicon gate can be formed
simultaneously (i.e., using the same mask step) with the control
gate of the memory cell. That is, the same two successive
deposition steps in forming an undoped polysilicon layer followed
by a doped polysilicon layer may be carried out to simultaneously
form the control gate of the memory cells and the gate of periphery
transistors. In another embodiment, the MOS transistor polysilicon
gate can be formed simultaneously with the floating gate rather
than with the control gate. In the memory cell embodiment wherein
the floating gate comprises three polysilicon layers (FIG. 3a), the
top undoped polysilicon layer is not useful in the periphery
transistor, but may be present if a sufficiently uniform final
doping could be obtained. In yet another embodiment, the gate of
the peripheral transistors is formed simultaneously with the
combined floating gate and control gate polysilicon layers. This
embodiment, as in many flash EPROM processes, requires that the
interpoly ONO dielectric be removed from the periphery.
[0042] The present invention is not limited in application to MOS
transistors and stacked gate non-volatile memories. Any structure
wherein doped polysilicon comes in contact with an insulating layer
can benefit from the doped/undoped multi-layer polysilicon approach
described herein. Examples of other structures include N-channel or
P-channel non-volatile memory cells such as ROM, EPROM, EEPROM, and
flash EEPROM cells, volatile memory cells such as DRAM and SRAM
cells, NMOS and PMOS transistors, and depletion and enhancement
transistors. Further, the present invention is not limited to any
specific parameters or values indicated herein. For example, the
values indicated in the tables above correspond to one particular
process and set of targets, and may be varied to accommodate other
processes and cell technologies.
[0043] While the above is a complete description of preferred
embodiments of the present invention, it is possible to use various
alternatives, modifications, and equivalents. Therefore, the scope
of the present invention should be determined not with reference to
the above description but should, instead, be determined with
reference to the appended claims, along with their full scope of
equivalents.
* * * * *