U.S. patent application number 11/454812 was filed with the patent office on 2006-10-19 for high density direct connect loc assembly.
Invention is credited to Trung T. Doan.
Application Number | 20060231940 11/454812 |
Document ID | / |
Family ID | 21834089 |
Filed Date | 2006-10-19 |
United States Patent
Application |
20060231940 |
Kind Code |
A1 |
Doan; Trung T. |
October 19, 2006 |
High density direct connect LOC assembly
Abstract
An apparatus and method for attaching a semiconductor die to a
lead frame wherein the electric contact points of the semiconductor
die are relocated to the periphery of the semiconductor die through
a plurality of conductive traces. A plurality of leads extends from
the lead frame over the conductive traces proximate the
semiconductor die periphery and directly attaches to and makes
electrical contact with the conductive traces in a LOC arrangement.
Alternately, a connector may contact a portion of the conductive
trace to make contact therewith.
Inventors: |
Doan; Trung T.; (Boise,
ID) |
Correspondence
Address: |
TRASK BRITT
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
21834089 |
Appl. No.: |
11/454812 |
Filed: |
June 15, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11109133 |
Apr 5, 2005 |
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11454812 |
Jun 15, 2006 |
|
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|
10366769 |
Feb 14, 2003 |
6882033 |
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11109133 |
Apr 5, 2005 |
|
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|
09649803 |
Aug 28, 2000 |
6531761 |
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10366769 |
Feb 14, 2003 |
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09026839 |
Feb 20, 1998 |
6335225 |
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09649803 |
Aug 28, 2000 |
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Current U.S.
Class: |
257/686 ;
257/692; 257/E23.024; 257/E23.039; 257/E23.048; 257/E23.146 |
Current CPC
Class: |
H01L 2224/0556 20130101;
H01L 2224/0556 20130101; H01L 23/525 20130101; H01L 2924/00014
20130101; H01L 2224/02379 20130101; H01L 2224/85399 20130101; H01L
24/05 20130101; H01L 2924/00014 20130101; H01L 2924/14 20130101;
H01L 2224/04042 20130101; H01L 2224/05599 20130101; H01L 2924/01005
20130101; H01L 2924/01014 20130101; H01L 2924/00014 20130101; H01L
24/48 20130101; H01L 2924/0002 20130101; H01L 2224/4826 20130101;
H01L 2924/01082 20130101; H01L 2224/05554 20130101; H01L 2924/01033
20130101; H01L 2224/06136 20130101; H01L 2224/48091 20130101; H01L
2224/48091 20130101; H01L 2924/0002 20130101; H01L 24/06 20130101;
H01L 23/4951 20130101; H01L 2224/85399 20130101; H01L 24/72
20130101; H01L 2924/01013 20130101; H01L 2924/00014 20130101; H01L
23/522 20130101; H01L 2924/00014 20130101; H01L 2224/05552
20130101; H01L 2224/45099 20130101; H01L 2224/05599 20130101; H01L
2924/00012 20130101 |
Class at
Publication: |
257/686 ;
257/692; 257/E23.048 |
International
Class: |
H01L 23/52 20060101
H01L023/52 |
Claims
1. An assembly comprising: a semiconductor die having a periphery
and an active surface having a plurality of electric contact points
disposed on the active surface; and a plurality of conductive
traces on the active surface, each conductive trace of the
plurality of conductive traces comprising a first end electrically
contacting at least one electric contact point of the plurality of
electric contact points and a second end terminating proximate the
semiconductor die periphery, each conductive trace comprising a
trace of extruded conductive material on the active surface between
the at least one semiconductor die electric contact point making
contact therewith and the periphery of the semiconductor die.
2. The assembly of claim 1, further comprising a plurality of leads
of a lead frame resiliently connected to and in electrical
communication with portions of the second ends of the plurality of
conductive traces.
3. The assembly of claim 1, wherein the semiconductor die comprises
one semiconductor die of a plurality of semiconductor dice on a
wafer.
4. A plurality of semiconductor dice on a wafer, comprising: a
plurality of semiconductor dice located on the wafer, each
semiconductor die having a periphery and an active surface with at
least one electric contact point disposed on the active surface;
and at least one conductive trace on the active surface, the at
least one conductive trace comprising a first end electrically
contacting the at least one semiconductor die electric contact
point and a second end terminating proximate the semiconductor die
periphery, the at least one conductive trace comprising a trace of
extruded conductive material on the active surface between the at
least one electric contact point making contact therewith and the
periphery of the semiconductor die to expose a portion of the at
least one conductive trace at a portion of the periphery of the
semiconductor die.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No.
11/109,133, filed Apr. 5, 2005, pending, which is a continuation of
application Ser. No. 10/366,769, filed Feb. 14, 2003, now U.S. Pat.
No. 6,882,033, issued Apr. 19, 2005, which is a continuation of
application Ser. No. 09/649,803, filed Aug. 28, 2000, now U.S. Pat.
No. 6,531,761, issued Mar. 11, 2003, which is a divisional of
application Ser. No. 09/026,839, filed Feb. 20, 1998, now U.S. Pat.
No. 6,335,225, issued Jan. 1, 2002.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to an apparatus and method for
attaching a semiconductor die to a lead frame or other type of
connector. More particularly, the present invention relates to
relocating electric contact points of a semiconductor die to the
periphery of the semiconductor die through a plurality of
conductive traces. The leads of the lead frame extend over the
conductive traces proximate the semiconductor periphery and
directly attach to and make electrical contact with the conductive
traces in a variety of arrangements or configurations. Alternately,
a connector may be used to contact a portion of the end of a
conductive trace located at the periphery of a semiconductor
die.
[0004] 2. State of the Art
[0005] Higher performance, lower cost, increased miniaturization of
components, and greater packaging density of integrated circuits
are goals of the computer industry. Greater integrated circuit
density is primarily limited by the space or "real estate"
available for mounting a semiconductor die on a substrate such as a
printed circuit board. Conventional lead frame design inherently
limits package density for a given semiconductor die size because
the die-attach paddle of the lead frame must be larger than the die
to which it is bonded. The larger the semiconductor die, the less
space that remains around the periphery of the die-bonding pad for
wire bonding. Furthermore, the wire bonding pads on the standard
lead frame provide anchorage for the leads when the leads and the
semiconductor die are encapsulated in plastic. Therefore, as the
die size is increased in relation to a given package size, there is
a corresponding reduction in the space along the sides of the
package for the encapsulating plastic which joins the top and
bottom of the plastic body at the mold part line and anchors the
leads. Thus, as the leads and encapsulant are subjected to the
normal stresses of subsequent forming and assembly operations, the
encapsulating plastic may crack, compromising package integrity and
substantially increasing the probability of premature device
failure.
[0006] Also, since lead frames are designed for use with a
semiconductor die having a specific pattern of bond pads located on
the active surface thereof, it is desirable to have the flexibility
of changing the bond pad locations of a die so that an existing
lead frame design may be used with differing types of die
material.
[0007] For example, one method of chip attachment which reduces the
die size is a so-called "leads-over-chip" ("LOC") arrangement.
Conventional LOC devices have a plurality of leads disposed on and
attached to an active surface of a semiconductor die, thus the name
leads-over-chip. A primary advantage of LOC is that the ratio
between the size of the semiconductor die and the size of a package
which encapsulates the semiconductor die is high. This advantage is
achieved because the die-attach paddle is not required since the
semiconductor die is instead attached to the leads.
[0008] U.S. Pat. No. 4,862,245 issued Aug. 29, 1989 to Pashby et
al. ("the '245 patent") illustrates a LOC arrangement on a
semiconductor die (see FIG. 10). The leads 16 are extended over a
semiconductor die 10 toward a central or axial line of bond pads 14
wherein bond wires 12 make the electrical connection between the
inner ends of leads 16 and the bond pads 14. In wire bonding, the
bond wires 12 are attached, one at a time, to each bond pad 14 on
the semiconductor die 10 and extend to a corresponding lead or
trace end 16 on a lead frame or printed circuit board (not shown).
The bond wires 12 are generally attached through one of three
industry-standard wire bonding techniques: ultrasonic bonding,
using a combination of pressure and ultrasonic vibration bursts to
form a metallurgical cold weld; thermocompression bonding, using a
combination of pressure and elevated temperature to form a weld;
and thermosonic bonding, using a combination of pressure, elevated
temperature, and ultrasonic vibration bursts. Film-type alpha
barriers 18 are provided between the semiconductor die 10 and the
leads 16, and are adhered to both, thus eliminating the need for a
separate die paddle or other die support aside from the leads 16
themselves. The configuration of the '245 patent assists in
limiting the ingress of corrosive environmental contaminants to the
active surface of the die, achieves a larger portion of the circuit
path length encapsulated in the packaging material applied after
wire bonding, and reduces electrical resistance caused by the bond
wires 12 by placing the lead ends in closer proximity to the bond
pads 14 (i.e., the longer the bond wire, the higher the
resistance). Although this configuration offers certain advantages,
it requires that bond wires 12 be individually attached between the
bond pads 14 and the leads 16. Bond wires have an inherent problem
called bond wire sweep. When encapsulating a bare die assembly, the
die assembly is generally placed in a mold with a molten encasing
material being injected into the mold whereby the encasing material
surrounds the die assembly and the material conforms to the mold.
However, this process causes stresses on the bond wires. Since the
molten encasing material is viscous, it tends to place directional
forces on the bond wires as the encasing material is injected into
the mold. These directional forces cause the bond wires to stretch,
which can, in turn, cause the bond wires to short with adjacent
bond wires or bond pads or be pulled from a bond pad or lead to
which the wires are bonded.
[0009] U.S. Pat. No. 5,252,853 issued Oct. 12, 1993 to Michii
illustrates a LOC arrangement on the semiconductor die which does
not use bond wires (see FIG. 11). The leads 22 are extended over a
semiconductor die 20 toward centrally located bond pads 24 (shown
in shadow). The leads 22 extend to a position over their respective
bond pads 24 wherein the leads 22 are bonded directly to their bond
pads 24 with TAB attachment. Although this direct bonding of the
lead to the bond pad eliminates the need for wire bonding, it still
requires lengthy leads to make electrical contact between the bond
pads and the lead frame. Film-type alpha barriers 26 are also
provided between the semiconductor die 20 and the leads 22.
[0010] Therefore, it would be advantageous to develop a technique
and a device for increasing integrated circuit density by reducing
lead width and reducing bond pad size, using non-complex lead frame
configurations and eliminating bond wires, while using commercially
available, widely practiced semiconductor device fabrication
techniques.
BRIEF SUMMARY OF THE INVENTION
[0011] The present invention relates to an apparatus and method for
attaching a semiconductor die to a lead frame or other type of
connector, such as a clip type. Electric contact points of the
semiconductor die of the present invention are relocated to the
periphery of a semiconductor die and are in electrical contact with
a lead frame or connector. The semiconductor die may be in
electrical contact with a lead frame through at least one lead
which extends over and directly attaches to its respective electric
contact point on the semiconductor die periphery, or through one
lead which extends over and is attached to a die contact point with
electrical contact being made to the electrical contact point of
the die by means of a wire bond, or through one lead which extends
adjacent the edge of a die with electrical contact being made to
the electrical contact point of the die by means of a wire
bond.
[0012] The apparatus is constructed by first forming a
semiconductor die on a semiconductor wafer. A plurality of electric
contact points, such as bond pads, is disposed on an active surface
of the semiconductor die. A plurality of conductive traces is
formed on the semiconductor die active surface to make a conductive
route between each electric contact point and a position proximate
to the semiconductor die periphery. A plurality of edge electric
contact points may be formed on the periphery of the semiconductor
die active surface during the formation of the conductive
traces.
[0013] The conductive traces can be formed by a number of industry
standard techniques, such as: depositing a conductive material on
the active surface of the semiconductor die, patterning, and
etching the conductive material; depositing a conductive paste on
the semiconductor die active surface by silk screening the
conductive traces directly thereon; directly extruding a conductive
paste to form the conductive traces, or applying an insulative
material on the semiconductor die active surface, etching a trough
in the insulative material, filling the trough with a conductive
material, and removing the excess material. These methods are less
expensive than relocating the electric contact points during the
semiconductor die fabrication process.
[0014] Although the formation of the conductive traces is
preferably carried out on the semiconductor wafer, it is understood
that the traces can be formed on each semiconductor die after the
semiconductor dice have been cut from the semiconductor wafer.
[0015] After the electrical traces have been formed on the
semiconductor die and the semiconductor die has been cut from the
semiconductor wafer, a lead frame is attached to the semiconductor
die. In one instance, a plurality of leads from the lead frame is
attached directly to and forms an electrical contact with the edge
electric contact points of the semiconductor die. The direct
attachment of the leads eliminates the need for bond wires, which
reduces the cost of the apparatus. In another instance, a plurality
of leads from the lead frame is directly attached to the die with
electrical contact being made to the contact points of the
semiconductor die by means of wire bonds. In yet another instance,
a plurality of leads from the lead frame is terminated adjacent an
edge of the semiconductor die with electrical contact being made
with contact points of the semiconductor die by means of
connectors.
[0016] In one instance, since the present invention provides
neither a die-attach paddle nor a plurality of lengthy leads to
provide support for both the semiconductor die and attached lead
frame, the semiconductor device fabrication technique for the
semiconductor die of the present invention may have to be slightly
modified over present semiconductor device fabrication techniques
to ensure that no stresses on the lead frame attached semiconductor
die occur prior to the encapsulation step. Such a fabrication
technique modification may include providing clips on the lead
frame to hold the semiconductor die. Although modifying the
fabrication process is a disadvantage, the disadvantage is far
outweighed by the benefits realized by the present invention. Since
the leads are not required to provide support, they can be designed
to be narrower in width. The narrower lead width allows the edge
electric contact points to be smaller than relocated electrical
contact points. The smaller edge electric contact points allow the
semiconductor die size to be reduced or allow a greater number of
edge electric contact points to be placed on the semiconductor die
periphery. The narrower lead width also results in a smaller lead
pitch which serves to reduce the cost of the apparatus.
Furthermore, attachment of the leads at the semiconductor die
periphery eliminates the need for a film-type alpha barrier between
the semiconductor die and the lead, which further reduces the
semiconductor die cost.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0017] While the specification concludes with claims particularly
pointing out and distinctly claiming that which is regarded as the
present invention, the advantages of this invention can be more
readily ascertained from the following description of the invention
when read in conjunction with the accompanying drawings, in
which:
[0018] FIGS. 1a-1g are full and partial views of a first preferred
method of forming conductive traces on the semiconductor die of the
present invention in wafer form or individual die form;
[0019] FIGS. 2a-2c are partial views of a second preferred method
of forming conductive traces on the semiconductor die of the
present invention;
[0020] FIGS. 3a-3c are partial views of a third preferred method of
forming conductive traces on the semiconductor die of the present
invention;
[0021] FIGS. 4a-4d are partial views of a fourth preferred method
of forming conductive traces on the semiconductor die of the
present invention;
[0022] FIG. 5 is a top view of a lead arrangement of the present
invention;
[0023] FIG. 6 is a top view of a first alternative lead arrangement
of the present invention;
[0024] FIG. 7 is a view of an alternative connector arrangement of
the present invention;
[0025] FIG. 8 is a view of an alternative connector arrangement of
the present invention;
[0026] FIG. 9 is a view of an alternative connector arrangement of
the present invention;
[0027] FIG. 10 is a top view of a prior art semiconductor die
assembly using leads extending onto the semiconductor die and using
bond wires to connect the leads to the bond pads prior to the
encapsulation of the semiconductor die in a protective coating;
and
[0028] FIG. 11 is a top view of a prior art semiconductor die
assembly using leads extending onto the semiconductor die to
directly connect to the bond pads prior to the encapsulation of the
semiconductor die in a protective coating.
DETAILED DESCRIPTION OF THE INVENTION
[0029] FIGS. 1a-1g illustrate a first method of forming conductive
traces on a semiconductor die 100 of the present invention. FIG. 1a
illustrates a plurality of semiconductor die 100 located on a wafer
1000, each semiconductor die 100 having a periphery 101 defined, in
general, by the street areas 103 located therebetween of the wafer
1000. Each semiconductor die 100 has conductive traces 116 on an
active surface thereof connecting the bond pads 104 of the die to
the periphery 101 of the semiconductor die 100. FIG. 1b illustrates
a silicon substrate 102 having circuitry (not shown) disposed on an
active surface. The circuitry of the silicon substrate 102 receives
input and/or distributes output via bond pads 104 or electric
contact points disposed on the semiconductor die active surface. A
passivation layer 106 is generally applied over the semiconductor
die active surface with the bond pads 104 exposed. As shown in FIG.
1c, a layer of conductive material 108 is applied over the
passivation layer 106, making electrical contact with the bond pads
104. A layer of etch resist material 110 is applied over the layer
of conductive material 108, as shown in FIG. 1d. The etch resist
material layer 110 is then masked and etched to form a trace
pattern 112 which extends from the bond pads (not shown) to an edge
114 of the silicon substrate 102 and exposing a portion of the
conductive material layer 108, as shown in FIG. 1e. The conductive
material layer 108 is then etched, as shown in FIG. 1f, wherein the
trace pattern 112 acts as a mask to form a conductive trace 116
from the conductive material layer 108. As shown in FIG. 1g, the
trace pattern 112 is stripped to expose the conductive trace 116.
The conductive trace 116 may have a landing portion 118 proximate
to the silicon substrate edge 114. The landing portion 118 may be
slightly wider than the conductive trace 116 and serves as the
contact sight to attach a lead (not shown) from a lead frame (not
shown).
[0030] FIGS. 2a-2c illustrate a second method of forming conductive
traces on a semiconductor die 200 of the present invention. FIG. 2a
illustrates a silicon substrate 202 having circuitry (not shown)
disposed on an active surface. The circuitry of the silicon
substrate 202 receives input and/or distributes output via bond
pads or electric contact points 204 disposed on the semiconductor
die active surface. A passivation layer 206 is generally applied
over the semiconductor die active surface with the contact points
204 exposed. As shown in FIG. 2b, a silk screen 208 is placed over
the passivation layer 206. The silk screen 208 has a permeable
portion 210 in the shape of a desired conductive trace. The silk
screen permeable portion 210 allows a substantially liquid
conductive material to pass therethrough and attach to the
passivation layer 206 to form a conductive trace 212, as shown in
FIG. 2c, which makes electrical contact with the contact points 204
and extends to an edge 214 of the silicon substrate 202.
[0031] FIGS. 3a-3c illustrate a third method of forming conductive
traces on a semiconductor die 300 of the present invention. FIG. 3a
illustrates a silicon substrate 302 having circuitry (not shown)
disposed on an active surface. The circuitry of the silicon
substrate 302 receives input and/or distributes output via bond
pads or electric contact points 304 disposed on the semiconductor
die active surface. A passivation layer 306 is generally applied
over the semiconductor die active surface with the contact points
304 exposed. As shown in FIG. 3b, an extrusion nozzle 308 extrudes
a viscous conductive material 310 directly onto the passivation
layer 306. The viscous conductive material 310 forms a conductive
trace 312 between the contact points 304 and an edge 314 of the
silicon substrate 302, as shown in FIG. 3c.
[0032] FIGS. 4a-4d illustrate a fourth method of forming conductive
traces on the semiconductor die 400 of the present invention. FIG.
4a illustrates a silicon substrate 402 having circuitry (not shown)
disposed on an active surface. The circuitry of the silicon
substrate 402 receives input and/or issues output via bond pads or
electric contact points 404 disposed on the semiconductor die
active surface. A passivation layer 406 is generally applied over
the semiconductor die active surface with the contact points 404
exposed. As shown in FIG. 4b, a layer of etch resist material 408
is applied over the passivation layer 406. The etch resist material
layer 408 is then masked and etched to form a recessed conductive
trace pattern 410 which exposes the contact points 404 and extends
to an edge 412 of the silicon substrate 402, as shown in FIG. 4c. A
conductive material is disposed within the recessed conductive
trace pattern 410 which forms a conductive trace 414, as shown in
FIG. 4d.
[0033] FIG. 5 illustrates a semiconductor assembly 500 of the
present invention. The semiconductor assembly 500 comprises a lead
frame 502 having a plurality of leads 504 extending therefrom. The
leads 504 extend to a periphery 506 of semiconductor die 508
wherein the leads 504 extend over, directly attach to, and make
electrical contact with a plurality of respective conductive traces
510 which is attached to the semiconductor die 508. The conductive
traces 510 each terminate proximate to the semiconductor die
periphery 506 and extend to make electrical contact with a
plurality of bond pads or electrical contact points 512 (shown in
shadow) disposed on the semiconductor die 508.
[0034] FIG. 6 illustrates an alternative semiconductor assembly 600
of the present invention. The alternative semiconductor assembly
600 is similar to the semiconductor assembly 500 of FIG. 5;
therefore, components common to FIGS. 5 and 6 retain the same
numeric designation. The difference between the alternative
semiconductor assembly 600 and the semiconductor assembly 500 is
that the bond pads 602 are variably disposed on the semiconductor
die 508, rather than in linear rows, as shown in FIG. 5 for bond
pads 512. Thus, the conductive traces 604 for alternative
semiconductor assembly 600 are of variable shape and configuration
in order to route the conductive traces 604 to their appropriate
position on the semiconductor die periphery 506.
[0035] Referring to drawing FIG. 7, a semiconductor die 100 is
illustrated having a conductive trace 414 extending to the
periphery 101 of the semiconductor die 100. Making electrical
contact with a portion of the second end of the conductive trace
414 is a portion of a connector 700. The connector 700 resiliently
abuts the periphery 101 of the semiconductor die 100, making
contact with a portion of the second end of conductive trace 414.
The connector 700 may be any suitable type, such as a clip-type
connector, to resiliently engage the conductive trace 414 of the
semiconductor die 100. Any desired number of connectors 700 may be
used for such a purpose. Further, if desired, the connector 700 may
be resiliently biased through the use of springs, elastomers, etc.
in contact with conductive trace 414.
[0036] Referring to drawing FIG. 8, a connector 702 is illustrated
making contact with a portion of the second end of the conductive
trace 414 and a portion of the upper surface of the conductive
trace 414 adjacent the periphery 101 of the semiconductor die 100.
The connector 702 may be of any suitable type and may be used in
any desired number to connect the conductive traces 414 of the
semiconductor die 100 to a substrate. Further, the connector 702
may be resiliently biased into engagement with the conductive trace
414.
[0037] Referring to drawing FIG. 9, a connector 702 is illustrated
making contact with a portion of the second end of the conductive
trace 414 and a portion of the upper surface of the conductive
trace 414 adjacent the periphery 101 of the semiconductor die 100.
The connector 702 may be of any suitable type and may be used in
any desired number to connect the conductive traces 414 of the
semiconductor die 100 to a substrate 402. Also illustrated is a
portion 710 resiliently contacting the opposed surface 100N of the
semiconductor die 100 to resiliently bias the connector 702 into
contact with conductive trace 414. The portion 710 may be part of a
suitable connector or a portion of connector 702, etc. Alternately,
the portion 710 may bear against the exterior of connector 702
(shown in phantom lines) to bias the connector 702 against the
conductive trace 414 at the periphery 101 of the semiconductor die
100.
[0038] Having thus described in detail preferred embodiments of the
present invention, it is to be understood that the invention
defined by the appended claims is not to be limited by particular
details set forth in the above description as many apparent
variations thereof are possible without departing from the spirit
or scope thereof.
* * * * *