U.S. patent application number 11/393324 was filed with the patent office on 2006-08-17 for apparatus and methods for cooling semiconductor integrated circuit chip packages.
Invention is credited to Paul S. Andry, Evan G. Colgan.
Application Number | 20060180924 11/393324 |
Document ID | / |
Family ID | 36385396 |
Filed Date | 2006-08-17 |
United States Patent
Application |
20060180924 |
Kind Code |
A1 |
Andry; Paul S. ; et
al. |
August 17, 2006 |
Apparatus and methods for cooling semiconductor integrated circuit
chip packages
Abstract
Apparatus and methods are provided for integrating microchannel
cooling modules within high-density electronic modules (e.g., chip
packages, system-on-a-package modules, etc.,) comprising multiple
high-performance IC chips. Electronic modules are designed such
that high-performance (high power) IC chips are disposed in close
proximity to the integrated cooling module (or cooling plate) for
effective heat extraction. Moreover, electronic modules which
comprise large surface area silicon carriers with multiple chips
face mounted thereon are designed such that integrated silicon
cooling modules are rigidly bonded to the back surfaces of such
chips to increase the structural integrity of the silicon
carriers.
Inventors: |
Andry; Paul S.; (Yorktown
Heights, NY) ; Colgan; Evan G.; (Chesnut Ridge,
NY) |
Correspondence
Address: |
F. CHAU & ASSOCIATES, LLC
130 WOODBURY ROAD
WOODBURY
NY
11797
US
|
Family ID: |
36385396 |
Appl. No.: |
11/393324 |
Filed: |
March 30, 2006 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10987985 |
Nov 12, 2004 |
|
|
|
11393324 |
Mar 30, 2006 |
|
|
|
Current U.S.
Class: |
257/712 ;
257/E23.08; 257/E23.098; 257/E25.013 |
Current CPC
Class: |
H01L 25/0657 20130101;
H01L 2224/16225 20130101; H01L 2225/06589 20130101; H01L 2924/00011
20130101; H01L 2924/00014 20130101; H01L 2224/0401 20130101; H01L
2224/0401 20130101; H01L 2225/06517 20130101; H01L 2224/32245
20130101; H01L 2924/01019 20130101; H01L 2224/73253 20130101; H01L
2924/15311 20130101; H01L 2924/00014 20130101; H01L 23/473
20130101; H01L 2924/00011 20130101 |
Class at
Publication: |
257/712 ;
257/E23.08 |
International
Class: |
H01L 23/34 20060101
H01L023/34 |
Goverment Interests
GOVERNMENT RIGHTS
[0002] This invention was made with Government support under
Contract No. H98230-04-C-0920 awarded by the Maryland Procurement
Office. The Government has certain rights in this invention.
Claims
1. An electronic module, comprising: a first carrier substrate; a
second carrier substrate formed of silicon, which is bonded to the
first carrier substrate; a plurality of IC (integrated circuit)
chips flip-chip bonded to the second carrier substrate; a
microchannel cooling device formed of silicon, the microchannel
cooling device comprising a first surface that is thermally bonded
to a non active surface of each of the IC chips, the microchannel
cooling device having a plurality of coolant inlet and outlet
manifolds formed in a second surface opposite the first surface; a
package cap attached to the second surface of the microchannel
cooling device using a flexible seal, the package cap comprising
fluid distribution manifolds that are aligned to corresponding
inlet and outlet manifolds of the microchannel cooling device.
2. The electronic module of claim 1, wherein the first carrier
substrate comprises a ceramic package substrate.
3. The electronic module of claim 1, wherein the second carrier
substrate has a thickness of less than about 0.5 mm, and wherein
the second carrier substrate comprises electrical through vias.
4. The electronic module of claim 1, wherein the second carrier
substrate has a thickness in a range of about 50 microns to about
200 microns, and wherein the second carrier substrate comprises
electrical through vias.
5. The electronic module of claim 1, wherein a pitch of the
electrical interconnections between the second carrier substrate
and the IC chips is less than or equal to about 300 microns and
more preferably less than about 100 microns.
6. The electronic module of claim 1, wherein the first surface of
the microchannel cooling device is thermally bonded to the
non-active surface of each of the IC chips using rigid bonding
material.
7. The electronic module of claim 6, wherein the rigid bonding
material comprises solder, metal, silver filled epoxy, or a filled
polymer material.
8. The electronic module of claim 1, wherein the non-active surface
of one or more of the IC chips mounted on the second carrier
substrate is planarized prior to being bonded to the microchannel
cooling device.
9. The electronic module of claim 7, wherein a thickness of rigid
bonding material between the non-active surface of the chips and
the first surface of the microchannel cooling device is varied for
different chips in accordance with a thermal resistance required
for the IC chips.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a Divisional of U.S. patent application
Ser. No. 10/987,985, filed on Nov. 12, 2004, which is fully
incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
[0003] The present invention relates generally to apparatus and
methods for packaging semiconductor IC (integrated circuit) chips
with integrated cooling modules. More specifically, the present
invention relates to apparatus and methods for integrating
microchannel cooling modules within high-density chip packages and
system-on-a-package modules comprising multiple high-performance IC
chips.
BACKGROUND
[0004] In the design and manufacture of semiconductor IC chip
packages and modules (e.g., SCM (single chip modules), MCMs
(multi-chip modules), etc.), it is imperative to implement
mechanisms that can effectively remove heat generated by IC chips,
such as microprocessors or other high-performance chips, to ensure
continued reliable operation of the IC chips. Effective heat
removal becomes increasingly problematic as chip geometries are
scaled down and operating speeds are increased, which results in
increased power density. Moreover, as chip packages or electronic
modules become more compact with multiple IC chips densely packed
together, the increased heat density generated by operation of the
chips in such close proximity can adversely affect integrated
circuit components and cause physical damage to the package
structure due to differences in thermal expansion of the package
components. Accordingly, there is a continuing need for improved
devices and methods for effectively cooling high-density and/or
high-performance IC chip packages and modules.
[0005] One method of dense packaging of high performance chips,
known as "system on a package", uses a silicon carrier with
electrical through vias as an additional intermediate package layer
between the chips and a ceramic first level package to provide high
density and high performance electrical interconnects, such as
described in U.S. Pat. No. 6,593,644, entitled "System on a Package
Fabricated on a Semiconductor or Dielectric Wafer with Wiring on
One Face, Vias Extending Through the Wafer, and External
Connections on the Opposing Face," which is commonly assigned and
fully incorporated herein by reference. Packaging structures and
method described in this patent provide a number of significant
advantages, but one critical factor that should be considered for
practical implementations of package structures with silicon
carriers is the size and thickness of such silicon carriers. For a
silicon carrier to be useful, the carrier should be larger in size
than the size of the chip or chip array to be mounted on the
carrier. For example, the largest practical size for a high
performance chip is currently about 20 mm.times.20 mm . Therefore,
to mount a 2.times.2 array of such chips, the silicon carrier would
need to be over 40 mm.times.40 mm in size.
[0006] Another factor that is considered when using silicon
carriers in package structures is the thickness of the silicon
carrier. It is desirable to make the silicon carrier substrate as
thin as possible due the difficulties associated with forming
electrical through vias and filling the vias with a conductive
material and minimizing the inductance of the electrical
interconnects. For example, if a silicon carrier is 0.2 mm thick
and 40 mm wide, the width/thickness ratio is 200:1. As reported in
the literature, a practical silicon carrier thickness is primarily
limited by the ultimate aspect ratio of the through vias. In
general, aspect ratio values much higher than about 10:1 are
considered to be difficult to manufacture and make highly reliable.
By way of example, the consortium composed mainly of Japanese
Electronics companies known as the Association of Super-Advanced
Electronic Technologies (ASET) has worked intensively on silicon
carrier through-via technology for the past five years (see
Takahashi, K. et al., "Current Status of Research and Development
of Three-dimensional Chip Stacking Technology", Jpn. J. Appl. Phys.
Vol. 40, (2001) pp. 3032-3037), and such work has culminated in a
reportedly robust process employing 10 um wide vias and a carrier
thickness fixed at 50 um (see Takahashi, K. et al., "Process
Integration of 3D Chip Stack with Vertical Interconnection", Proc.
54th Electron. Components and Technol. Conf. Las Vegas, Nev., June
2004, pp. 601-609).
[0007] Some of the practical difficulties which occur with a large
area and thin silicon carrier include increased risk of fracturing
the silicon carrier during processing, bonding or assembly, as well
as providing an effective means for cooling the chips mounted on
the silicon carrier. It is difficult to use a conventional cooling
means such as a thermal paste layer and a heat sink attached to the
back surface of the chips since the force used to hold the heat
sink in place and the large force used during assembly to insure a
thin and uniform thermal paste layer could crack the silicon
carrier. Therefore, packaging structures and methods that provide
increased stiffness of a silicon carrier while providing a high
performance cooling solution are highly desirable.
SUMMARY OF THE INVENTION
[0008] Exemplary embodiments of the invention generally include
apparatus and methods for packaging semiconductor IC chips with
integrated cooling modules. More specifically, exemplary
embodiments of the invention include apparatus and methods for
integrating microchannel cooling modules within high-density
electronic modules (e.g., chip packages, system-on-a-package
modules, etc.,) comprising multiple high-performance IC chips.
[0009] In general, electronic modules according to exemplary
embodiments of the invention are designed such that
high-performance (high power) IC chips are disposed in close
proximity to an integrated cooling module (or cooling plate) for
effective heat extraction. More specifically, exemplary embodiments
of the invention include electronic modules which comprises an
integrated cooling module and high-performance IC chips bonded
directly to the cooling module. For instance, in one exemplary
embodiment of the invention, the non-active surface of an IC chip
can be rigidly bonded to a microchannel cooler device using solder,
silver filled epoxy, or similar filled polymer.
[0010] In other exemplary embodiments of the invention, electronic
modules are designed having a cooling module disposed between
carrier substrates having a plurality of IC chips mounted on the
carrier substrates. In such exemplary embodiments, high-performance
IC chips are mounted in surface regions of the carrier substrates
that are aligned with the cooling module. In other exemplary
embodiments of the invention, conductive vias can be formed through
the cooling module (e.g., in thermal microfins of a microchannel
cooler) to provide electrical signal paths across the cooling
module between the carrier substrates and/or the IC chips mounted
on the carrier substrates.
[0011] In another exemplary embodiment of the invention, an
electronic module comprises a first level carrier substrate and an
intermediate carrier substrate bonded to the first level carrier
substrate, wherein the intermediate carrier substrate comprises a
plurality of IC chips flip-chip bonded thereto. A cooling device,
such as a microchannel cooler, is thermally bonded to the
non-active surfaces of each IC chip mounted on the intermediate
carrier substrate using rigid bonding material. The cooling device
is formed of a material which is thermal expansion matched to the
material from which the intermediate substrate carrier is formed to
reduce mechanical stresses caused by differences in thermal
expansion. The microchannel cooling device provides cooling for the
chips and additionally increases the structural integrity of the
electronic assembly by rigidly bonding the microchannel cooler to
the back surfaces of IC chips mounted on the intermediate carrier.
Moreover, microchannel cooler is light weight and the bonding
material can be compatible with a C4 reflow, such that the
microchannel cooler could be assembled to the intermediate carrier
package with the IC chips before bonding the intermediate carrier
package to the first level package.
[0012] Exemplary packaging methods and structures according to the
invention may be used for building a compact computer
system-on-a-package comprising multiple IC processor chips, IC
memory chips, and communication chips and modules, which are
densely packed together with an integrated cooling module. In such
embodiments, the high-performance IC processor chips are disposed
in proximity to the integrated cooling module for efficient heat
extraction.
[0013] These and other exemplary embodiments, aspects, features,
and advantages of the present invention will become apparent from
the following detailed description of exemplary embodiments, which
is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a schematic perspective view of an electronic
module according to an exemplary embodiment of the invention.
[0015] FIG. 2 is a schematic perspective view of an electronic
module according to another exemplary embodiment of the
invention.
[0016] FIGS. 3A and 3B schematically illustrate a microchannel
cooling device which can be integrated within an electronic module
according to an exemplary embodiment of the invention.
[0017] FIG. 4 schematically illustrates a microchannel cooling
device which can be integrated within an electronic module
according to another exemplary embodiment of the invention.
[0018] FIG. 5 schematically illustrates an electronic module
according to another exemplary embodiment of the invention.
[0019] FIG. 6 schematically illustrates an electronic module
according to another exemplary embodiment of the invention.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENT
[0020] FIG. 1 is a schematic perspective view of an electronic
module according to an exemplary embodiment of the invention. FIG.
1 schematically illustrates an exemplary embodiment of an
electronic module (100) comprising an integrated cooling module
(101) (e.g., microchannel cooler) with high-performance IC chips
(102) and (103) bonded directly to the cooling module (101). The
cooling device (101) comprises a microchannel cooling device having
a plurality of coolant inlet/outlets (101a) to enable coolant to
flow in and out of the cooling device (101). In one exemplary
embodiment, the electronic module (100) comprises a computer
"system on a package" in a stacked chip structure, wherein the IC
chips (102) and (103) are processor chips (e.g., CPUs,
microprocessors, etc.). The back (non-active) surfaces of the IC
processor chips (102) and (103) are thermally coupled to opposite
surfaces of the cooling device (101). Furthermore, an array of IC
memory chips (104) and (105) are flip-chip bonded to the active
surface of the IC processor chips (102) and (103), respectively. It
is to be understood that depending on the application, the module
(100) can have any number and/or arrangement of IC memory chips
bonded to the IC processor chips (102) and (103).
[0021] The electronic module (100) further comprises separate CIO
(communication and input/output) modules (106) and (107) for
corresponding IC processor chips (102) and (103), respectively. The
CIO module (106) is connected to the IC processor chip (102) via an
array of vertical pins, or solder columns, (108) mounted
therebetween, and the CIO module (107) is connected to the IC
processor chip (103) via an array of vertical pins, or solder
columns, (109) mounted therebetween.
[0022] In one exemplary embodiment of the invention, each vertical
pin or solder column may be formed of two separate solder bumps,
wherein one solder bump originates on an IC processor chip and
another solder bump originates on a corresponding CIO module, thus
giving an effective "double bump" standoff height. Moreover, the IC
memory chips may be thinned considerably, e.g., to 100 microns
thick, using standard backside grind techniques, and the C4s used
to join the IC memory chips to the corresponding IC processor chips
may be reduced in height, making it possible to use more or less
standard bumping techniques to assemble the module (100).
[0023] The CIO modules (106) and (107) can be bonded thermally to
the non-active surfaces of the memory chips in IC memory chip
arrays (104) and (105), respectively, if the CIO modules (106) and
(107) need to dissipate heat through the memory chips and the IC
processor chips. Alternatively, if the power of the CIO modules
(106) and (107) are low, enabling heat to be easily dissipated to
the surroundings, the CIO modules (106) and (107) do not have to be
bonded to the respective memory chips of chip arrays (104) and
(105) to the memory chips.
[0024] The CIO modules (106) and (107) are constructed to include
the required electrical interconnects, bonding pads, integrated
circuits/devices, I/O components, etc., that enable electrical
connection/communication with other electronic components, devices,
modules, power sources, etc. The IC processor chips (102) and (103)
can directly communicate via a communication link provided by a
flexible cable (110). Each end of the cable (110) is soldered to
one of the IC processor chips (102) and (103) and disposed along
the side of the module (100).
[0025] With the exemplary package structure of FIG. 1, the cooling
device (101) is thermally coupled directly to IC processor chips
(102) and (103) to provide increased cooling capacity for the
module (100). Indeed, high-performance IC chips such as computer
processors typically have high average power densities and may
contain "hot spot" regions with increased (above-average) heat flux
(power/unit area). Directly connecting the IC processor chips (102)
and (103) to the cooling device (101) provides a low resistance
heat conduction path and enables increased cooling. Further, the IC
processor chips (102) and (103) are formed of a thermal conductive
material (e.g., silicon) and act as thermal heat spreaders for
extracting and conducting heat from the low-power density chips
(104) and (105) to the cooling module (101).
[0026] In one exemplary embodiment, the non-active surfaces of the
IC processor chips (102) and (103) are rigidly bonded to the
cooling device (101) using a silver filled epoxy, filled polymer
adhesive, filled thermoplastic or solder, or other thermally
conductive bonding material with low thermal resistance. To reduce
mechanical stresses, the material of the cooling device (101) is
selected to have a TCE (thermal coefficient of expansion) that
closely matches the TCE of the material of the IC processor chips
(102) and (103). The ability to effectively use a rigid bond is
limited not only by the difference in the TCEs of the materials
that form the cooling device (101) and the IC chips, but also on
the temperature range (cycle) in which the semiconductor package
will operate or be exposed to, as well as size of the area over
which the rigid bond will be formed.
[0027] In one exemplary embodiment, the cooling device (101)
comprises a microchannel cooling device having a plurality of
coolant inlet/outlets (101a) to enable coolant to flow in and out
of the cooling device (101). Microchannel cooling devices can be
implemented for effectively cooling electronic devices under
conditions of increased heat flux/high power densities (power/unit
area), e.g., .about.800 W/cm.sup.2. FIGS. 3A and 3B are schematic
diagrams that illustrate a microchannel cooling apparatus (300)
which can be implemented for the cooling device (101) of FIG. 1.
FIG. 3B illustrates a cross-sectional view of FIG. 3A along the
line 3B-3B. As shown, the exemplary microchannel cooling device
(300) comprises a planar substrate (301) (e.g., silicon substrate)
that is etched to form a recessed region (302) comprising a
plurality of parallel, microscopic heat conducting fins (303) which
define a plurality of channels (304). A second substrate (305)
(e.g., silicon substrate) (305), or cover plate, is bonded to the
etched surface of the substrate (301) and the tops of the fins
(303) thereby defining a chamber for the flow of a coolant (e.g.,
water) through the channels (304) between the inlets (I) and
outlets (O). Heat removal is achieved by thermal contact between
the fins (303) and the coolant fluid that flows through the
channels (304).
[0028] It is to be understood that the cooling device (300)
depicted in FIGS. 3A and 3B is merely one exemplary embodiment of
the cooling device (101) of FIG. 1, and that any suitable
microchannel cooling devices and methods known to those of ordinary
skill in the art may be implemented and customer designed for the
intended application. For instance, although the exemplary cooling
module (300) is depicted as having two inlet/outlet ducts, it is to
be understood that the number and orientation of the inlet/outlets
of the cooling device will vary depending on the particular design.
Moreover, the cooling device (300) may be formed to have two
separate chambers to allow coolant flowing inside the two chambers
in opposite directions.
[0029] FIG. 2 is a schematic perspective view of an electronic
module according to another exemplary embodiment of the invention.
FIG. 2 is one exemplary embodiment of an electronic module (200)
which is designed having a cooling module disposed between carrier
substrates having a plurality of IC chips mounted on the carrier
substrates. In particular, FIG. 2 schematically depicts an
electronic module (200) comprising a cooling device (201)
interposed between a first carrier substrate (202) and a second
carrier substrate (203) (e.g., silicon substrates). The cooling
device (201) comprises a microchannel cooling device having a
plurality of coolant inlet/outlets (201a) to enable coolant to flow
in and out of the cooling device (201). An exemplary embodiment of
the cooling device (201) will be discussed below with reference to
FIG. 4, for example.
[0030] In one exemplary embodiment, the electronic module (200)
comprises a computer "system on a package", wherein the first
carrier substrate (202) comprises an array of IC processor chips
(204) and arrays of IC memory chips (206) and (207) mounted on a
surface thereof, and the second carrier substrate (203) comprises
an array of IC processor chips (205) and arrays of IC memory chips
(208) and (209) mounted on a surface thereof. The high-performance
processor chip arrays (204) and (205) are mounted active area down
in surface regions of respective carrier substrates (202) and (203)
that are aligned with the cooling module (201). The carrier
substrates (202) and (203) comprise one or more levels of
metallization to provide the required conductive lines and
interconnections for signal transmission between the IC memory
chips and processor chips.
[0031] Moreover, in the exemplary embodiment of FIG. 2, the IC
memory chip in the arrays (206).about.(209) are vertically mounted
on the respective carrier substrates (202) and (203) to provide a
high density vertical chip package. In such embodiment, the IC
memory chips can be designed such that the signal and power
connections are formed on the edges of the IC memory chips that are
bonded to the substrates. Methods for vertically mounting IC chips
to carrier substrates are known to those of ordinary skill in the
art. For instance, the methods described in U.S. Pat. No.
4,266,282, entitled "Vertical Semiconductor Integrated Circuit Chip
Packaging", which is commonly assigned and fully incorporated
herein by reference, may be implemented for forming carrier
substrates (202) and (203) and vertically mounting the IC memory
chips thereto.
[0032] The electronic module (200) further comprises separate CIO
modules (210) and (211) for corresponding IC processor chip arrays
(204) and (205), respectively. The CIO module (210) is connected to
the carrier substrate (202) by soldering pins or solder columns
(212) and the CIO module (211) is connected to the second carrier
substrate (203) by soldering pins or solder columns (213).
Alternatively, the CIO modules (210) and (211) can be connected to
respective carrier substrates (202) and (203) using a pin and
socket connection, as is well known to those of ordinary skill in
the art. The CIO modules (210) and (211) are constructed to include
the required electrical interconnects, bonding pads, integrated
circuits/devices, I/O components, etc., that enable electrical
connection/communication with other electronic components, devices,
modules, power sources, etc.
[0033] In the exemplary embodiment of FIG. 2, the carrier
substrates (202) and (203) provide a thermal path for conducting
heat away from the IC processor chips and IC memory chips mounted
thereon to the cooling device (201). In one exemplary embodiment of
the invention, the carrier substrates (202) and (203) are formed
having a thickness in a range of about 50 microns to about 400
microns. The cooling device (201) is disposed between the carrier
substrates (202) and (203) in alignment with surface regions of
carrier substrates on which the IC processor chip arrays (204) and
(205) are mounted, where the heat density is the greatest. The
high-density IC memory chip arrays (206).about.(208) are disposed
in regions of the respective carrier substrates adjacent the
high-performance IC processor chip arrays, which extend past the
cooling device (201). The IC memory chips can be effectively cooled
by the heat spreading ability of the carrier substrates and the air
columns formed between the IC memory chips. The portions of the
carrier substrates (202) and (203) which extend past the cooling
device (201) are supported by respective mechanical support
structures (214) and (215).
[0034] In another exemplary embodiment, the cooling device (201)
can be made the same size as the carrier substrates (202) and
(203), in which case the mechanical support structures (214) and
(215) would not be needed. With this exemplary embodiment, since
the power dissipation rates are generally lower in the memory
regions, the cooling channels in the cooling device (201) can be
designed accordingly to handle higher power density in the
processor region and relatively lower power density in the memory
regions.
[0035] In one exemplary embodiment, the carrier substrates (202)
and (203) are rigidly bonded to the cooling device (201) using a
silver filled epoxy, filled polymer adhesive, filled thermoplastic
or solder, or other thermally conductive bonding material with low
thermal resistance. To reduce mechanical stresses in the thermal
interface between the cooling module (201) and carrier substrates
(202) and (203) due to thermal expansion/contraction, the material
of the cooling device (201) is selected to have a TCE that closely
matches the TCE of the material of the carrier substrates (202) and
(203). Moreover, mechanical stresses in the thermal interface
between the cooling device (201) and the carrier substrates (202)
and (203) are reduced by limiting the size of the cooling device
(201) to be aligned with only the high-performance IC processor
chips. In particular, the cooling device (201) is made smaller than
the carrier substrates (202) and (203) and thus, the surface area
over which the rigid bond (or other thermal interface) between the
cooling device and carrier substrates is limited (as compared to
forming the cooling device (201) to have the same planar dimensions
as the carrier substrates).
[0036] In another exemplary embodiment of the invention, the
cooling device (201) is constructed to have a plurality of
conducting through vias that provide connection paths between the
first and second carrier substrates (202) and (203). In this
exemplary embodiment, the surface regions of the carrier substrates
(202) and (203) that are aligned with the cooling module (201) have
bonding pads/connectors that can be bonded (via solder balls) to
exposed portions of the conducting through vias (or other
interconnects) on the respective mating surfaces of the cooling
module (201) to provide electrical connections between IC chips on
the different silicon carriers. Moreover, thermal conduction from
the high performance processor chip arrays (204) and (205) to their
respective silicon carriers (202) and (203) can be enhanced by
filling the empty space among the solder ball bonds between the
processor chips and silicon carriers as much as possible with
additional solder balls (i.e. thermal via's) and by using a
thermally conductive, and electrically insulating, underfill
material. Additional structures to reduce the thermal conductivity
in the silicon carriers and in the chip metallization levels can be
formed, aligned with the additional solder balls, as is known to
those of ordinary skill in the art.
[0037] It is to be appreciated that in one exemplary embodiment
when the IC memory chips and carrier substrates (202) and (203) are
made from silicon (or other TCE matched materials) the area density
of the individual solder connections may be increased and/or the
height of solder connections may be reduced to provide a further
reduction in thermal resistance from the IC memory chip arrays
(204) and (205) to the respective carrier substrates (202) and
(203). Indeed, it is advantageous to keep the thermal resistance as
small as possible to avoid a large delta T, which is the leading
factor in chip-to-carrier stress (assuming matched TCEs). This
approach is useful with high-density micro joins with pitches as
low as "1 on "2" mil.
[0038] FIG. 4 schematically illustrates one exemplary embodiment of
the cooling device (201) of FIG. 2, which has electrically
conducting vias formed through the cooling module to provide
electrical signal paths between silicon carriers (202) and (203).
In particular, FIG. 4 depicts a microchannel cooling device (400)
according to an exemplary embodiment of the invention, which
comprises a substrate (401) (e.g., silicon substrate) that is
etched to form a coolant chamber having microchannel pattern with
multiple channel walls (402) and narrow channels (403) formed by
the conventional silicon etching technology. A plurality of
conductive through vias (404) are formed inside the channel walls
(402). Coolant fluid flows into the microchannel cooling device
(400) from inlet ducts (405) and the coolant fluid is diverted to
the channels (403) by diverters (406). The coolant is then heated
by absorbing heat from the channel walls (402) and then flows out
of the microchannel cooler device (400) and exits through outlet
ducts (407). The arrows denote the coolant flow direction. There
are periodic widening portions along the channel walls (402) where
the through vias (404) are located. Advantageously, the through
vias (404) not only provide short communication paths for signal
transmissions between the carrier substrates, but enable enhanced
cooling of the module (200) due to the close proximity of the
conductive through vias with the cooling fluid that flows through
the microchannels (403).
[0039] FIG. 5 is a schematic cross-sectional view of an electronic
module according to another exemplary embodiment of the invention.
More specifically, FIG. 5 schematically illustrates an electronic
module (500) for integrating a microchannel cooler with IC chips
mounted face down on a high-density wiring carrier such as a
silicon carrier. In particular, the exemplary package comprises a
first level package carrier (501) (e.g., ceramic substrate) with an
array of large (.about.1 mm pitch) solder balls (B.sub.1) (e.g.,
BGA, ball grid array) that are used for bonding the substrate (501)
to a card or printed circuit board (not shown). The module (500)
further comprises an intermediate (or 2.sup.nd level) carrier
substrate (502) (e.g., silicon substrate) having a plurality of IC
chips (503) and (504) that are flip-chip bonded thereto. The
intermediate carrier substrate (502) is bonded to the first level
carrier substrate (501) via an array of fine pitch (.about.0.2 mm
pitch) solder balls (B.sub.2), such as C4's.
[0040] The carrier substrate (502) is constructed to comprise high
density wiring on the top surface thereof for providing electrical
interconnections to the IC chips (503) and (504) via high-density
solder bump arrays (B.sub.3) and (B.sub.4) (.about.0.05 mm pitch),
respectively. Moreover, the intermediate carrier substrate (502)
comprises a plurality of conductive vias that are formed through
the carrier substrate (502) to enable electrical connections with
the first level package substrate (501) via the solder bump array
(B.sub.2). The intermediate carrier substrate (502) and ceramic
substrate (501) are designed to provide a space transformation
between electrical connections between the fine pitch solder ball
arrays (B.sub.3 and B.sub.4) and the printed circuit board bond
ball array (B.sub.1) and to interconnect multiple chips on the
intermediate carrier substrate (502).
[0041] The electronic module (500) further comprises an integrated
microchannel cooling device (505) that is thermally bonded to the
non-active surfaces of the IC chips (503) and (504) via respective
rigid thermal bonds (B.sub.5) and (B.sub.6). The bonding material
used for the rigid thermal bonds (B.sub.5) and (B.sub.6) may
comprise any suitable material with low thermal resistivity, such
as a solder, metal layer, Ag epoxy, or a filled polymer, to thereby
allow sufficient heat conduction from the chips to the microchannel
plate (506). A low thermal resistance bond such as a metal joint,
solder joint, or a filled thermal adhesive such as a Ag epoxy, or
other joining means could be used, as long as the bonding thickness
is sufficiently thin and compatible with the cooling requirements.
Further, it is desirable that the bonds (B.sub.5) and (B.sub.6) are
reworkable, so that the microchannel cooler (505) can be removed
from the chips, when necessary, to either replace the microchannel
cooler device (505) or replace one or more of the chips (503) and
(504).
[0042] In one exemplary embodiment, the microchannel cooler module
(505) comprises a microchannel plate (506) connected to a manifold
plate (507) via bond (B.sub.7). The microchannel cooling device
(505) extends over the IC chips and is approximately the same size,
or slightly larger than, the intermediate carrier substrate (502).
The microchannel and manifold plates (506) and (507) may be formed
from silicon substrates, or other materials having TCE that matches
the TCE of the material forming the IC chips (503) and (504). The
microchannel plate (506) comprises a plurality of microfins (506a)
that define channels (506b), which are formed in surface regions of
the microchannel plate (506) that are aligned with the IC chips
(503) and (504). Further, the manifold plate (507) (or manifold
cover), which is bonded to the microchannel plate (506), comprises
a plurality of fluid manifolds formed therein, wherein each fluid
manifold comprises a corresponding manifold channel (507b) formed
in one surface the manifold plate (507) and a corresponding
pattern/series of fluid vias (507a) that form openings which extend
from the opposing surface of the manifold plate (507) to various
points along the corresponding manifold channel (507b).
[0043] The microchannel and manifold plates (506) and (507) may be
formed using the methods described in U.S. patent application Ser.
No. 10/883,392, filed Jul. 1, 2004, entitled "Apparatus and Methods
for Microchannel Cooling of Semiconductor Integrated Circuit
Packages", which is commonly assigned and fully incorporated herein
by reference. In general, this application describes methods for
constructing integrated microchannel cooler devices that include
supply/return manifolds and microchannels/microfins which are
structured, patterned, dimensioned and/or arranged in a manner that
minimizes pressure drop and increases uniformity of fluid flow and
distribution along coolant flow paths, as well as maintain the
structural integrity of the manifold plate to prevent breakage
during manufacturing. For instance, as explained in detail in U.S.
Ser. No. 10/883,392, the manifold plate (507) is designed such that
the inlets/outlets (507a) for a given manifold channel (507b) are
formed as a series of circular openings, or openings with rounded
corners, arranged in a zig-zag pattern, to reduce wafer cracking
during manufacturing. The manifold channel (507b) comprises tapered
channel segments formed between the circular openings on the plate
surface that faces the microchannels. The manifold is designed to
reduce the potential of wafer breakage by using circular openings
to minimize stress concentrations which can serve as crack
nucleation sites, minimizing the total cavity area of the channel
manifolds by using recessed regions of the microchannel pattern to
act as a manifold in conjunction with the manifold channels, and
avoid aligning the cavities along the (100) Si cleavage planes. In
another exemplary embodiment of the invention, an integrated
microchannel cooler device (505) may be formed from a single plate
that is constructed with both microchannels and supply/return
manifolds structures using the methods described in the above
incorporated application.
[0044] The microchannel plate (506) and manifold plate (507) are
bonded using bonding material (B.sub.7) that is sufficient to
provide a watertight seal, but the bond (B.sub.7) does not have to
provide a low thermal resistance. Accordingly, bonding methods such
as direct wafer bonding, fusion bonding, anodic bonding, glass frit
bonding, solder bonding, polymer adhesive bonding, or any other
suitable bonding method may be used to join the microchannel and
manifold plates (506) and (507).
[0045] The electronic module (500) further comprises a gasket (508)
and package cap (509). The package cap (509) comprises fluid
inlet/outlet manifolds (509a) that are aligned to corresponding
inlets/outlets (507a) of the microchannel cooler device (505). The
package cap (509) is connected to the back surface of the
microchannel cooler (505) via the gasket (508). In one exemplary
embodiment, the gasket (508) is adhered to both the microchannel
cooler (505) and the package cap (509) using a high temperature
epoxy or other suitable adhesive. In the exemplary embodiment of
FIG. 5, the package cap (509) is designed as a fluid distribution
manifold for delivering coolant fluid to/from integrated
microchannel cooler device (505). The manifold structure of the
package cap (509) can be designed using methods described in the
above incorporated patent application U.S. Ser. No. 10/883,392.
[0046] For instance, the fluid distribution manifolds (509a) can be
designed in a manner to minimize overall system pressure drop by
using variable cross-sectional fluid supply/return channels for
delivering coolant fluid to/from integrated microchannel cooler
devices. Moreover, with the exemplary microchannel cooling device
(505) depicted in FIG. 5, the fluid vias (507a) are formed on the
back surface of the manifold plate (507) chip to input/output
coolant fluid to/from the integrated microchannel cooler device,
which enables the microchannel cooler device (505) to be
dimensioned such that is does not extend significantly beyond the
area of the array of chips to be cooled.
[0047] FIG. 6 is a schematic cross-sectional view of an electronic
module (600) according to another exemplary embodiment of the
invention. In particular, the electronic module (600) is an
alternate embodiment similar to the electronic module (500) of FIG.
5, but wherein a high-performance processor chip (601) and memory
chips (602) and (603), which have different thicknesses, are
flip-chip mounted on an intermediate carrier substrate (604). In
the exemplary embodiment of FIG. 6, the processor chip (601), which
has a higher power density than the memory chips (602) and (603),
is mounted in a center region of the intermediate carrier substrate
(604), and the lower power density memory chips (or other chips),
are mounted along the peripheral regions of the carrier (604). The
chips (601), (602) and (603) are rigidly bonded a microchannel
cooler device (605) via rigid thermal bonds B1, B2 and B3,
respectively.
[0048] With the higher power-density chip (601), it is desirable to
have a lower total thermal resistance in the thermal bond (b1)
between the chip (601) and the microchannel cooler device (605) to
maintain the same maximum junction temperature as compared to the
lower power density chips (602) and (603). In particular, when
assembling a microchannel cooler (605) over multiple chips
(601.about.603) on a carrier (604) as depicted in the exemplary
embodiment of FIG. 6, it is desirable to insure that the high power
chip (601) have the thinnest bond layer of thermally conductive
material to attach the chip (601) to the microchannel cooler (605).
For example, in FIG. 6, if both memory chips (602) and (603) were
thicker than the processor chip (601), the thickness of the bond
line of the thermally conductive material (B.sub.1) used to attach
the processor chip (601) to the microchannel cooler (605) would be
greater than that of the bonds B.sub.2 and B.sub.3. Thus, in the
exemplary embodiment of FIG. 6, the lower power-density memory
chips (602) and (603) are thinned slightly as compared to the high
power processor chip (601) to insure that the thickness of the bond
line is determined by the back surface of the processor chip (601).
Methods for thinning of a lower power chip to accommodate different
power densities while maintaining a simple hat or lid structure are
described in U.S. patent application Ser. No. 10/711,023, filed on
Aug. 18, 2004, entitled "Multiple Power Density Chip Structure",
which is commonly assigned and fully incorporated herein by
reference. The power density of the chips and also the desired
junction temperature or power distribution of power on the chip are
factors that are considered when determining the thermal resistance
required to adequately cool the chips. Various methods for
assembling an electronic module having structures similar to those
depicted in the exemplary embodiment of FIGS. 5 and 6 will now be
described. An exemplary assembly process begins with mounting an
array of chips to an intermediate silicon carrier using any
suitable flip-chip bonding method known to those of ordinary skill
in the art. Optionally, the mounted chips may be under filled
and/or the back surface of the chips may be planarized by
polishing, lapping, or grinding. Then, a previously assembled and
pressure tested silicon microchannel cooler device can be attached
to the back surface of the chips mounted on the carrier using a
solder, metal layer, Ag epoxy, filled polymer, or other rigid
thermally conductive bonding method. The silicon carrier, chips,
and microchannel cooler package can then be assembled to a first
level package using C4's. In a final step, a package cap with
corresponding designed fluid inlet/outlet manifolds, is connected
to the back surface of the microchannel cooler using a gasket. The
gasket maybe adhered to both the microchannel cooler and the cap
using a high temperature epoxy or other suitable adhesive. In an
alternate embodiment, the microchannel cooler can be attached to
the chips and silicon carrier after they are assembled to the first
level package using C4's.
[0049] As discussed above, the use of a silicon carrier has a
number of significant advantages such as using finer pitch
electrical connections to the chips to provide greater electrical
signaling capacity and greater wiring capacity. However, silicon
carriers are difficult to cool using conventional methods because
of their limited thickness and large area. A typical silicon
carrier is between about 50 microns and about 200 microns thick
(and could be as thick as 500 microns), but the lateral size could
be 4 or 5 cm along each edge.
[0050] The exemplary package structures of FIGS. 5 and 6 according
to the invention, which integrate silicon carriers and microchannel
coolers, afford a number of significant advantages including, for
example, providing a low thermal resistance path to the integrated
microchannel cooler and using the microchannel cooler as a means of
providing additional mechanical strength to thin silicon carriers
to prevent fracture during subsequent processing and operation.
[0051] Although exemplary embodiments have been described herein
with reference to the accompanying drawings, it is to be understood
that the present system and method is not limited to those precise
embodiments, and that various other changes and modifications may
be affected therein by one skilled in the art without departing
from the scope or spirit of the invention. All such changes and
modifications are intended to be included within the scope of the
invention as defined by the appended claims.
* * * * *