U.S. patent application number 11/403015 was filed with the patent office on 2006-08-17 for etching metal silicides and germanides.
Invention is credited to Justin K. Brask, Robert B. JR. Turkot.
Application Number | 20060180874 11/403015 |
Document ID | / |
Family ID | 34063276 |
Filed Date | 2006-08-17 |
United States Patent
Application |
20060180874 |
Kind Code |
A1 |
Brask; Justin K. ; et
al. |
August 17, 2006 |
Etching metal silicides and germanides
Abstract
A metal silicide may be selectively etched by converting the
metal silicide to a metal silicate. This may be done using
oxidation. The metal silicate may then be removed, for example, by
wet etching. A non-destructive low pH wet etchant may be utilized,
in some embodiments, with high selectivity by dissolution.
Inventors: |
Brask; Justin K.; (Portland,
OR) ; Turkot; Robert B. JR.; (Hillsboro, OR) |
Correspondence
Address: |
TROP PRUNER & HU, PC
1616 S. VOSS ROAD, SUITE 750
HOUSTON
TX
77057-2631
US
|
Family ID: |
34063276 |
Appl. No.: |
11/403015 |
Filed: |
April 12, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10622955 |
Jul 18, 2003 |
7056780 |
|
|
11403015 |
Apr 12, 2006 |
|
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Current U.S.
Class: |
257/382 ;
257/E21.309; 257/E21.444; 257/E29.255 |
Current CPC
Class: |
H01L 29/78 20130101;
H01L 21/32134 20130101; H01L 29/66545 20130101 |
Class at
Publication: |
257/382 |
International
Class: |
H01L 29/76 20060101
H01L029/76 |
Claims
1. a semiconductor structure comprising: a substrate; a polysilicon
layer over said substrate; and a metal silicate formed on said
polysilicon layer.
2. The structure of claim 1 wherein said polysilicon is a
polysilicon gate electrode.
3. The structure of claim 2 including a sidewall spacer on said
polysilicon gate electrode.
4. The structure of claim 3 including a source and drain formed
adjacent said gate electrode.
5. The structure of claim 4 including a gate oxide under said gate
electrode.
6. A semiconductor structure comprising: a substrate; a layer over
said substrate; and a metal germinate formed on said layer.
7. The structure of claim 6 wherein said layer is a gate
electrode.
8. The structure of claim 7 including a sidewall spacer on said
gate electrode.
9. The structure of claim 8 including a source and drain formed
adjacent said gate electrode.
10. The structure of claim 9 including a gate oxide under said gate
electrode.
Description
[0001] This application is a divisional of U.S. patent application
Ser. No. 10/622,955, filed on Jul. 18, 2003.
BACKGROUND
[0002] This invention relates generally to etching metal silicides
and germanides in connection with semiconductor processing.
[0003] Metal silicides and germanides are conventionally somewhat
difficult to etch. A robust chemistry is needed to remove the
silicides or germanides. Selectively etching the silicide, while
not adversely affecting surrounding components, is a problem.
[0004] One example of a situation where it is desired to etch
silicide is in connection with metal gate replacement processes. In
such processes, a silicon gate or, more particularly, a polysilicon
gate may be removed in a selected number of instances and replaced
with a metal gate.
[0005] Commonly, the polysilicon material is in contact with a
metal and forms a silicide. Conventional etching may not
selectively remove the silicide from the polysilicon without
adversely affecting other components.
[0006] One approach to the problem is to form the metal layer over
both the locations where the gate is to be removed and the
locations where the gate is to remain. A hard mask may be retained
over the gates that will ultimately be removed in order to prevent
the formation of a silicide. However, patterning of the high
dielectric constant gate oxide may be difficult without removing
the hard mask. Thus, the use of a hard mask to protect the
polysilicon from the silicide formation is an incomplete solution
to the problem.
[0007] Thus, there is a need for better ways to facilitate the
selective etching of silicides and germanides.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is an enlarged, cross-sectional view of one
embodiment of the present invention at an early stage of
manufacture;
[0009] FIG. 2 is an enlarged, cross-sectional view corresponding to
FIG. 1 after further processing; and
[0010] FIG. 3 is an enlarged, cross-sectional view of the
embodiment in FIG. 2 after further processing.
DETAILED DESCRIPTION
[0011] In general, a metal silicide or germanide may be selectively
etched by converting the metal silicide or germanide into a metal
silicate or germinate. This may be done by oxidizing the
metal-silicon/germanium bond to form the silicate or germinate. The
metal-to-silicide bond is relatively weak compared to
silicon-to-oxygen or metal-to-oxygen bonds. Hence, oxidation of the
metal-to-silicon bond is energetically favored, given the correct
oxidation conditions. The correct oxidation conditions may include,
in some embodiments, the use of an aqueous solution of hydrogen
peroxide, organic peroxides, gaseous oxygen, or ozone, to mention a
few examples. Such treatments oxidize neutral metals and bare
silicon to their respective oxides. Also, in some embodiments,
extreme oxidation conditions may yield products including silicon
dioxide and non-discernable metal species. The intermediate silicon
species can be isolated and exploited.
[0012] Thus, in some embodiments of the present invention, the
silicide or germanide is first converted to a silicate or germinate
and then the silicate or germinate is selectively etched away. In
other embodiments, the removal and the conversion to silicate or
germinate may occur simultaneously in a one-step process.
[0013] Referring to FIG. 1, in an embodiment involving a metal gate
replacement process, a semiconductor wafer 10 may include a
substrate 12 having a source/drain region 24 formed on either side
of the polysilicon gate electrode 20. The substrate 12 may include
silicon or germanium. A dielectric 22 may separate the electrode 20
from the substrate 12. Sidewall spacers 18 may coat the side of the
gate electrode 20. A germanide or silicide 16 may be formed over
the gate electrode 20. For example, cobalt or nickel silicides may
be formed. An interlayer dielectric 14 may be positioned over the
substrate 12, around the gate electrode 20 and the silicide 16.
[0014] The structure shown in FIG. 1 may be exposed to a mild
oxidant, such as hydrogen peroxide or R.sub.2O.sub.2 (where R is an
organic material), O.sub.3 in vapor or gas form, or O.sub.2 in
gaseous form. The oxidation converts the germanide or silicide 16
into the germinate or silicate 16a as indicated in FIG. 2. Next,
the germinate or silicate 16a may be selectively etched using a
non-destructive, low pH wet etchant, such as H.sub.3PO.sub.4,
sulfuric acid, chelating species, or supercritical carbon dioxide
at lower temperatures such as 25 to 120.degree. C. In one
embodiment, the wafers may be immersed in a bath of liquid etchant.
These etchants have high selectivity and work by dissolution. This
results in the selective removal of the silicide 16a.
[0015] In some embodiments, the oxidation and the wet etching
processes may be combined, enabling the silicide to be removed in
essentially one step with two parallel processes occurring at the
same time.
[0016] It is desirable, in some embodiments, to use mild oxidation
to reduce the formation of silicon dioxide. Selectively removing
silicon dioxide is more difficult because of the likelihood that
other occurrences of silicon dioxide on the wafer will be
unintentionally removed.
[0017] In some embodiments, after exposing the gate electrode 20,
the gate electrode 20 may be removed using conventional technology
and the gate electrode may be replaced with a metal gate electrode.
However, the present invention is not necessarily limited to
silicide removal in connection with metal gate replacement
processes.
[0018] In some embodiments, vaporous or gaseous oxidizers may be
used. But given the cage-like structure of silicate oligomers, the
use of liquid oxidants may be advantageous.
[0019] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
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