U.S. patent application number 11/394233 was filed with the patent office on 2006-08-03 for 1t-nmemory cell structure and its method of formation and operation.
Invention is credited to Hasan Nejad, Mirmajid Seyyedy.
Application Number | 20060171224 11/394233 |
Document ID | / |
Family ID | 36756375 |
Filed Date | 2006-08-03 |
United States Patent
Application |
20060171224 |
Kind Code |
A1 |
Nejad; Hasan ; et
al. |
August 3, 2006 |
1T-nmemory cell structure and its method of formation and
operation
Abstract
A memory array architecture incorporates certain advantages from
both cross-point and 1T-1Cell architectures during reading
operations. The fast read-time and higher signal to noise ratio of
the 1T-1Cell architecture and the higher packing density of the
cross-point architecture are both exploited by using a single
access transistor to control the reading of multiple stacked
columns of memory cells, each column being provided in a respective
stacked memory layer.
Inventors: |
Nejad; Hasan; (Boise,
ID) ; Seyyedy; Mirmajid; (Boise, ID) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
2101 L STREET, NW
WASHINGTON
DC
20037
US
|
Family ID: |
36756375 |
Appl. No.: |
11/394233 |
Filed: |
March 31, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10925243 |
Aug 25, 2004 |
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11394233 |
Mar 31, 2006 |
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10214167 |
Aug 8, 2002 |
6882553 |
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10925243 |
Aug 25, 2004 |
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Current U.S.
Class: |
365/205 ;
257/E27.004 |
Current CPC
Class: |
G11C 11/22 20130101;
G11C 5/02 20130101; G11C 13/004 20130101; H01L 27/228 20130101;
G11C 2013/0054 20130101; H01L 27/24 20130101; G11C 11/16 20130101;
G11C 13/0011 20130101; G11C 2213/71 20130101 |
Class at
Publication: |
365/205 |
International
Class: |
G11C 7/00 20060101
G11C007/00 |
Claims
1-25. (canceled)
26. A memory device comprising: a plurality of memory slices, each
memory slice comprising a plurality of memory cells arranged
vertically and horizontally in a plane and which are commonly
electrically coupled to a respective sense line interconnect; and a
plurality of access transistors, each electrically coupled to a
respective sense line interconnect of a memory slice, each access
transistor operating during a read operation to couple a selected
memory cell in a slice to a sense amplifier.
27. The memory device of claim 26, wherein each of said memory
cells is a programmable conductor random access memory cell.
28. The memory device of claim 26, wherein each of said memory
cells is a ferroelectric random access memory cell.
29. The memory device of claim 26, wherein each of said memory
cells is a polymer memory cell.
30. The memory device of claim 26, wherein each of said memory
cells is a phase-changing chalcogenide memory cell.
31. The memory device of claim 26, wherein each memory cell has an
associated read line.
32. The memory device of claim 31, wherein during a read operation
said read line is selected by a row decoder, said access transistor
is selected by a column decoder.
33. A memory device comprising: a plurality of access transistors
each adapted to be electrically coupled with a sense amplifier; a
plurality of memory slices, each memory slice comprising a stacked
plurality of columns of commonly electrically coupled memory cells,
each column of commonly electrically coupled memory cells being
electrically coupled to a respective sense line wherein each of
said memory cells is a programmable conductor random access memory
cell; and a plurality of sense line interconnects, each said sense
line interconnect being electrically coupled between a respective
access transistor and the sense lines of a respective memory
slice.
34. The memory device of claim 33, further comprising: a plurality
of sensing circuits, each said sensing circuit coupling to said
respective access transistor.
35. The memory device of claim 33, further comprising a plurality
of read lines respectfully associated with said memory cells for
selecting an associated memory cell for a read operation.
36-76. (canceled)
77. A computer system comprising: a central processing unit; and a
memory device electrically coupled to said central processing unit,
said memory device comprising: a plurality of memory slices, each
memory slice comprising a plurality of memory cells arranged
vertically and horizontally in a plane and which are commonly
electrically coupled to a respective sense line interconnect,
wherein each of said memory cells is a programmable conductor
random access memory cell; and a plurality of access transistors,
each electrically coupled to a respective sense line interconnect
of a memory slice, each access transistor operating during a read
operation to couple a selected memory cell in a slice to a sense
amplifier.
78. The computer system of claim 77, wherein each memory cell has
an associated read line.
79. The computer system of claim 78, wherein during a read
operation said read line is selected by a row decoder, said access
transistor is selected by a column decoder.
80. A computer system comprising: a central processing unit; and a
memory device electrically coupled to said central processing unit,
said computer system comprising: a plurality of access transistors
each adapted to be electrically coupled with a sense amplifier; a
plurality of memory slices, each memory slice comprising a stacked
plurality of columns of commonly electrically coupled memory cells,
each column of commonly electrically coupled memory cells being
electrically coupled to a respective sense line; and a plurality of
sense line interconnects, each said sense line interconnect being
electrically coupled between a respective access transistor and the
sense lines of a respective memory slice.
81. The computer system of claim 80, further comprising: a
plurality of sensing circuits, each said sensing circuit coupling
to said respective access transistor.
82. The computer system of claim 81, further comprising a plurality
of read lines respectfully associated with said memory cells for
selecting an associated memory cell for a read operation.
83. The computer system of claim 80, wherein each of said memory
cells is a phase changing chalcogenide memory cell.
84. The computer system of claim 80, wherein each of said memory
cells is a polymer memory cell.
85. The computer system of claim 80, wherein each of said memory
cells is a programmable conductor random access memory cell.
86. The computer system of claim 80, wherein each of said memory
cells is a ferroelectric random access memory cell.
Description
[0001] This application is a continuation-in-part of U.S. patent
application Ser. No. 10/214,167, entitled STACKED COLUMNAR 1T-nMJT
MRAM STRUCTURE AND ITS METHOD OF FORMATION AND OPERATION, filed
Aug. 8, 2002, the entirety of which is hereby incorporated by
reference.
FIELD OF THE INVENTION
[0002] The present invention relates to memory devices employing
memory cell arrays including but not limited to nonvolatile and
semi-volatile programmable resistance memory cells such as MRAM and
PCRAM, and, more particularly, to read circuitry for memory
cells.
BACKGROUND OF THE INVENTION
[0003] Integrated circuit designers have always sought the ideal
semiconductor memory: a device that is randomly accessible, can be
written or read very quickly, is non-volatile, but indefinitely
alterable, and consumes little power. Emerging technologies are
increasingly viewed as offering these advantages. Some nonvolatile
or semi-volatile memory technologies include Magnetoresistive
Random Access Memory (MRAM), Programmable Conductor Random Access
Memory (PCRAM), Ferroelectric Random Access Memory (FERAM), polymer
memory, and chalcogenide memory. Each of these memory types can be
employed in stacked arrays of memory cells for increased
density.
[0004] One type of memory element has a structure which includes
ferromagnetic layers separated by a non-magnetic barrier layer that
forms a tunnel junction. A typical memory device is described in
U.S. Pat. No. 6,359,756 to Sandhu et al., entitled Self-Aligned
Magnetoresistive Random Access Memory (MRAM) Structure. Information
can be stored as a digital "1" or a "0" as directions of
magnetization vectors in these ferromagnetic layers. Magnetic
vectors in one ferromagnetic layer are magnetically fixed or
pinned, while the magnetic vectors of the other ferromagnetic layer
are not fixed so that the magnetization direction is free to switch
between "parallel" and "anti-parallel" states relative to the
pinned layer. In response to parallel and anti-parallel states, the
magnetic memory element represents two different resistance states,
which are read by the memory circuit as either a "1" or a "0." It
is the detection of these resistance states for the different
magnetic orientations that allows the memory to read binary
information.
[0005] Recently resistance variable memory elements, which include
PCRAM elements, have been investigated for suitability as
semi-volatile and non-volatile random access memory devices. A
typical PCRAM device is disclosed in U.S. Pat. No. 6,348,365 to
Moore et al. In typical PCRAM devices, conductive material, such as
silver, is incorporated into a chalcogenide material. The
resistance of the chalcogenide material can be programmed to stable
higher resistance and lower resistance states. The unprogrammed
PCRAM device is normally in a high resistance state. A write
operation programs the PCRAM device to a lower resistance state by
applying a voltage potential across the chalcogenide material.
[0006] The programmed lower resistance state can remain intact for
an indefinite period, typically ranging from hours to weeks, after
the voltage potentials are removed. The PCRAM device can be
returned to its higher resistance state by applying a reverse
voltage potential of about the same order of magnitude as used to
write the element to the lower resistance state. Again, the higher
resistance state is maintained in a semi-volatile manner once the
voltage potential is removed. In this way, such a device can
function as a resistance variable memory element having two
resistance states, which can define two logic states.
[0007] A PCRAM device can incorporate a chalcogenide glass
comprising germanium selenide (GexSe100-x). The germanium selenide
glass may also incorporate silver (Ag) or silver selenide
(Ag.sub.2Se). A PCRAM memory element utilizes at least one
chalcogenide-based glass layer between two electrodes. For an
example of a typical PCRAM cell, refer to U.S. Pat. No. 6,348,365
to Moore et al. A PCRAM cell operates by exhibiting a reduced
resistance in response to an applied write voltage. This state can
be reversed by reversing the polarity of the write voltage. Like
the MRAM, the resistance states of a PCRAM cell can be sensed and
read as data. Analog programming states are also possible with
PCRAM. MRAM and PCRAM cells can be considered nonvolatile or
semi-volatile memory cells since their programmed resistance state
can be retained for a considerable period of time without requiring
a refresh operation. They have much lower volatility than a
conventional Dynamic Random Access Memory (DRAM) cell, which
requires frequent refresh operations to maintain a stored logic
state.
[0008] FERAM, another nonvolatile memory type, utilizes
ferroelectric crystals integrated into the memory cells. These
crystals react in response to an applied electric field by shifting
the central atom in the direction of the field. The voltage
required to shift the central atoms of the crystals of the cells
can be sensed as programmed data.
[0009] Polymer memory utilizes a polymer-based layer having ions
dispersed therein or, alternatively, the ions may be in an adjacent
layer. The polymer memory element is based on polar conductive
polymer molecules. The polymer layer and ions are between two
electrodes such that upon application of a voltage or electric
field the ions migrate toward the negative electrode, thereby
changing the resistivity of the memory cell. This altered
resistivity can be sensed as a memory state.
[0010] There are different array architectures that are used within
memory technology to read memory cells. One architecture which is
used is the so-called one transistor--one cell ("1T-1Cell")
architecture. This structure is based on a single access transistor
for selecting a memory element for a read operation. Another
architecture is the cross-point architecture, where a cell is
selected and a read operation performed without using an access
transistor. This type of system uses row and column lines set to a
predetermined voltage levels to read a selected cell. Each system
has its advantages and disadvantages. The cross-point system is
somewhat slower in reading than the 1T-1Cell system, as well as
having a lower signal to noise ratio during a read operation;
however, the cross-point array has the advantage that such arrays
can be easily stacked within an integrated circuit for higher
density. The 1T-1Cell array is faster, has a better signal to noise
ratio, but is less densely integrated than a cross-point array.
[0011] It is desirable to have a memory read architecture that
could utilize advantages from both the 1T-1Cell and cross-point
architectures, while minimizing the disadvantages of each.
SUMMARY
[0012] This invention provides a memory array read architecture
which incorporates certain advantages from both cross-point and
1T-1Cell architectures. The fast read-time and high signal to noise
ratio of the 1T-1Cell architecture and the higher packing density
of the cross-point architecture are both exploited in the invention
by uniquely combining certain characteristics of each. In an
exemplary embodiment, an access transistor is used to select for
reading multiple columns of memory cells, which are stacked
vertically above one another in a memory slice of a memory array.
In this architecture, the plurality of columns of memory cells
share a common sense line. A specific memory cell within the
multiple columns is accessed by a row and plane address during a
read operation.
[0013] The invention also provides methods of fabricating memory
devices having characteristics noted in the preceding paragraph and
methods of operating memory devices to read a selected memory
cell.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] These and other features and advantages will become more
apparent from the following detailed description of the invention
which is provided in conjunction with the accompanying drawings, in
which:
[0015] FIG. 1 is a two-dimensional cross-sectional view of a
portion of a memory array constructed in accordance with an
exemplary embodiment of the invention;
[0016] FIG. 2a is a perspective cross-sectional illustration of a
portion of a memory array constructed in accordance with the
embodiment shown in FIG. 1;
[0017] FIG. 2b is a perspective cross-sectional illustration of a
memory slice of a memory array, constructed in accordance with FIG.
2a;
[0018] FIG. 2c is a perspective cross-sectional illustration of a
memory array layer of a memory array, constructed in accordance
with FIG. 2a;
[0019] FIG. 2d is an illustration of a memory column of a memory
array, constructed in accordance with FIG. 2a;
[0020] FIG. 3 is a three dimensional block diagram and
representational illustration of the FIGS. 1 and 2a-d memory
array;
[0021] FIG. 4 is a block diagram and representational illustration
of a memory cell showing the interaction between the layers of the
cell and other circuitry;
[0022] FIG. 5 is a block diagram representation of a
processor-based system incorporating a memory device in accordance
with the invention;
[0023] FIG. 6 is a cross-sectional view of a PCRAM memory cell used
in an embodiment of the invention; and
[0024] FIG. 7 is a cross-sectional view of a PCRAM memory cell used
in another embodiment of the invention.
DETAILED DESCRIPTION
[0025] In the following detailed description, reference is made to
various specific embodiments in which the invention may be
practiced. These embodiments are described with sufficient detail
to enable those skilled in the art to practice the invention, and
it is to be understood that other embodiments may be employed, and
that structural and electrical changes may be made without
departing from the spirit or scope of the present invention.
[0026] The terms "substrate" and "wafer" can be used
interchangeably in the following description and may include any
semiconductor-based structure. The structure should be understood
to include silicon, silicon-on insulator (SOI), silicon-on-sapphire
(SOS), doped and undoped semiconductors, epitaxial layers of
silicon supported by a base semiconductor foundation, and other
semiconductor structures. The semiconductor need not be
silicon-based. The semiconductor could be silicon-germanium,
germanium, or gallium arsenide. When reference is made to the
substrate in the following description, previous process steps may
have been utilized to form regions or junctions in or over the base
semiconductor or foundation. Additionally, the substrate need not
be semiconductor-based, but may be any structure suitable for
supporting a memory array, such as polymer, ceramic, metal, glass,
and other materials.
[0027] The term "silver" is intended to include not only elemental
silver, but silver with other trace metals or in various alloyed
combinations with other metals as known in the semiconductor
industry, as long as such silver alloy is conductive, and as long
as the physical and electrical properties of the silver remain
unchanged.
[0028] The term "silver-selenide" is intended to include various
species of silver-selenide, including some species which have a
slight excess or deficit of silver. For example, silver-selenide
species may be represented by the general formula Ag.sub.2+/-xSe.
Though not being limited by a particular stoichiometric ratio
between Ag and Se, devices of the present invention typically
comprise an Ag.sub.2+/-xSe species, where x ranges from about 1 to
about 0.
[0029] The term "semi-volatile memory" is intended to include any
memory device or element which is capable of maintaining its memory
state after power is removed from the device for some period of
time. Thus, semi-volatile memory devices are capable of retaining
stored data after the power source is disconnected or removed.
Accordingly, the term "semi-volatile memory" is also intended to
include not only semi-volatile memory devices, but also
non-volatile memory devices and those of low volatility.
[0030] The term "resistance variable material" is intended to
include chalcogenide glasses, and chalcogenide glasses comprising a
metal, such as silver or metal ions. For instance, the term
"resistance variable material" may include silver doped
chalcogenide glasses, silver-germanium-selenide glasses,
chalcogenide glass comprising a silver selenide layer, and
non-doped chalcogenide glass.
[0031] The term "chalcogenide glass" is intended to include glasses
that comprise an element from group VIA (or group 16) of the
periodic table. Group VIA elements, also referred to as chalcogens,
include sulfur (S), selenium (Se), tellurium (Te), polonium (Po),
and oxygen (O).
[0032] This invention relates to low volatility memory technology
(e.g., MRAM, PCRAM, FERAM, polymer memory, and chalcogenide memory)
and new variations on memory array architecture to incorporate
certain advantages from both cross-point and 1T-1Cell
architectures. The fast read-time and high signal to noise ratio of
the 1T-1Cell architecture and the higher packing density of the
cross-point architecture are both exploited by combining certain
characteristics of each layout. FIGS. 1 and 2a-2d illustrate memory
device 100, an exemplary embodiment of the invention in which an
array architecture has a plurality of memory arrays 34 stacked one
over another. Each array 34 includes a plurality of rows and
columns of memory cells. All of the memory cells in the
corresponding column in each of the stacked arrays form a memory
slice 80 and are coupled to a single access transistor 16 as a
group. Although the novel architecture of FIGS. 1 and 2a-2d is
applicable to any memory device than can utilize either cross-point
or 1T-1Cell read architecture and is described generally in
relation to such devices (in particular those discussed in the
background), the invention is specifically described in relation to
MRAM devices for exemplary purposes. In an embodiment of the
invention, a PCRAM cell comprises a layer of Ge.sub.xSe.sub.100-x,
a layer of silver, and a layer of silver selenide where X is about
40. Although described in reference to Ge.sub.xSe.sub.100-x, the
invention is not meant to be so limited.
[0033] In FIGS. 1 and 2a-2b, an access transistor 16 is used to
control the reading of multiple memory cells 38, arranged in
columns 81, one from each array layer 34, which are stacked
substantially above one another in the "Z" axis direction. The
memory cells 38 can be low volatility cells of MRAM, PCRAM, FERAM,
polymer memory, chalcogenide memory, or other memory construction.
Thus, each access transistor 16 is connected to a substantially
vertical stack of columns 81 of memory cells 38 arranged
substantially above it. The plurality of columns 81 in this "Y-Z"
direction have respective sense lines 33 which are interconnected
by virtue of a sense line interconnect 32. This architecture is
represented in two-dimensions in FIG. 1 and in three-dimensions in
FIG. 2a, 2b, 2c, and 2d. The "X," "Y." and "Z" axes are shown in
FIG. 1.
[0034] Now referring more specifically to the figures, where like
reference numbers designate like elements, FIG. 1 shows a plurality
of stacked planar memory cell array layers 34. Each layer 34 has a
plurality of memory cells 38 arranged in rows, defined by
read/write row lines 44, and columns, defined by sense lines 33 and
write only column lines 40. An access transistor layer 12 is
fabricated on a semiconductor substrate 10 below the array layers
34. The access transistor layer 12 includes a plurality of access
transistors 16 arranged along the "X" axis direction corresponding
to the direction in which the row lines 44 extend in each memory
array layer 34.
[0035] As shown in FIG. 1, the access transistors 16 can be typical
N-channel MOSFET (metal oxide semiconductor field effect
transistor), though the specific structure of the access transistor
16 is not crucial to the invention. The transistor 16 includes
source/drain regions 14 in the substrate 10. Each transistor 16
further includes a gate oxide 18, and over this a polysilicon gate
layer 20 with an overlying silicide layer 22, all topped by a
nitride cap 24. The polysilicon layer 20 and silicide layer 22
together form a control line 23 which continues in the "X" axis
direction in the manner best shown in FIG. 3. The sides of the
access transistor 16 control line 23 are insulated and protected by
insulating sidewalls 26, made of an oxide or nitride material. In a
preferred embodiment, transistors 16 share the control line 23. The
control line 23 of the access transistor 16 can be connected to a
decoding circuit with peripheral circuitry 48 (depicted in FIG. 4).
Access transistor 16 can be fabricated by any techniques well known
to those skilled in the art.
[0036] Still referring to FIG. 1, an insulating dielectric layer 28
is formed over and around the access transistor 16. Through this
insulating dielectric layer 28 conductive plugs 30 are fabricated
which connect to the source/drain regions 14. The insulating
dielectric 28 can be any material known in the art, such as an
oxide or BPSG, and can be formed according to methods well known in
the art. The conductive plugs 30 similarly can be any conductive
material well known in the art, but preferably are polysilicon or
tungsten, and can be formed by known methods. One of the conductive
plugs 30 serves to connect one of the source and drain regions 14
to the column sense lines 33 of the stacked memory array layers 34,
while the other conductive plug connects the other of the source
and drain regions 14 to a sense amplifier 50 used during the
reading of memory cells 38. The connections between each access
transistor 16 and the memory array layers 34 and the bit lines 31
are typically formed as metal interconnects 36, provided within
insulating layer 41. The metal interconnects 36 and bit lines 31
can be copper, aluminum, or any other metal or other conductor
known as suitable in the art, and can be formed by known
methods.
[0037] As further shown in FIG. 2a, the memory cells 38 are
arranged in rows and columns in each array layer 34, and each array
layer 34 is arranged in a stacked fashion over substrate 10. Memory
cells 38 are arranged in two-dimensional arrays (in the "X, Y"
plane) in each array layer 34, where each cell 38 is defined at the
intersection of a row read/write line 44 and a column sense line
33, which are orthogonal to each other, as shown in FIGS. 2a, 2b,
and 2c. The stacked columns 81 of cells 38 from each array layer 34
form a memory slice 80, that is, a plane of cells in the Y-Z
direction, as shown in FIG. 2b. In the figures a, b, c, d are used
to reference structures laid out in the X axis (column) direction,
i, j, k, I are used to reference structures laid out in the Y axis
(row) direction, and p, q, r are used to reference structures laid
out in the Z axis (stacked array 34 direction) direction.
Accordingly, the ath memory slice (i.e., memory slice 80a) is
formed by the ath columns 81 of memory cells 38 of each array layer
34. Therefore, memory slices 80 taken in the Y-Z direction are
orthogonal to the memory array layers 34 which are formed in the
X-Y direction.
[0038] Each sense line 33 in a common memory slice 80 is coupled to
a plurality of memory cells 38 arranged in a respective column 81
of a layer 34 (FIG. 2d), in a Y axis direction. This can best be
seen in the three-dimensional perspective of FIG. 3. The sense
lines 33 for a memory slice 80 are also interconnected by a
vertical metal interconnect 32 (FIGS. 1-3). FIG. 1 also shows a
write only column line 40 for each column 81 of memory cells 38 in
each array 34, which may be provided to assist in writing memory
cells 38 when memory cells 38 are MRAM cells. The write only lines
40 are omitted in FIGS. 2a-d and 3 for clarity, although they are
shown in simplified format in FIG. 4. The write only lines 40 would
not be necessary in memory schemes other than MRAM, where they are
used to produce a crossing magnetic field.
[0039] FIG. 3 shows four memory slices 80 arranged in the X axis
direction, where each memory slice 80 contains four columns 81 of
memory cells 38 stacked in a vertical direction. Each memory slice
80 has an associated access transistor 16, bit line 31 and sense
amplifier 50.
[0040] Referring to FIG. 4, which shows the memory cell 38 as an
exemplary MRAM cell, each cell 38 can include, the common
read/write row line 44, used for both the reading and writing
functions, a memory region 42, a column sense line 33 used for the
reading function, and a column write-only line 40 used for the
writing function (again, only for MRAM), which is separated from
the sense line 33 by a dielectric layer 46. The memory region 42
includes a free ferromagnetic structure 43, a tunnel junction layer
45, and a pinned ferromagnetic structure 41. In the illustrated
embodiment, the free ferromagnetic structure 43 is above the pinned
ferromagnetic structure 41, which is adjacent to the sense line 33;
however, it is possible to invert the arrangement of the pinned and
free ferromagnetic structures as is known in the art.
[0041] The memory cells 38 which are coupled through sense lines 33
from respective array layers 34 and share a sense line interconnect
32 are in a memory slice 80 in the "Y-Z" direction, which is
vertical relative to the access transistor 16 as shown in FIG. 3.
However, other configurations are possible, so long as a plurality
of sense lines 33, corresponding to a column 81 of memory cells 38
in each array 34, is connected to the common vertically arranged
sense line interconnect 32.
[0042] The write-only column line 40 of the (MRAM) memory cell 38
can be composed of conductive materials as known in the art; the
particular combination of materials making up the write-only line
is not a critical element of the invention; however, as an example
this line 40 can be copper or aluminum, and is insulated from other
conductive structures by dielectric layer 46. Though shown in
segments in FIG. 1, the write-only column lines 40 actually are
continuous and travel around the sense line interconnects 32, as
shown by the dashed arrows in FIG. 1.
[0043] Shown more clearly in FIG. 4, above the write-only line 40
is the sense line 33, which will be further described below, and
the magnetic bit (memory region) 42, which is in contact with the
common read/write line 44. The pinned ferromagnetic structure 41
includes an associated anti-ferromagnetic layer (not shown), such
as iron manganese, which keeps the magnetic orientation of this
layer 41 fixed, i.e., "pinned." The pinned ferromagnetic structure
41 can be formed of layers of ferromagnetic material having good
magnetic properties, such as nickel iron cobalt or nickel iron, for
instance. The tunnel junction 45 is a non-magnetic region
separating the two ferromagnetic structures 41 and 43. The tunnel
junction 45 can be made of many materials, as is known in the art,
but the preferred material is aluminum oxide. The tunnel junction
45 layer should be thin, smooth and consistent throughout the
various memory (e.g., MRAM) cells 38, as is known in the art. Over
the tunnel junction 45 is the free ferromagnetic structure 43,
which also can be made of a plurality of ferromagnetic layers.
Unlike the pinned ferromagnetic structure 41, the free
ferromagnetic structure 43 is free to shift its magnetic
orientation during the writing of the memory (e.g., MRAM) cell 38
and has no associated anti-ferromagnetic layer. The free
ferromagnetic structure 43 is in electrical contact with a common
(read/write) row line 44.
[0044] Referring again to FIG. 1, a nitride passivation layer is
typically provided over the uppermost array layer 34 to protect the
memory device. There is no restrictive limit on the number of
memory array layers 34 which may be used, other than the
practicality of physical size of the ultimate device. In general,
ten or more layers 34 are feasible. Of course, a lesser number of
layers 34 can also be used. Likewise, the only limit on the number
of Y-Z axis memory slices 80 arranged in the X axis direction and
the number of memory cells 38 contained in each memory slice 80 is
the practicality of physical size of the ultimate device.
[0045] In the architecture of the invention, a single access
transistor 16 is shared by each of the memory cells 38 within a
memory slice 80 in the "Y-Z" planar direction of the stacked layers
34 substantially above the access transistor 16.
[0046] Each access transistor 16 can be connected to a
corresponding sense amplifier 50 in various ways. For instance,
each access transistor 16 can be electrically coupled with a single
respective bit line 31 and that bit line 31 can be electrically
coupled as one input to a single respective sense amplifier 50
which has another input receiving a reference voltage or,
alternatively, multiple bit lines 31 associated with respective
access transistors 16 can be electrically coupled through a switch
circuit and share a single sense amplifier 50.
[0047] During a write operation a memory (e.g., MRAM) cell 38 is
addressed by the coinciding activation of the common read/write row
line 44 and a write-only column line 40 in a selected array layer
34 associated with that cell 38 by peripheral logic circuitry.
Thus, the peripheral logic 48 performs a row, column and array
layer decode to select a cell 38 for a writing operation. The
actual writing of memory is performed, as is known in the art in
the exemplary MRAM, as a function of magnetic moments produced by
the electric currents of the common read/write row line 44 and
write only column line 40 causing the free ferromagnetic structure
43 to obtain a particular magnetic orientation depending on the
direction of current flow through the read/write row line 44 and
the write only column line 40.
[0048] To read stored information in a memory cell 38, a cell 38 in
the Y-Z plane of memory cells is accessed by applying an
appropriate voltage to a read/write row line 44 of a selected
planar array 34 relative to other read/write row lines 44 in the
selected planar array and by activating the access transistor 16
associated with the Y-Z plane (column) of cells containing the
selected cell. Thus, a cell 38 in the three-dimensional array (as
shown in FIG. 3) is addressed for reading in "X" axis direction by
column decode signal which turns on access transistor 16, and in
the "Y-Z" planar direction by a selected common read/write row line
44 activated by a row decode signal. A decoded plane address signal
selects one of the planar layers 34 to which the decoded row signal
is applied.
[0049] When turned on, the access transistor 16 connects a sense
amplifier 50 (connected to the source/drain 14 of the transistor 16
by the bit line 31) to a sense line interconnect 32 (connected to
the other source/drain 14 of the access transistor 16) associated
with the sense lines 33 of a memory cell 38 associated with a
plurality of columns in the associated memory slice 80 in the "Y-Z"
planar direction over that transistor 16. When a cell is read, the
sense amplifier 50 connected to the access transistor 16 senses the
logic state stored in the read cell as a resistance (or voltage or
current depending on the memory type) by any method well known in
the art.
[0050] Conventional row decoding techniques can be used to activate
a read/write line 44 to select a row of memory cells 38 in each
array layer 34. Additional address bits are decoded and used to
select one of the array layers 34. For the three array layers 34
shown in FIGS. 1, 2a-c and 3, this would require two additional
address bits which can be added to the row or column address bits.
During a read, the column addresses are used to select an access
transistor 16, corresponding to a memory slice 81. Once the row and
column addresses have been received in the memory device, they are
decoded to activate an addressed row, column, and array layer 34.
As one example, if the memory device is a 16 Mbit array organized
as 2048 rows by 2048 columns by 4 layers 34, the memory device
would utilize an 11-bit (2.sup.11=2048) row address and a 13-bit
column address, with 11 of the 13 bits used for a column selection
(2.sup.11=2048) and the two remaining column bits used for planar
array 34 selection (2.sup.2=4).
[0051] Once a memory cell 38 has been addressed for a read
operation, the addressed cell 38 is coupled to one of the inputs of
a sense amplifier 50 via a sense line 33, a sense line interconnect
32, an access transistor 16, and a bit line 31. The other input of
the sense amplifier 50 is coupled to another one of the
non-addressed lines 31 to use as a reference, or to a reference
voltage. The sense amplifier 50 senses the resistance of the
selected cell 38 connected to one input of the sense amplifier 50
using the other input of the sense amplifier 50 as a reference.
[0052] This architecture provides for a transistor driver (the
access transistor 16) for the reading function, which is close to
both the memory cells 38 and the sense amplifier 50 enabling a
faster read function. This arrangement also produces a higher
signal to noise ratio during the read function than is provided by
a conventional cross-point architecture. In this arrangement, the
memory three-dimensional array essentially consists of a 1T-nCell
architecture, where n is equal to the number of memory cells 38 in
the memory slice 80 in the "Y-Z" planar direction. Accordingly,
fewer access transistors 16 are required than is needed in the
1T-1Cell architecture known in the art.
[0053] FIG. 6 is a cross-sectional view of a PCRAM memory cell used
as the memory cells in the memory device 100 (FIG. 1) constructed
in accordance with another exemplary embodiment of the invention.
FIG. 6 depicts a conventional structure for a PCRAM memory cell as
seen, for example, in U.S. Pat. No. 6,348,365 and U.S. published
application No. 2003/0155589, which are incorporated herein by
reference in their entirety. As seen in FIG. 6, the PCRAM memory
cell includes a semiconductive substrate 610, an insulating
material 611, a conductive material 612, dielectric material 613,
metal ion-laced glass material 651, metal material 641, and
conductive material 661. The semiconductive substrate 610 may be a
silicon wafer. The insulating material 611 may be a material such
as silicon dioxide. The conductive material 612 may be a material
such as tungsten. The dielectric material 613 may be a material
such as silicon nitride. The metal ion-laced glass material 651
that serves as an ion conductor may be formed from a glass
material, such as Ge.sub.xSe.sub.y, that has been diffused with
metal material layer 641 which results in material layer 651 being
laced with metal ions.
[0054] The metal material 641 may be a material such as silver,
tellurium, or copper. Suitable conductive materials that can be
used to form electrode or conductive material 661 include those
conductive materials that will effectively alloy with the metal
material selected to form metal material 641, of which silver is
preferred. In the case where silver is used to form conductive
material 641, suitable conductive materials for conductive material
661 include tungsten, tantalum, titanium, tantalum nitride,
tungsten nitride and so forth. The PCRAM memory cell is formed in
accordance with fabrication steps used by those skilled in the art.
In an embodiment of the invention, the glass material 651 is formed
from Ge.sub.xSe.sub.100-x, where X is about 40. Although described
with specific architectures, layers, materials and stoichiometries,
the invention is not meant to be so limited.
[0055] FIG. 7 is a more detailed cross-sectional view of a PCRAM
memory cell 700 used as the memory cells in the memory device 100
(FIG. 1) constructed in accordance with another exemplary
embodiment of the invention. The memory cell 700 includes a
semiconductor substrate 710, which in the illustrated embodiment is
a silicon wafer. A bottom electrode 712 is over the substrate 710.
The electrode may be tungsten or nickel. A first glass layer 714 is
over the bottom electrode 712. The first glass layer 714 comprises
Ge.sub.xSe.sub.100-x, where X is about 40, and is approximately 150
.ANG. thick. A layer of silver (Ag) 716 is provided over the first
glass layer 714. The silver layer 716 is approximately 35 .ANG. to
approximately 50 .ANG. thick. A silver-selenide (Ag.sub.2+xSe)
layer 718 is provided over the silver layer 716 and is
approximately 470 .ANG. thick.
[0056] A second glass layer 720 is provided over the
silver-selenide layer 718. The second glass layer 720 comprises
Ge.sub.xSe.sub.100-x, where X is about 40, and is approximately 150
.ANG. thick. A second layer of silver (Ag) 722 is provided over the
second glass layer 720. The second silver layer 722 is
approximately 200 .ANG. thick. A third glass layer 724 is provided
over the second silver layer 722. The third glass layer 724
comprises Ge.sub.xSe.sub.100-x, where X is about 40, and is
approximately 100 .ANG. thick. A first top electrode 726 is
provided over the third glass layer 724. In the illustrated
embodiment, the first top electrode 726 does not contain silver and
comprises tungsten. A second top electrode 728 is provided over the
first top electrode 726. In the illustrated embodiment, the second
top electrode 728 does not contain silver and comprises nickel.
[0057] A memory array as described above can be formed using
conventional processing techniques commonly known in the art. A
layer 12 of access transistors, each having a gate and source drain
region is formed over a substrate. Sense amplifier circuitry is
also formed in the same layer along with other periphery circuitry
such as row, column, and plane decoders. The transistor layer is
covered by one or more insulating layers 28. Conductive paths are
formed through the insulating layer 28 and additional insulating
layer 41 is provided over the insulating layer 28. Planar memory
array layers 34 are sequentially formed one over another; each
layer 34 contains a plurality of rows and columns of memory cells.
A conductive path 36, including interconnect 32, is formed from one
of one source/drain regions of each transistor 16 to memory cells
of stacked columns of cells in a manner commonly known in the art.
The memory cells can be formed by different layers of materials as
commonly known and discussed above. The other of the source/drain
regions is coupled to a sense amplifier 50 by a conductive path 36
formed between the transistor and sense amplifier 50.
[0058] FIG. 5 illustrates an exemplary processing system 900, which
may utilize a memory device 100 as in FIGS. 1-3. The processing
system 900 includes one or more processors 901 coupled to a local
bus 904. A memory controller 902 and a primary bus bridge 903 are
also coupled the local bus 904. The processing system 900 may
include multiple memory controllers 902 and/or multiple primary bus
bridges 903. The memory controller 902 and the primary bus bridge
903 may be integrated as a single device 906.
[0059] The memory controller 902 is also coupled to one or more
memory buses 907. Each memory bus 907 accepts memory components
908, which include at least one memory device 100 constructed in
accordance with the present invention. The memory components 908
may be a memory card or a memory module. Examples of memory modules
include single inline memory modules (SIMMs) and dual inline memory
modules (DIMMs). The memory components 908 may include one or more
additional devices 909. For example, in a SIMM or DIMM, the
additional device 909 might be a configuration memory, such as a
serial presence detect (SPD) memory. The memory controller 902 may
also be coupled to a cache memory 905. The cache memory 905 may be
the only cache memory in the processing system. Alternatively,
other devices, for example, processors 901 may also include cache
memories, which may form a cache hierarchy with cache memory 905.
If the processing system 900 includes peripherals or controllers,
which are bus masters or which support direct memory access (DMA),
the memory controller 902 may implement a cache coherency protocol.
If the memory controller 902 is coupled to a plurality of memory
buses 907, each memory bus 907 may be operated in parallel, or
different address ranges may be mapped to different memory buses
907.
[0060] The primary bus bridge 903 is coupled to at least one
peripheral bus 910. Various devices, such as peripherals or
additional bus bridges may be coupled to the peripheral bus 910.
These devices may include a storage controller 911, a miscellaneous
I/O device 914, a secondary bus bridge 915, a multimedia processor
918, and a legacy device interface 920. The primary bus bridge 903
may also be coupled to one or more special purpose high speed ports
922. In a personal computer, for example, the special purpose port
might be the Accelerated Graphics Port (AGP), used to couple a high
performance video card to the processing system 900.
[0061] The storage controller 911 couples one or more storage
devices 913, via a storage bus 912, to the peripheral bus 910. For
example, the storage controller 911 may be a SCSI controller and
storage devices 913 may be SCSI discs. The I/O device 914 may be
any sort of peripheral. For example, the I/O device 914 may be a
local area network interface, such as an Ethernet card. The
secondary bus bridge may be used to interface additional devices
via another bus to the processing system. For example, the
secondary bus bridge may be an universal serial port (USB)
controller used to couple USB devices 917 via to the processing
system 900. The multimedia processor 918 may be a sound card, a
video capture card, or any other type of media interface, which may
also be coupled to one additional device such as speakers 919. The
legacy device interface 920 is used to couple legacy devices, for
example, older styled keyboards and mice, to the processing system
900.
[0062] The processing system 900 illustrated in FIG. 5 is only an
exemplary processing system with which the invention may be used.
While FIG. 5 illustrates a processing architecture especially
suitable for a general purpose computer, such as a personal
computer or a workstation, it should be recognized that well known
modifications can be made to configure the processing system 900 to
become more suitable for use in a variety of applications. For
example, many electronic devices, which require processing may be
implemented using a simpler architecture, which relies on a CPU
901, coupled to memory components 908 and/or memory devices 100.
These electronic devices may include, but are not limited to
audio/video processors and recorders, gaming consoles, digital
television sets, wired or wireless telephones, navigation devices
(including system based on the global positioning system (GPS)
and/or inertial navigation), and digital cameras and/or recorders.
The modifications may include, for example, elimination of
unnecessary components, addition of specialized devices or
circuits, and/or integration of a plurality of devices.
[0063] The above description and accompanying drawings are only
illustrative of an exemplary embodiment which can achieve the
features and advantages of the present invention. For example,
although the invention has been described as coupling an access
transistor 16 to a sense amplifier 50 by way of a bit line 31, it
should be noted that the memory device illustrated may have one
sense amplifier 50 associated with each access transistor 16, or
one sense amplifier 50 may be shared among access transistors 16
through a suitable decoding and switch arrangement. Other
variations in the illustrated architecture are also possible. Thus,
while the embodiment of the invention described above is
illustrative, it is not intended that the invention be limited to
the embodiments shown and described in detail herein. The invention
can be modified to incorporate any number of variations,
alterations, substitutions, or equivalent arrangements not
heretofore described, but which are commensurate with the spirit
and scope of the invention. Accordingly, the invention is not
limited by the foregoing description but is only limited by the
scope of the following claims.
* * * * *