Seyyedy; Mirmajid
Patent Applications and Registrations
Patent applications and USPTO patent grants for Seyyedy; Mirmajid.The latest application filed is for "hybrid mram array structure and operation".
Company Profile
0.52.31
- Seyyedy; Mirmajid - Boise ID
Patent Activity
| Patent | Date |
|---|---|
| Hybrid MRAM array structure and operation Grant 8,451,642 - Seyyedy , et al. May 28, 2 | 2013-05-28 |
| Hybrid Mram Array Structure And Operation App 20120188812 - Seyyedy; Mirmajid ; et al. | 2012-07-26 |
| Hybrid MRAM array structure and operation Grant 8,154,004 - Seyyedy , et al. April 10, 2 | 2012-04-10 |
| Stacked memory cell structure and method of forming such a structure Grant 7,978,491 - Nejad , et al. July 12, 2 | 2011-07-12 |
| Hybrid MRAM array structure and operation Grant 7,732,221 - Seyyedy , et al. June 8, 2 | 2010-06-08 |
| Hybrid Mrar Array Structure And Operation App 20100044668 - Seyyedy; Mirmajid ; et al. | 2010-02-25 |
| Method and apparatus for testing a memory device with compressed data using a single output Grant 7,562,268 - Seyyedy , et al. July 14, 2 | 2009-07-14 |
| Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation Grant 7,440,339 - Nejad , et al. October 21, 2 | 2008-10-21 |
| Stacked 1T-nmemory cell structure App 20080180982 - Nejad; Hasan ; et al. | 2008-07-31 |
| Magnetic tunneling junction antifuse device Grant 7,405,966 - Seyyedy , et al. July 29, 2 | 2008-07-29 |
| Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation Grant 7,339,811 - Nejad , et al. March 4, 2 | 2008-03-04 |
| Stacked 1T-nmemory cell structure Grant 7,339,812 - Nejad , et al. March 4, 2 | 2008-03-04 |
| Stacked 1T-nMTJ MRAM structure Grant 7,330,367 - Nejad , et al. February 12, 2 | 2008-02-12 |
| Magnetic Tunneling Junction Antifuse Device App 20070127303 - Seyyedy; Mirmajid ; et al. | 2007-06-07 |
| Columnar 1T-N memory cell structure Grant 7,209,378 - Nejad , et al. April 24, 2 | 2007-04-24 |
| Magnetic tunneling junction antifuse device Grant 7,176,065 - Seyyedy , et al. February 13, 2 | 2007-02-13 |
| Integrated Circuits With Contemporaneously Formed Array Electrodes And Logic Interconnects App 20070029630 - Seyyedy; Mirmajid ; et al. | 2007-02-08 |
| Integrated circuits with contemporaneously formed array electrodes and logic interconnects Grant 7,126,200 - Seyyedy , et al. October 24, 2 | 2006-10-24 |
| 1T-nmemory cell structure and its method of formation and operation App 20060171224 - Nejad; Hasan ; et al. | 2006-08-03 |
| Integrated circuits with contemporaneously formed array electrodes and logic interconnects App 20060099797 - Seyyedy; Mirmajid ; et al. | 2006-05-11 |
| Stacked 1T-nmemory cell structure Grant 7,042,749 - Nejad , et al. May 9, 2 | 2006-05-09 |
| Method and apparatus for testing a memory device with compressed data using a single output App 20060090108 - Seyyedy; Mirmajid ; et al. | 2006-04-27 |
| Stacked columnar 1T-nMTJ structure and its method of formation and operation Grant 7,023,743 - Nejad , et al. April 4, 2 | 2006-04-04 |
| Method and apparatus for testing a memory device with compressed data using a single output Grant 6,976,195 - Seyyedy , et al. December 13, 2 | 2005-12-13 |
| Stacked 1T-nmemory cell structure App 20050226041 - Nejad, Hasan ; et al. | 2005-10-13 |
| Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation App 20050226037 - Nejad, Hasan ; et al. | 2005-10-13 |
| Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation App 20050226038 - Nejad, Hasan ; et al. | 2005-10-13 |
| Stacked 1T-nMTJ MRAM structure Grant 6,940,748 - Nejad , et al. September 6, 2 | 2005-09-06 |
| Magnetic tunneling junction antifuse device App 20050190620 - Seyyedy, Mirmajid ; et al. | 2005-09-01 |
| Columnar 1T-nMemory cell structure and its method of formation and operation App 20050162883 - Nejad, Hasan ; et al. | 2005-07-28 |
| Stacked IT-nMTJ MRAM structure App 20050162898 - Nejad, Hasan ; et al. | 2005-07-28 |
| Magnetic tunneling junction antifuse device Grant 6,919,613 - Seyyedy , et al. July 19, 2 | 2005-07-19 |
| Stacked 1T-nMTJ MRAM structure Grant 6,882,566 - Nejad , et al. April 19, 2 | 2005-04-19 |
| Stacked columnar resistive memory structure and its method of formation and operation Grant 6,882,553 - Nejad , et al. April 19, 2 | 2005-04-19 |
| Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation Grant 6,879,516 - Nejad , et al. April 12, 2 | 2005-04-12 |
| Stacked 1T-nMTJ MRAM structure App 20040264242 - Nejad, Hasan ; et al. | 2004-12-30 |
| Flip chip technique for chip assembly Grant 6,831,361 - Seyyedy December 14, 2 | 2004-12-14 |
| Hybrid MRAM array structure and operation App 20040213044 - Seyyedy, Mirmajid ; et al. | 2004-10-28 |
| Magnetic tunneling junction antifuse device App 20040188799 - Seyyedy, Mirmajid ; et al. | 2004-09-30 |
| Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation App 20040165461 - Nejad, Hasan ; et al. | 2004-08-26 |
| Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation App 20040165421 - Nejad, Hasan ; et al. | 2004-08-26 |
| Flip-chip technique for chip assembly Grant 6,780,675 - Seyyedy August 24, 2 | 2004-08-24 |
| Integrated circuits with contemporaneously formed array electrodes and logic interconnects App 20040160795 - Seyyedy, Mirmajid ; et al. | 2004-08-19 |
| Hybrid MRAM array structure and operation Grant 6,754,124 - Seyyedy , et al. June 22, 2 | 2004-06-22 |
| Single ended row select for a MRAM device Grant 6,751,117 - Voshell , et al. June 15, 2 | 2004-06-15 |
| Magnetic tunneling junction antifuse device Grant 6,751,149 - Seyyedy , et al. June 15, 2 | 2004-06-15 |
| Error correction chip for memory applications Grant 6,725,414 - Seyyedy April 20, 2 | 2004-04-20 |
| Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation App 20040057276 - Nejad, Hasan ; et al. | 2004-03-25 |
| Hybrid MRAM array structure and operation App 20030227795 - Seyyedy, Mirmajid ; et al. | 2003-12-11 |
| Stacked 1T-nmemory cell structure App 20030223292 - Nejad, Hasan ; et al. | 2003-12-04 |
| Stacked 1t-nmtj Mram Structure App 20030214835 - Nejad, Hasan ; et al. | 2003-11-20 |
| Single ended row select for a MRAM device App 20030202401 - Voshell, Tom W. ; et al. | 2003-10-30 |
| Magnetic tunneling junction antifuse device App 20030179601 - Seyyedy, Mirmajid ; et al. | 2003-09-25 |
| Single ended row select for a MRAM device App 20030043619 - Voshell, Tom W. ; et al. | 2003-03-06 |
| Error correction chip for memory applications App 20020049951 - Seyyedy, Mirmajid | 2002-04-25 |
| Flip chip technique for chip assembly App 20010050432 - Seyyedy, Mirmajid | 2001-12-13 |
| Error correction chip for memory applications Grant 6,282,689 - Seyyedy August 28, 2 | 2001-08-28 |
| Column select latch for SDRAM App 20010009529 - Seyyedy, Mirmajid ; et al. | 2001-07-26 |
| Flip chip technique for chip assembly Grant 6,265,775 - Seyyedy July 24, 2 | 2001-07-24 |
| Flip chip technique for chip assembly App 20010008777 - Seyyedy, Mirmajid | 2001-07-19 |
| Laser antifuse using gate capacitor Grant 6,252,293 - Seyyedy , et al. June 26, 2 | 2001-06-26 |
| Method for making three dimensional ferroelectric memory Grant 6,004,825 - Seyyedy December 21, 1 | 1999-12-21 |
| Ferroelectric memory using ferroelectric reference cells Grant 5,999,439 - Seyyedy December 7, 1 | 1999-12-07 |
| Multi bank test mode for memory devices Grant 5,996,106 - Seyyedy November 30, 1 | 1999-11-30 |
| Three dimensional ferroelectric memory Grant 5,969,380 - Seyyedy October 19, 1 | 1999-10-19 |
| Fuse option for multiple logic families on the same die Grant 5,926,034 - Seyyedy July 20, 1 | 1999-07-20 |
| Error correction chip for memory applications Grant 5,923,682 - Seyyedy July 13, 1 | 1999-07-13 |
| Destructive read protection using address blocking technique Grant 5,907,861 - Seyyedy May 25, 1 | 1999-05-25 |
| Ferroelectric memory using ferroelectric reference cells Grant 5,905,672 - Seyyedy May 18, 1 | 1999-05-18 |
| Low voltage dynamic memory Grant 5,856,939 - Seyyedy January 5, 1 | 1999-01-05 |
| Ferroelectric memory using non-remnant reference circuit Grant 5,847,989 - Seyyedy December 8, 1 | 1998-12-08 |
| Column select latch for SDRAM Grant 5,835,441 - Seyyedy , et al. November 10, 1 | 1998-11-10 |
| Circuit for implementing and method for initiating a self-refresh mode Grant 5,818,777 - Seyyedy October 6, 1 | 1998-10-06 |
| Laser antifuse using gate capacitor Grant 5,811,869 - Seyyedy , et al. September 22, 1 | 1998-09-22 |
| Ferroelectric memory using ferroelectric reference cells Grant 5,751,626 - Seyyedy May 12, 1 | 1998-05-12 |
| Circuit and method of operating a ferrolectric memory in a DRAM mode Grant 5,680,344 - Seyyedy October 21, 1 | 1997-10-21 |
| Ferroelectric memory using reference charge circuit Grant 5,677,865 - Seyyedy October 14, 1 | 1997-10-14 |
| Ferroelectric memory using ferroelectric reference cells Grant 5,638,318 - Seyyedy June 10, 1 | 1997-06-10 |
| Low voltage dynamic memory Grant 5,636,170 - Seyyedy June 3, 1 | 1997-06-03 |
| Multiport RAM based multiprocessor Grant 5,555,429 - Parkinson , et al. September 10, 1 | 1996-09-10 |
| Multiport RAM based multiprocessor Grant 5,475,631 - Parkinson , et al. December 12, 1 | 1995-12-12 |
| Structure for a semiconductor device comprising conductive trench sidewalls Grant 5,376,817 - Seyyedy , et al. December 27, 1 | 1994-12-27 |
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