U.S. patent application number 11/365063 was filed with the patent office on 2006-07-06 for semiconductor device having a capping layer including cobalt and method of fabricating the same.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Jung-Wook Kim, Hyeon-Deok Lee, In-Sun Park, Ji-Soon Park.
Application Number | 20060145269 11/365063 |
Document ID | / |
Family ID | 36639435 |
Filed Date | 2006-07-06 |
United States Patent
Application |
20060145269 |
Kind Code |
A1 |
Kim; Jung-Wook ; et
al. |
July 6, 2006 |
Semiconductor device having a capping layer including cobalt and
method of fabricating the same
Abstract
A semiconductor device, and a method of fabricating the same,
includes cobalt as a capping layer. An interconnection structure of
the semiconductor device has an improved via resistance. In the
semiconductor device, a single cobalt layer or a composite film
including a cobalt layer and a titanium nitride layer is used as
the capping layer of a metal layer.
Inventors: |
Kim; Jung-Wook;
(Gyeonggi-do, KR) ; Lee; Hyeon-Deok; (Seoul,
KR) ; Park; In-Sun; (Gyeoggi-do, KR) ; Park;
Ji-Soon; (Gyeonggi-do, KR) |
Correspondence
Address: |
MARGER JOHNSON & MCCOLLOM, P.C.
210 SW MORRISON STREET, SUITE 400
PORTLAND
OR
97204
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Suwon-si
KR
|
Family ID: |
36639435 |
Appl. No.: |
11/365063 |
Filed: |
February 28, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10916303 |
Aug 10, 2004 |
7037828 |
|
|
11365063 |
Feb 28, 2006 |
|
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Current U.S.
Class: |
257/383 ;
257/763; 257/E21.584; 257/E23.019; 257/E23.145 |
Current CPC
Class: |
H01L 23/485 20130101;
H01L 2221/1078 20130101; H01L 2924/00 20130101; H01L 2924/0002
20130101; H01L 21/7685 20130101; H01L 2924/0002 20130101; H01L
21/76841 20130101 |
Class at
Publication: |
257/383 ;
257/763; 257/E23.145 |
International
Class: |
H01L 29/94 20060101
H01L029/94; H01L 23/48 20060101 H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 27, 2003 |
KR |
2003-59492 |
Claims
1. A semiconductor device, comprising: a semiconductor substrate on
which a structure including a transistor is formed; a lower capping
layer formed on the semiconductor substrate; a metal layer formed
on the lower capping layer; an upper capping layer formed on the
metal layer, covering substantially the entire surface of the metal
layer and including at least a cobalt layer; an interlayer
insulating layer pattern formed on the upper capping layer and
having a contact hole therethrough; and a contact plug filling the
contact hole of the interlayer insulating layer pattern.
2. The semiconductor device of claim 1, wherein the upper capping
layer is formed of one selected from a composite film including a
cobalt layer and a titanium nitride layer stacked sequentially, and
a cobalt layer.
3. The semiconductor device of claim 1, wherein the lower capping
layer is one selected from the group consisting of a composite film
including a cobalt layer and a titanium nitride layer stacked
sequentially, a cobalt layer, and a composite film including a
titanium layer and a titanium nitride layer stacked
sequentially.
4. The semiconductor device of claim 1, wherein the metal layer is
composed of aluminum.
5. The semiconductor device of claim 1, wherein the interlayer
insulating layer pattern is an oxide-based composite film.
6. A semiconductor device comprising: a semiconductor substrate on
which a structure including a transistor is formed; a lower capping
layer formed on the semiconductor substrate and including at least
one cobalt layer; a metal layer formed on the lower capping layer;
an upper capping layer formed on the metal layer and covering
substantially the entire surface of the metal layer; an interlayer
insulating layer pattern formed on the upper capping layer and
having a contact hole therethrough; and a contact plug filling the
contact hole of the interlayer insulating layer pattern.
7. The semiconductor device of claim 6, wherein the lower capping
layer is one selected from the group consisting of a composite film
including a cobalt layer and a titanium nitride layer stacked
sequentially, and a cobalt layer.
8. The semiconductor device of claim 6, wherein the upper capping
layer is one selected from the group consisting of a composite film
including a cobalt layer and a titanium nitride layer stacked
sequentially, a cobalt layer, and a composite film including a
titanium layer and a titanium nitride layer stacked sequentially.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Divisional of U.S. patent application
Ser. No. 10/916,303, filed Aug. 10, 2004, now pending, which claims
priority from Korean Patent Application No. 2003-59492, filed on
Aug. 27, 2003, which is incorporated by reference in its
entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device and
a method of fabricating the same, and more particularly, to a
capping layer of a metal pattern formed in a back-end process among
semiconductor device fabrication processes.
[0004] 2. Description of the Related Art
[0005] As the integration of semiconductor devices increases, the
design rules of semiconductor devices must account for decreasing
structure sizes. As the design rule decreases, the size of an
individual device such as a transistor in a semiconductor device
decreases also, and the process for interconnecting the individual
devices via a metal interconnection becomes more important. In
particular, in semiconductor devices requiring high speed
operation, various attempts to reduce the resistance of the metal
interconnection are being made.
[0006] Examples of such attempts to reduce the interconnection
resistance include replacing the metal interconnection of aluminum
(Al) with a metal interconnection of copper (Cu), using a barrier
layer in a contact hole to connect the metal interconnections.
[0007] A prior art example of using a cobalt layer as the barrier
layer in a contact hole is disclosed in U.S. Pat. No. 5,998,873.
However, this prior art is directed not to a capping layer covering
the entire surface of the metal layer, but to a cobalt layer
restricted only to the inside of the contact hole.
SUMMARY OF THE INVENTION
[0008] The present invention provides a semiconductor device
employing a cobalt layer as a capping layer so as to improve via
resistance of the semiconductor device.
[0009] The present invention also provides a method of
manufacturing a semiconductor device with a cobalt layer employed
as a capping layer.
[0010] According to an embodiment of the present invention, there
is provided a semiconductor device comprising: a semiconductor
substrate on which a structure including a transistor is formed; a
lower capping layer formed on the semiconductor substrate; a metal
layer formed on the lower capping layer; an upper capping layer
formed on the metal layer, covering an entire surface of the metal
layer, and including at least a cobalt layer; an interlayer
insulating layer pattern formed on the upper capping layer, and
having a contact hole; and a contact plug filling the contact hole
of the interlayer insulating layer pattern.
[0011] The lower capping layer may be one selected from the group
consisting of a composite film including a cobalt layer and a
titanium nitride layer stacked sequentially, a cobalt layer, and a
composite film including a titanium layer and a titanium nitride
layer stacked sequentially.
[0012] According to another embodiment of the present invention,
there is provided a semiconductor device comprising: a
semiconductor substrate on which a structure including a transistor
is formed; a lower capping layer formed on the semiconductor
substrate, and including at least one cobalt layer; a metal layer
formed on the lower capping layer; an upper capping layer formed on
the metal layer, and covering substantially the entire surface of
the metal layer; an interlayer insulating layer pattern formed on
the upper capping layer, and having a contact hole; and a contact
plug filling the contact hole of the interlayer insulating layer
pattern.
[0013] The upper capping layer may be one selected from the group
consisting of a composite film including a cobalt layer and a
titanium nitride layer stacked sequentially, a single cobalt layer,
and a composite film including a titanium layer and a titanium
nitride layer stacked sequentially.
[0014] According to yet another embodiment of the present
invention, there is provided a method of manufacturing a
semiconductor device, the method comprising: preparing a
semiconductor substrate on which a structure including a transistor
is formed; forming a lower capping layer on the semiconductor
substrate; forming a metal layer on the lower capping layer;
forming an upper capping layer including at least one cobalt layer
on the metal layer to cover substantially the entire surface of the
metal layer; patterning the upper capping layer and the metal layer
to form a metal layer pattern; performing an alloy process on the
metal layer pattern; forming an interlayer insulating layer pattern
with a contact hole on the upper capping layer; and forming a
contact plug in the contact hole of the interlayer insulating layer
pattern.
[0015] The upper capping layer may be one of a cobalt layer, and a
composite film including a cobalt layer and a titanium nitride
layer stacked sequentially.
[0016] Also, the lower capping layer may be one selected from the
group consisting of a cobalt layer, a composite film including a
cobalt layer and a titanium nitride layer stacked sequentially, and
a composite film including a titanium layer and a titanium nitride
layer stacked sequentially.
[0017] According to still another embodiment of the present
invention, there is provided a method of manufacturing a
semiconductor device, the method comprising: preparing a
semiconductor substrate on which a structure including a transistor
is formed; forming a lower capping layer including at least one
cobalt layer on the semiconductor substrate; forming a metal layer
on the lower capping layer; forming an upper capping layer on the
metal layer to cover substantially the entire surface of the metal
layer; patterning the upper capping layer and the metal layer to
form a metal layer pattern; performing an alloy process on the
metal layer pattern; forming an interlayer insulating layer pattern
with a contact hole on the capping layer; and forming a contact
plug in the contact hole of the interlayer insulating layer
pattern.
[0018] The lower capping layer may be one of a cobalt layer, and a
composite film including a cobalt layer and a titanium nitride
layer stacked sequentially.
[0019] The upper capping layer may be one selected from the group
consisting of a cobalt layer, a composite film including a cobalt
layer and a titanium nitride layer stacked sequentially, and a
composite film including a titanium layer and a titanium nitride
layer stacked sequentially.
[0020] According to the embodiments of the present invention, a
cobalt layer or a composite film including a cobalt layer is used
as the capping layer of the metal layer to improve via resistance
in the metal interconnection process, thereby improving the speed
performance of a semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and other features and advantages of the present
invention will become more apparent by describing in detail
exemplary embodiments thereof with reference to the attached
drawings in which:
[0022] FIG. 1 is a sectional view of a semiconductor device
employing a single cobalt layer as an upper capping layer according
to a first embodiment of the present invention;
[0023] FIG. 2 is a sectional view of a semiconductor device
employing a composite film of a cobalt layer and a titanium nitride
layer as an upper capping layer according to a second embodiment of
the present invention;
[0024] FIG. 3 is a sectional view of a semiconductor device
employing a single cobalt layer as a lower capping layer according
to a third embodiment of the present invention;
[0025] FIG. 4 is a sectional view of a semiconductor device
employing a composite film of a cobalt layer and a titanium nitride
layer as a lower capping layer according to a fourth embodiment of
the present invention; and
[0026] FIGS. 5 to 7 are graphs for illustrating a via resistance
when a composite film is employed as an upper capping layer in a
semiconductor device as shown in FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
[0027] The present invention will now be described more fully with
reference to the accompanying drawings, in which exemplary
embodiments of the invention are shown. This invention may,
however, be embodied in many different forms and should not be
construed as being limited to the embodiments set forth herein;
rather, these embodiments are provided so that this disclosure will
be thorough and complete, and will fully convey the concept of the
invention to those skilled in the art.
[0028] It will be understood by those of ordinary skill in the art
that various changes in form and details may be made to be
embodiments without departing from the spirit and scope of the
present invention. For instance, a cobalt layer may be replaced by
an equivalent layer having a low resistivity such as a nickel (Ni)
layer or a copper (Cu) layer. Also, it will be understood by those
of ordinary skill in the art that in the below exemplary
embodiments, the composite layer of a cobalt layer and a titanium
nitride layer used as the capping layer can be replaced by a
composite layer of a nickel layer and a titanium nitride layer or a
composite layer of a copper layer and a titanium nitride layer.
[0029] FIG. 1 is a sectional view of a semiconductor device
employing a single cobalt layer as an upper capping layer according
to the first embodiment of the present invention.
[0030] Referring to FIG. 1, the semiconductor device includes a
semiconductor substrate 100 having a structure including a
transistor formed thereon. A lower capping layer 110 is formed on
the semiconductor substrate 100 and a metal layer 104 formed on the
lower capping layer 110 acts as a metal interconnection. An upper
capping layer 102 formed of cobalt is disposed on the metal layer
104, and an interlayer insulating layer 106 with a contact hole is
disposed on the upper capping layer 102. A contact plug 108 fills
the contact hole of the interlayer insulating layer 106.
[0031] The capping layers 102 and 110 cover substantially the
entire surfaces of the metal layer 104, thereby enhancing the
conductivity of the metal interconnection, and have different
characteristics than the characteristics of the layer formed only
inside the contact hole. Also, the capping layers 102 and 110 are
formed in the back-end process of semiconductor fabrication after
forming transistors.
[0032] The lower capping layer 110 can be formed of various
materials that enhance the conductivity of the metal layer 104. For
instance, the lower capping layer 110 can be formed of one selected
from the group consisting of a single cobalt layer identical to the
upper capping layer 102, a composite film of a cobalt layer and a
titanium nitride layer, and a composite film of a titanium layer
and a titanium nitride layer.
[0033] The metal layer 104 can be formed of aluminum (Al). The
interlayer insulating layer 106 may be formed of an oxide-based
composite film, for example, a composite film of a TEOS layer and a
Fox layer. The contact plug 108 may be formed of tungsten or
aluminum reflow.
[0034] Cobalt used to form the upper capping layer 102 has a
relative resistance of 18 .mu..OMEGA., which is very low compared
to 66 .mu..OMEGA., the relative resistance of titanium (Ti). Hence,
if the upper capping layer 102 is formed of cobalt on the metal
layer 104 at a thickness of approximately 50-1,000 angstroms, the
via resistance of the metal interconnection is remarkably improved,
thereby enhancing the electrical performance and the speed of a
semiconductor device, such as SRAM.
[0035] FIG. 2 is a sectional view of a semiconductor device
employing a composite film of a cobalt layer and a titanium nitride
layer as an upper capping layer according to the second embodiment
of the present invention. A description of components identical to
components in the device of FIG. 1 is omitted.
[0036] As opposed to the semiconductor device according to the
first embodiment, the semiconductor device of the second embodiment
includes an upper capping layer 102 composed of a composite film of
a cobalt layer 112 and a titanium nitride layer 114, not a single
cobalt layer. Accordingly, the upper capping layer 102 acts as an
anti reflective layer (ARL) when patterning the metal layer 104.
Also, the titanium nitride layer 114 of the upper capping layer
acts as an etching stopper when forming a contact hole in the
interlayer insulating layer 106. Preferably, the cobalt layer 112
is formed by an in-situ process to a thickness range of 20-500
angstroms and the titanium nitride layer 114 is formed by an
in-situ process using a sputtering apparatus to a thickness range
of 100-1,000 angstroms.
[0037] A method of manufacturing a semiconductor device having a
cobalt layer will now be described with reference to FIG. 2.
[0038] First, a semiconductor substrate 100 having a structure
including a transistor formed thereon is prepared. The structure is
preferably a structure requiring fast speed, such as SRAM. Next, a
metal interconnection is formed. For this purpose, a composite film
of a titanium layer and a titanium nitride (TiN) layer is formed as
a lower capping layer 110 on the semiconductor substrate 100. The
lower capping layer 110 is preferably formed using an SIP
(Self-Ionized Plasma) sputtering method such that the titanium
layer has a thickness of, for example, 150 angstroms and the
titanium nitride layer has a thickness of, for example, 300
angstroms. The lower capping layer 110 may also be a single cobalt
layer or a composite film of a cobalt layer and a titanium nitride
layer.
[0039] Then, a metal layer 104, for example, an aluminum layer, is
deposited by a conventional thin film deposition process such as a
sputtering process. Thereafter, an upper capping layer 102 is
formed on the metal layer 104. For this purpose, a cobalt layer 112
is first formed by an ALPS (Al Low Pressure Sputtering) process. To
form the cobalt layer 112, the semiconductor substrate 100 on which
the lower capping layer 110 and the metal layer 104 are formed is
positioned on an ESC (Electro-Static Chuck), and then an Ar gas is
supplied as a carrier gas at a temperature of about 150.degree. C.
Preferably, the cobalt layer 112 is formed to a thickness of, for
example, 50 angstroms. Next, a titanium nitride layer 114 is formed
to a thickness of approximately 400 angstroms on the cobalt layer
112 using a generally well-known process. Preferably, the cobalt
layer 112 and the titanium nitride layer 114 are formed in-situ by
the sputtering apparatus.
[0040] Thereafter, the upper capping layer 102 and the metal layer
104 are patterned, thereby forming a metal layer pattern. For this
purpose, a hard mask pattern including a composite film of a SiON
layer and a PEOX layer may be formed as an ARL on the upper capping
layer 102. The upper capping layer 102 and the metal layer 104 are
etched using the hard mask pattern as an etch mask.
[0041] An alloy process is formed on the resultant structure. For
the alloy process, a TEOS layer with a thickness of about 500
angstroms is deposited on the resultant structure. Then, the
resultant structure is thermally annealed in a hydrogen atmosphere
at a temperature of about 380.degree. C. for about 30 minutes. This
alloy process is performed to suppress the occurrence of an
electro-migration (EM) phenomenon in which the metal layer 104 is
moved by heat during a subsequent process, and to suppress the
occurrence of voids in a subsequent process of filling a via
contact hole with a conductive material.
[0042] Thereafter, an interlayer insulating layer 106 is deposited
on the resultant structure, and is then planarized by a
conventional planarization process such as chemical mechanical
polishing (CMP). The interlayer insulating layer 106 can be a
composite film including a Fox layer with a thickness of, for
example, 2,600 angstroms and a TEOS layer with a thickness of 4,000
angstroms. Then, the interlayer insulating layer 106 is patterned
to form a via contact hole exposing a part of the upper capping
layer 102. The titanium nitride layer 114 of the upper capping
layer 102 functions as an etching stopper when the via contact hole
is formed. Thereafter, a contact plug 108 filling the contact hole
is formed of aluminum reflow or tungsten.
[0043] FIG. 3 is a sectional view of a semiconductor device
employing a single cobalt layer as a lower capping layer according
to the third embodiment of the present invention, and FIG. 4 is a
sectional view of a semiconductor device employing a composite film
of a cobalt layer and a titanium nitride layer as a lower capping
layer according to the fourth embodiment of the present invention.
The description overlapping with that of the aforementioned first
embodiment will be omitted hereinbelow.
[0044] Referring to FIGS. 3 and 4, a semiconductor device includes
a single cobalt layer as a lower capping layer 202 or a composite
film including a cobalt layer 212 and a titanium nitride layer 214
as the lower capping layer 202. As in the first and second
embodiments, the upper capping layer 210 can be formed of various
materials that enhance the conductivity of a metal layer 204. For
instance, the upper capping layer 210 can be formed of one selected
from the group consisting of a single cobalt layer identical to the
lower capping layer 202, a composite film including a cobalt layer
and a titanium nitride layer, and a composite film including a
titanium layer and a titanium nitride layer.
[0045] FIGS. 5 to 7 are graphs illustrating a via resistance when a
composite film is employed as an upper capping layer in a
semiconductor device as shown in FIG. 2.
[0046] Referring to FIGS. 5 to 7, a semiconductor substrate was
fabricated using the composite film including the cobalt layer and
the titanium nitride layer as the upper capping layer as
illustrated in FIG. 2. For the comparison, a conventional
semiconductor device employing a composite film including a
titanium layer and a titanium nitride layer as an upper capping
layer was used. Except for the upper capping layer, the structure
was the same for the two cases. Also, except for the forming of the
upper capping layer, the methods of fabricating the semiconductor
devices were identical. Via resistances were measured in both
cases. Here, FIG. 5 corresponds to a case where the via contact
hole of the interlayer insulating layer has a critical dimension of
0.34 .mu.m, FIG. 6 corresponds to a case where the via contact hole
of the interlayer insulating layer has a thickness of 0.36 .mu.m,
and FIG. 7 corresponds to a case where the via contact hole of the
interlayer insulating layer has a critical dimension of 0.38
.mu.m.
[0047] In each graph, the Y-axis indicates distribution and the
X-axis indicates resistance. Lines represented by .circle-solid.
correspond to a case when the composite film including cobalt layer
(50 {hacek over (A)}) and a titanium nitride layer (400 angstroms)
was employed as the upper capping layer like FIG. 2, and Lines
represented by .box-solid. correspond to a case where the composite
film including a titanium layer (50 angstroms) and a titanium
nitride layer (400 angstroms) was employed as the upper capping
layer.
[0048] In a semiconductor device having via contact holes with
different sizes, when the composite film including cobalt layer (50
angstroms) and a titanium nitride layer (400 angstroms) was
employed as the upper capping layer, the via resistance was 1-3
.OMEGA./cm, and in the case where the composite film of titanium
layer (50 angstroms)/titanium nitride layer (400 angstroms) was
employed as the upper capping layer, the via resistance was 4-7
.OMEGA./cm. This result shows that the via resistance
characteristics of the capping layer including the cobalt layer are
improved by about 200%.
[0049] As described above, according to embodiments of the present
invention, among others, when a cobalt layer or a composite film
including a cobalt layer is used as the capping layer of the metal
layer, it is possible to improve via resistance of the metal
interconnection.
[0050] While the present invention has been particularly shown and
described with reference to exemplary embodiments thereof, it will
be understood by those of ordinary skill in the art that various
changes in form and details may be made therein without departing
from the spirit and scope of the present invention as defined by
the following claims.
* * * * *