U.S. patent application number 11/298012 was filed with the patent office on 2006-06-22 for semiconductor wafer with an epitaxially deposited layer, and process for producing the semiconductor wafer.
This patent application is currently assigned to Siltronic AG. Invention is credited to Gerhard Huettl, Rupert Krautbauer, Andrej Lenz, Erwin-Peter Mayer, Rainer Winkler.
Application Number | 20060131649 11/298012 |
Document ID | / |
Family ID | 36580173 |
Filed Date | 2006-06-22 |
United States Patent
Application |
20060131649 |
Kind Code |
A1 |
Krautbauer; Rupert ; et
al. |
June 22, 2006 |
Semiconductor wafer with an epitaxially deposited layer, and
process for producing the semiconductor wafer
Abstract
A semiconductor wafer is formed of a substrate wafer of single
crystal silicon doped with dopant atoms of the n type or p type,
with a front surface and a back surface, contains a layer deposited
epitaxially on the front surface of the substrate wafer. The
substrate wafer additionally includes an n.sup.++ or p.sup.++ doped
layer, which extends from the front surface of the substrate wafer
into the substrate wafer and has a defined thickness. The
semiconductor wafer is produced by a process in which dopant atoms
of the n type or p type are introduced into the substrate wafer
through the front surface of the substrate wafer, the dopant
concentration in a layer which extends from the front surface of
the substrate wafer into the substrate wafer being increased from
the level n.sup.+ or p.sup.+ to the level n.sup.++ or p.sup.++, and
an epitaxial layer is then deposited on this layer.
Inventors: |
Krautbauer; Rupert;
(Portland, OR) ; Huettl; Gerhard; (Engelsberg,
DE) ; Lenz; Andrej; (Tittmoning, DE) ; Mayer;
Erwin-Peter; (Burghausen, DE) ; Winkler; Rainer;
(Zorneding, DE) |
Correspondence
Address: |
BROOKS KUSHMAN P.C.
1000 TOWN CENTER
TWENTY-SECOND FLOOR
SOUTHFIELD
MI
48075
US
|
Assignee: |
Siltronic AG
Munich
DE
|
Family ID: |
36580173 |
Appl. No.: |
11/298012 |
Filed: |
December 9, 2005 |
Current U.S.
Class: |
257/347 ;
257/E21.129; 257/E29.109; 438/222; 438/514 |
Current CPC
Class: |
H01L 29/36 20130101;
H01L 29/0878 20130101 |
Class at
Publication: |
257/347 ;
438/222; 438/514 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 16, 2004 |
DE |
10 2004 060 624.2 |
Claims
1. A semiconductor wafer comprising a substrate wafer of single
crystal silicon doped with dopant atoms of the n type or p type,
with a front surface and a back surface, an epitaxial layer on the
front surface, and an n.sup.++ or p.sup.++ doped layer with a lower
resistivity than the substrate wafer, positioned below the
epitaxial layer and extending into the substrate wafer.
2. The semiconductor wafer of claim 1, wherein the n.sup.++ or
p.sup.++ doped layer is substantially devoid of dislocations.
3. The semiconductor wafer of claim 1, wherein the thickness of the
substrate wafer is less than 120 .mu.m.
4. The semiconductor wafer of claim 1, wherein electronic
components are integrated in the epitaxially deposited layer.
5. The semiconductor wafer of claim 1, wherein the thickness of the
semiconductor wafer following a process for fabricating electronic
components is less than 120 .mu.m.
6. An electronic component, such as a power MOSFET, a power IC or
an IGBT, fabricated from the semiconductor wafer of claim 1.
7. A process for producing an epitaxially coated semiconductor
wafer with low resistivity below the epitaxial layer, comprising
providing a substrate wafer of single crystal silicon doped with
dopant atoms of the n type or p type and having a front surface and
a back surface, forming a layer on the front surface of the
substrate wafer by introducing additional dopant atoms of the n
type or p type into the substrate wafer through the front surface
of the substrate wafer, the dopant concentration in this layer
which extends from the front surface of the substrate wafer into
the substrate wafer being increased from the level n.sup.+ or
p.sup.+ to the level n.sup.++ or p.sup.++, and depositing an
epitaxial layer is deposited on the front surface of the substrate
wafer.
8. The process of claim 7, wherein the dopants are introduced into
the substrate wafer by diffusion.
9. The process of claim 7, wherein the dopants are introduced into
the substrate wafer by implantation.
10. The process of claim 7, wherein the back surface of the
substrate wafer is ground.
11. The process of claim 7, wherein the thickness of the substrate
wafer is reduced following a process for fabricating electronic
components.
12. The process of claim 11, wherein the back surface of the
substrate wafer is ground.
13. The process of claim 7, further comprising fabricating a
plurality of electronic components on the wafer, and removing them
from the back surface of the wafer sufficient thickness to remove
substantially all of the n.sup.+ or p.sup.+ doped single crystal
silicon.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a semiconductor wafer comprising a
silicon substrate wafer doped with dopant atoms of the n type or p
type and having a low resistance, with a front surface and a back
surface, and comprising a layer deposited epitaxially on the front
surface of the substrate wafer.
[0003] 2. Background Art
[0004] A semiconductor wafer of the type to which the invention is
directed is suitable, in particular, as a base material for the
fabrication of electronic power semiconductor components, with the
components being integrated in the epitaxially deposited layer (epi
layer) and the flow of current through such components usually
passing through the epi layer and the substrate beneath it. The
electrical resistance of power semiconductor components, in the on
state, is therefore dependent to a significant extent on the
resistivity of the substrate wafer, and this resistivity is
approximately inversely proportional to the concentration of the
dopant atoms. When producing the single crystal which is
subsequently divided into substrate wafers, the concentration of
these dopant atoms is usually set by the addition of dopant.
[0005] The processes for producing single crystals from silicon
which are in most widespread use on an industrial scale are the
Czochralski method (CZ method) and the float zone method (FZ
method). However, it is not possible to increase the concentration
of dopant atoms without restriction in such processes. If the
dopant concentrations in the melt are too high, dislocations which
disrupt the single crystal structure of the crystal are formed
during the pulling of single crystals using the CZ method. The
lowest substrate resistance which can be achieved by adding dopant
when producing the single crystal also depends on the type of
dopant and the size of the single crystal. In the case of
phosphorus, the lowest resistance produced in this way is in the
region of 0.71 mOhmcm. For crystals with a diameter of 150 mm or
200 mm, as are used for the industrial manufacture of the latest
generation of power semiconductor components, the lowest resistance
which can be achieved in practice is, however, above this value
(approx. 0.9 mOhmcm).
SUMMARY OF THE INVENTION
[0006] It is an object of the present invention to provide a
semiconductor wafer having an epitaxial layer, which comprises a
substrate wafer of single crystal silicon doped with dopant atoms
of the n type or p type, the resistivity of which is particularly
low. This and other objects are provided by an n type or p type
wafer which has an n.sup.++ or p.sup.++ layer extending into the
wafer and positioned below an epitaxial layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 illustrates the simulated resistance profile of a
highly doped substrate with additional diffusion of dopant.
[0008] FIG. 2 illustrates one type of semiconductor processing
employing the wafers of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0009] The invention thus relates to a semiconductor wafer
comprising a substrate wafer of single crystal silicon doped with
dopant atoms of the n type or p type, with a front surface and a
back surface, and comprising a layer deposited epitaxially on the
front surface of the substrate wafer, as well as an n.sup.++ or
p.sup.++ doped layer with a lower resistivity than the substrate
wafer, which extends below the epitaxial layer from the front
surface of the substrate wafer into the substrate wafer and has a
defined thickness.
[0010] The invention also relates to a process for producing a
semiconductor wafer of this type, wherein dopant atoms of the n
type or p type are introduced into the substrate wafer through the
front surface of the substrate wafer, the dopant concentration in a
layer which extends from the front surface of the substrate wafer
into the substrate wafer being increased from the level n.sup.+ or
p.sup.+ to the level n.sup.++ or p.sup.++, and wherein an epitaxial
layer is deposited on the front surface of the substrate wafer.
[0011] Semiconductor wafers in accordance with the present
invention are distinguished by a particularly low resistivity of
the substrate wafer and are therefore optimally suitable as base
material for the fabrication of power electronic semiconductor
components. According to a particularly preferred embodiment of the
process, the initial thickness of the substrate wafer is reduced by
removal of material on the back surface of the substrate wafer,
preferably to such an extent that the substrate wafer of reduced
thickness is predominantly or exclusively n.sup.++ or p.sup.++
doped, which additionally reduces the resistivity of the substrate
wafer. The removal of material from the back surface is usually
carried out by back grinding, but can in principle also be effected
using other techniques, such as lapping, polishing, CMP or etching.
Since the way in which the material is removed is not pertinent to
the invention, the following description mentions merely by way of
example the grinding of the back surface, without thereby
restricting the general nature of the invention.
[0012] After the grinding of the back surface, the substrate wafer
is preferably less than 120 .mu.m thick, particularly preferably
less than 80 .mu.m thick. The back surface of the substrate wafer
can be ground before or after the process for fabricating
semiconductor components, which is substantially carried out on the
front surface. Components which are integrated in the epitaxially
deposited layer are in particular power transistors, power MOSFETs,
power ICs or IGBTs.
[0013] The dopant atoms of the n type include phosphorus, arsenic
and antimony, and the dopant atoms of the p type include boron. A
dopant concentration of the n.sup.+ or p.sup.+ level is understood
by those skilled in the art to be present if it is generally no
longer possible to increase the concentration of the dopant by
adding more of the dopant in question to the melt during production
of the single crystal without the formation of dislocations, or if
production requires an extraordinarily high level of technical
outlay compared to lightly doped crystals. This applies in
particular if the resistivity at any position in the crystal drops
below defined limit values which are dependent on the type of
dopant and the crystal diameter. The limit value at which
dislocations may occur in conventional production processes, for
crystals with a diameter of 150 mm or 200 mm, is approximately 1
mOhmcm in the case of phosphorus, 2 mOhmcm in the case of arsenic,
10 mOhmcm in the case of antimony and 1 mOhmcm in the case of
boron. When producing single crystals using the CZ process, the
concentration of the dopant rises on account of segregation along
the crystal axis. Therefore, economic production of highly doped
single crystals with a low resistivity is only possible if the
crystals are devoid of dislocations over the entire length.
Problems with dislocations therefore arise even when producing
crystals with higher target resistances. Consequently, a dopant
concentration of the n.sup.+ or p.sup.+ level is present at a
resistivity of approximately 1.5 mOhmcm or below in the case of
phosphorus, 2.5 mOhmcm or below in the case of arsenic, 15 mOhmcm
or below in the case of antimony, and 2.5 mOhmcm or below in the
case of boron.
[0014] A dopant concentration of the n.sup.++ or p.sup.++ level is
present if a dopant concentration of the n.sup.+ or p.sup.+ level
is exceeded. This is the case in particular if the resistivity is
less than 1 mOhmcm for phosphorus, less than 2 mOhmcm for arsenic,
less than 10 mOhmcm for antimony and less than 1 mOhmcm for boron.
The theoretical maximum dopant concentration is given by the
solubility limit of the corresponding dopant and is approximately
8.times.10.sup.20/cm.sup.3 for boron, 1.3.times.10.sup.21/cm.sup.3
for phosphorus, 1.8.times.10.sup.21/cm.sup.3 for arsenic and
7.times.10.sup.19/cm.sup.3 for antimony (temperature range approx.
1000-1410.degree. C.). Under certain conditions, higher
concentrations may be present as metastable states, but under
equilibrium conditions a phase separation in the form of
precipitates commences.
[0015] According to the invention, the dopant concentration of the
substrate wafer is increased by further dopant of the same type
being forced into the substrate wafer by diffusion or implantation
through the front surface of the n.sup.+ or p.sup.+ doped substrate
wafer. According to a preferred procedure, additional dopant is
forced into the substrate wafer through the whole of the front
surface. However, it is also possible to mask individual regions of
the front surface and in this way to incorporate additional dopant
atoms in the crystal lattice in a patterned arrangement.
[0016] The result of the diffusion or implantation is a substrate
wafer made from single crystal silicon, which has an n.sup.++ or
p.sup.++ doped layer which extends from the front surface of the
substrate wafer down to a certain depth into the substrate wafer.
The thickness of this layer depends on the conditions, such as
duration, temperature, dopant concentration and dose at which the
diffusion or implantation of the additional dopant is carried out.
The transition between the n.sup.++ layer and the n.sup.+
substrate, or between the p.sup.++ layer and the p.sup.+ substrate,
may be relatively sharply defined or continuous, depending on the
process used. Irrespective of the type of transition, the thickness
of the layer is in this case defined as the thickness of the layer
in which the resistivity is at least 20% lower than in the original
substrate.
[0017] A thickness of at least 20 .mu.m is preferred, and a
thickness of more than 30 .mu.m is particularly preferred. The
advantageous effect of the invention is more pronounced the deeper
the layer extends into the substrate wafer and the thinner the
substrate wafer after the grinding of the back surface. The
n.sup.++ or p.sup.++ doped layer is substantially devoid of
dislocations.
[0018] An epitaxial layer, preferably a layer of silicon, which is
doped with a lower concentration of dopant atoms than the substrate
wafer, is deposited on the front surface of the substrate wafer.
The doping of the epitaxial layer may be of the same type as or of
the opposite type to that of the substrate. Doping of the epitaxial
layer of the same type as that of the substrate is preferred. Power
semiconductor components, such as power transistors, power MOSFETs,
power ICs or IGBTs, are integrated in this epitaxial layer and are
singulated at the end of the process to form individual
components.
[0019] FIG. 1 shows the simulated profile of the resistivity in a
highly doped substrate (dopant phosphorus) after additional
diffusion of dopant (duration of diffusion t). The absolute
thickness of the highly doped layer (in this case n.sup.++) which
has diffused in is dependent on the duration of diffusion, the
temperature and the applied surface concentration of the dopant.
For other dopants, the profile is in qualitative terms very
similar, but the conduction type and thickness of the layer depend
on the type of dopant and the respective diffusion properties in
silicon.
[0020] FIG. 2 diagrammatically depicts the production process
according to the invention: dopant of the same type is made to
diffuse into the front surface of a highly doped silicon wafer (n
type or p type). An epitaxial layer, the doping of which is
significantly lower than that of the underlying substrate, is
deposited on the extremely high doped layer (n.sup.++ or p.sup.++)
formed in this way. Semiconductor components are formed on the
epitaxial layer of the wafer. After processing, the back surface of
the finished wafer is partially removed. This is usually done by
back grinding, but can in principle also be effected by other
techniques, such as lapping, polishing, CMP or etching.
[0021] While embodiments of the invention have been illustrated and
described, it is not intended that these embodiments illustrate and
describe all possible forms of the invention. Rather, the words
used in the specification are words of description rather than
limitation, and it is understood that various changes may be made
without departing from the spirit and scope of the invention.
* * * * *