U.S. patent application number 11/345253 was filed with the patent office on 2006-06-15 for compact system module with built-in thermoelectric cooling.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Kie Y. Ahn, Eugene H. Cloud, Leonard Forbes.
Application Number | 20060128059 11/345253 |
Document ID | / |
Family ID | 22508012 |
Filed Date | 2006-06-15 |
United States Patent
Application |
20060128059 |
Kind Code |
A1 |
Ahn; Kie Y. ; et
al. |
June 15, 2006 |
Compact system module with built-in thermoelectric cooling
Abstract
An improved integrated circuit package for providing built-in
heating or cooling to a semiconductor chip is provided. The
improved integrated circuit package provides increased operational
bandwidth between different circuit devices, e.g. logic and memory
chips. The improved integrated circuit package does not require
changes in current CMOS processing techniques. The structure
includes the use of a silicon interposer. The silicon interposer
can consist of recycled rejected wafers from the front-end
semiconductor processing. Micro-machined vias are formed through
the silicon interposer. The micro-machined vias include electrical
contacts which couple various integrated circuit devices located on
the opposing surfaces of the silicon interposer. The packaging
includes a Peltier element.
Inventors: |
Ahn; Kie Y.; (Chappaqua,
NY) ; Forbes; Leonard; (Corvallis, OR) ;
Cloud; Eugene H.; (Boise, ID) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH
121 S. 8TH STREET
SUITE 1600
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
22508012 |
Appl. No.: |
11/345253 |
Filed: |
February 1, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10606539 |
Jun 26, 2003 |
7022553 |
|
|
11345253 |
Feb 1, 2006 |
|
|
|
09144307 |
Aug 31, 1998 |
6586835 |
|
|
10606539 |
Jun 26, 2003 |
|
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|
Current U.S.
Class: |
438/108 ;
257/E21.705; 257/E23.008; 257/E23.01; 257/E23.067; 257/E23.082;
257/E25.029; 257/E25.032; 438/109; 438/122; 438/667 |
Current CPC
Class: |
H01L 2224/16235
20130101; H01L 2924/01082 20130101; Y10S 257/93 20130101; H01L
23/38 20130101; H01L 2924/01033 20130101; H01L 25/167 20130101;
H01L 2924/00014 20130101; G02B 6/4214 20130101; H01L 2924/10253
20130101; H01L 2224/056 20130101; H01L 2924/01077 20130101; H01L
2924/19107 20130101; H01L 23/48 20130101; H01L 2924/01078 20130101;
H01L 2224/73257 20130101; H01L 2924/01023 20130101; H01L 2224/48091
20130101; H01L 2924/01032 20130101; H01L 2224/16225 20130101; H01L
2224/16237 20130101; H01L 33/645 20130101; H01L 2924/01052
20130101; H01L 2924/10329 20130101; H01L 2924/14 20130101; H01L
24/48 20130101; H01L 2924/01029 20130101; H01L 2924/01051 20130101;
H01L 2224/48227 20130101; H01L 33/62 20130101; H01L 2924/12042
20130101; H01L 2224/73265 20130101; H01L 2924/12041 20130101; H01L
2224/056 20130101; H01L 2924/01045 20130101; H01L 2924/19041
20130101; H01L 2924/10253 20130101; H01L 2924/1301 20130101; H01L
2224/854 20130101; H01L 25/50 20130101; H01L 2224/854 20130101;
H01L 2924/01013 20130101; H01L 23/345 20130101; G02B 6/4232
20130101; H01L 2224/45099 20130101; H01L 2924/15173 20130101; H01L
23/147 20130101; H01L 2924/00 20130101; H01L 24/73 20130101; H01L
2924/00014 20130101; H01L 2924/1301 20130101; H01L 25/16 20130101;
H01L 2924/01006 20130101; H01L 21/486 20130101; H01L 2924/12042
20130101; H01L 2224/48091 20130101; H01L 2924/01038 20130101; H01L
23/49827 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2224/45015 20130101; H01L 2224/45099 20130101; H01L 2924/207
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 25/0652
20130101 |
Class at
Publication: |
438/108 ;
438/667; 438/109; 438/122 |
International
Class: |
H01L 21/60 20060101
H01L021/60 |
Claims
1. A method for packaging an integrated circuit, comprising:
providing a silicon interposer having opposing sides; coupling a
semiconductor chip to each of the opposing sides of the silicon
interposer; coupling the semiconductor chips on each side of the
silicon interposer to one another through the silicon interposer by
a number of micro-machined vias, wherein the micro-machined vias
provide electrical connections between the opposing sides of the
silicon interposer; coupling a metal-to-semiconductor junction to
at least one of the semiconductor chips, wherein the semiconductor
includes a doped complex oxide semiconductor.
2. The method of claim 1, wherein coupling a doped complex oxide
semiconductor includes coupling an n-doped complex oxide
semiconductor comprising Strontium (Sr) and Titanium (Ti).
3. The method of claim 1, wherein coupling a doped complex oxide
semiconductor includes coupling an oxygen deficient an n-doped
complex oxide semiconductor.
4. The method of claim 1, wherein the semiconductor chips include a
flip chip.
5. The method of claim 4, wherein a Peltier element is coupled to a
flip chip.
6. The method of claim 1, wherein the semiconductor chips includes
a memory chip.
7. The method of claim 6, wherein the memory chip includes at least
one of a dynamic random access memory (DRAM) chip, a flash memory
chip and a static random access memory (SRAM) chip.
8. The method of claim 6, wherein the semiconductor chips include
capacitors.
9. A method for packaging an integrated circuit, comprising:
providing a silicon interposer having opposing sides; coupling a
semiconductor chip to each of the opposing sides of the silicon
interposer; coupling the semiconductor chips on each side of the
silicon interposer to one another through the silicon interposer by
a number of micro-machined vias, wherein the micro-machined vias
provide electrical connections between the opposing sides of the
silicon interposer; coupling a metal-to-semiconductor junction to
at least one of the semiconductor chips, wherein the semiconductor
includes an n-doped superlattice comprising alternating layers of
(PbTeSe)m and (BiSb)n, where m and n are the number of PbTeSe and
BiSb monolayers per superlattice period.
10. The method of claim 9, wherein the semiconductor chips include
a flip chip.
11. The method of claim 10, wherein a Peltier element is coupled to
a flip chip.
12. The method of claim 9, wherein the semiconductor chips includes
a memory chip.
13. The method of claim 12, wherein the memory chip includes at
least one of a dynamic random access memory (DRAM) chip, a flash
memory chip and a static random access memory (SRAM) chip.
14. The method of claim 12, wherein the semiconductor chips include
capacitors.
15. A method for packaging an integrated circuit, comprising:
providing a silicon interposer having opposing sides; coupling a
semiconductor chip to each of the opposing sides of the silicon
interposer; coupling the semiconductor chips on each side of the
silicon interposer to one another through the silicon interposer by
a number of micro-machined vias, wherein the micro-machined vias
provide electrical connections between the opposing sides of the
silicon interposer; coupling a metal-to-semiconductor junction to
at least one of the semiconductor chips, wherein the semiconductor
includes either an n or p-doped semiconductor alloy formed between
Antimony (Sb) and transition metal (T) from Group VIII, including
Cobalt (Co), Rhodium (Rh), and Iridium (Ir), and wherein the alloy
has the general formula TSb3.
16. The method of claim 15, wherein the semiconductor chips include
a flip chip.
17. The method of claim 16, wherein a Peltier element is coupled to
a flip chip.
18. The method of claim 15, wherein the semiconductor chips
includes a memory chip.
19. The method of claim 16, wherein the memory chip includes at
least one of a dynamic random access memory (DRAM) chip, a flash
memory chip and a static random access memory (SRAM) chip.
20. The method of claim 16, wherein the semiconductor chips include
capacitors.
21. A method for cooling an integrated circuit, comprising:
providing a silicon interposer having opposing sides; coupling a
first semiconductor chip to a first side of the silicon interposer;
coupling a second semiconductor chip to a second side of the
silicon interposer, wherein a number of electrical connections
through the silicon interposer couple the first semiconductor chip
to the second semiconductor chip; forming a metal-to-semiconductor
junction which couples to the first semiconductor chip on the first
side of the silicon interposer, wherein forming the
metal-to-semiconductor junction includes forming a Copper (Cu) and
n or p-doped semiconductor junction, wherein the semiconductor is
selected from Bismuth Telluride (Bi2Te3), Lead Telluride (PbTe),
and Silicon Germanium (SiGe); and passing current through the
metal-to-semiconductor junction in a direction such that a Peltier
cooling effect occurs adjacent to the first semiconductor chip.
22. The method of claim 21, wherein the semiconductor chips include
a flip chip.
23. The method of claim 22, wherein a Peltier element is coupled to
a flip chip.
24. The method of claim 21, wherein the semiconductor chips
includes a memory chip.
25. The method of claim 24, wherein the memory chip includes at
least one of a dynamic random access memory (DRAM) chip, a flash
memory chip and a static random access memory (SRAM) chip.
26. The method of claim 21, wherein the semiconductor chips include
capacitors.
27. A method for cooling an integrated circuit, comprising:
providing a silicon interposer having opposing sides; coupling a
first plurality of semiconductor chips to a first side of the
silicon interposer; coupling at least one Peltier element to one of
the first side of the silicon interposer and on of the first
plurality of semiconductor chips; and coupling a second plurality
of semiconductor chips to a second side of the silicon interposer
wherein a number of electrical connections through the silicon
interposer couple the first plurality of semiconductor chips to the
second plurality of semiconductor chips.
28. The method of claim 27, wherein the first plurality of
semiconductor chips includes flip chips, and the at least one
Peltier element is coupled to a selected one of the flip chips.
29. The method of claim 27, wherein the second plurality of
semiconductor chips includes a memory chip.
30. The method of claim 29, wherein the memory chip includes at
least one of a dynamic random access memory (DRAM) chip, a flash
memory chip and a static random access memory (SRAM) chip.
31. The method of claim 29, wherein the second plurality includes
semiconductor chip capacitors.
Description
[0001] This application is a divisional of U.S. application Ser.
No. 10/606,539 filed Jun. 26, 2003, which is a divisional of U.S.
application Ser. No. 09/144,307 filed on Aug. 31, 1998, now U.S.
Pat. No. 6,586,835, which are incorporated herein by reference.
[0002] 1. Field of the Invention
[0003] The present invention relates generally to semiconductor
integrated circuits. More particularly, it pertains to a compact
system module with built-in thermoelectric cooling.
[0004] 2. Background of the Invention
[0005] Integrated circuit technology relies on transistors to
formulate vast arrays of functional circuits. The complexity of
these circuits requires the use of an ever increasing number of
linked transistors. As the number of transistors required
increases, the integrated circuitry dimensions shrink. It is one
objective in the semiconductor industry to construct transistors
and other discrete devices which occupy less surface area on a
given silicon chip/die. At the same time, the semiconductor
industry seeks to increase the speed and power offered by
integrated circuits. One approach to the latter challenge is
through the development of improved methods for electrically
connecting and packaging circuit devices which are fabricated on
the same or on different silicon chips.
[0006] Ideally, we would like to build a computing system by
fabricating all the necessary integrated circuits on one wafer or
chip, as compared with today's method of fabricating many chips of
different functions and packaging them to assemble a system. A true
"system on a chip" would greatly improve integrated circuit
performance and provide higher bandwidth. Unfortunately, it is very
difficult with today's technology to implement a truly
high-performance "system on a chip" because of vastly different
fabrication processes and different manufacturing yields for the
logic and memory circuits.
[0007] As a compromise, various "system modules" have been
introduced that electrically connect and package circuit devices
which are fabricated on the same or on different semiconductor
chips. These began with simply stacking two semiconductor chips,
e.g. a logic and memory chip, one on top of the other in an
arrangement commonly referred to as chip-on-chip (COC) structure.
Chip-on-chip structure most commonly utilizes micro bump bonding
technology (MBB) to electrically connect the two chips. Several
problems, however, remain inherent with this design structure. One
serious complication includes the heating which occurs most
seriously in connection with a logic chip such as a microprocessor.
In high-performance microprocessors, where CPUs are running at 500
MHz and dissipating up to 85 watts of power, cooling becomes a
crucial issue.
[0008] Usually, the cooling of such a package is accomplished by
forced air. In certain applications, however, forced air cooling is
not feasible or practical. Examples of such applications include
computers to be used in outer space, in a vacuum environment on
earth, or in clean rooms where air circulation is not desirable.
For these and other instances, a different method of cooling is
required. Another cooling method includes liquid cooling, such as
the forced water cooling used in the thermal conduction modules of
113M main frame computers and forced freon cooling used in Cray
supercomputers. Still, liquid cooling methods can also prove too
bulky, costly, and not easily adapted for use in compact
high-performance integrated circuit systems, e.g. portable
devices.
[0009] Thus, it is desirable to develop an improved structure and
method for cooling high performance integrated circuit systems.
Additionally, the improved structure and method should accommodate
a dense integration and packaging for semiconductor chips, e.g.
logic and memory chips.
SUMMARY OF THE INVENTION
[0010] The above mentioned problems with integrated circuits and
other problems are addressed by the present invention and will be
understood by reading and studying the following specification. An
integrated circuit package which accords improved performance is
provided.
[0011] In particular, an improved integrated circuit package for
providing built-in heating or cooling to a semiconductor chip is
provided. The improved integrated circuit package provides
increased operational bandwidth between different circuit devices,
e.g. logic and memory chips. The improved integrated circuit
package does not require changes in current CMOS processing
techniques. The structure includes the use of a silicon interposer.
The silicon interposer can consist of recycled rejected wafers-from
the front-end semiconductor processing. Micro-machined vias are
formed through the silicon interposer. The micro-machined vias
include electrical contacts which couple various integrated circuit
devices located on the opposing surfaces of the silicon interposer.
The packaging includes a Peltier element.
[0012] The Peltier element, using semiconductor-based materials,
functions as a small heat pump. By applying a low-voltage d-c
current to the Peltier element thermal energy is transferred with
the effect that one portion of the Peltier element is cooled and
another heated. In one embodiment, the heated portion of the
Peltier element is in contact with a heat sink or the outer cover
of the integrated circuit package and the cooled portion is in
contact with a semiconductor chip. Thus providing improved cooling
for high frequency, high speed microprocessor chip components. In
an alternative embodiment, the arrangement is reversed. This design
has no moving parts, is small in size and lightweight, and has the
ability to cool below or heat above the ambient temperature
surrounding integrated circuit devices.
[0013] These and other embodiments, aspects, advantages, and
features of the present invention will be set forth in part in the
description which follows, and in part will become apparent to
those skilled in the art by reference to the following description
of the invention and referenced drawings or by practice of the
invention. The aspects, advantages, and features of the invention
are realized and attained by means of the instrumentalities,
procedures, and combinations particularly pointed out in the
appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1A is a cross-sectional view illustrating an electronic
packaging assembly according to the teachings of the present
invention.
[0015] FIG. 1B is a cross-sectional view illustrating in greater
detail a portion of a particular embodiment for the present
invention.
[0016] FIG. 2 is a cross-sectional view illustrating an embodiment
of a Peltier element according to the teachings of the present
invention.
[0017] FIG. 3 is a block diagram illustrating an electronic system
according to an embodiment of the present invention.
[0018] FIGS. 4A-4G illustrate an embodiment of a process of
fabrication for a portion of an embodiment of the present
invention.
[0019] FIG. 5 illustrates, in flow diagram form, a methodical
aspect according to the teachings of the present invention.
[0020] FIG. 6 illustrates, in flow diagram form, a methodical
aspect for forming an electronic packaging assembly according to
the teachings of the present invention.
[0021] FIG. 7 illustrates, in flow diagram form, a methodical
aspect for packaging an integrated circuit according to the
teachings of the present invention.
[0022] FIG. 8 illustrates, in flow diagram form, an embodiment for
the method of cooling an integrated circuit according to the
teachings of the present invention.
[0023] FIG. 9 illustrates, in flow diagram form, an embodiment for
the method of heating an integrated circuit according to the
teachings of the present invention.
DETAILED DESCRIPTION
[0024] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention.
[0025] The terms wafer and substrate used in the following
description include any structure having an exposed surface with
which to form the integrated circuit (IC) structure of the
invention. The term substrate is understood to include
semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other
layers that have been fabricated thereupon. Both wafer and
substrate include doped and undoped semiconductors, epitaxial
semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator is defined to include any
material that is less electrically conductive than the materials
referred to as conductors. The following detailed description is,
therefore, not to be taken in a limiting sense, and the scope of
the present invention is defined only by the appended claims, along
with the full scope of equivalents to which such claims are
entitled.
[0026] The term "horizontal" as used in this application is defined
as a plane parallel to the conventional plane or surface of a wafer
or substrate, regardless of the orientation of the wafer or
substrate. The term "vertical" refers to a direction perpendicular
to the horizonal as defined above. Prepositions, such as "on",
"side" (as in "sidewall"), "higher", "lower", "over" and "under"
are defined with respect to the conventional plane or surface being
on the top surface of the wafer or substrate, regardless of the
orientation of the wafer or substrate.
[0027] Throughout this specification the designation "n+" refers to
semiconductor material that is heavily doped n-type semiconductor
material, e.g., monocrystalline silicon or polycrystalline silicon.
Similarly, the designation "p+" refers to semiconductor material
that is heavily doped p-type semiconductor material. The
designations "n-" and "p-" refer to lightly doped n and p-type
semiconductor materials, respectively.
[0028] Several illustrative embodiments of the present invention
are provided below. In one illustrative embodiment of the present
invention includes an electronic packaging assembly. The electronic
packaging assembly includes a silicon interposer which has a first
and second, or opposing sides. At least one semiconductor chip is
provided on a first side of the silicon interposer. The
semiconductor chip on the first side of the silicon interposer is
coupled to a metal-to-semiconductor junction. At least one
semiconductor chip is similarly provided on a second side of the
silicon interposer. A number of electrical connections are formed
through the silicon interposer and couple the semiconductor chips
located on each side of the silicon interposer.
[0029] In another embodiment, an electronic system module is
provided the electronic system module includes a silicon interposer
having opposing surfaces. A microprocessor, which has a circuit
side, faces a first one of the opposing surfaces of the silicon
interposer. The microprocessor on the first side of the silicon
interposer is coupled to a metal-to-semiconductor junction. A
memory chip, which has a circuit side, faces a second one of the
opposing surfaces of the silicon interposer. A number of electrical
connections extend through the silicon interposer and couple the
circuit side of the microprocessor to the circuit side of the
memory chip.
[0030] In another embodiment, a computer system is provided. The
computer system includes an electronic packaging assembly as
presented and described above. A number of external devices are
connected to the electronic packaging assembly by a system bus.
[0031] In another embodiment of the present invention, a method for
cooling an integrated circuit is provided. The method includes
using, or providing, a silicon interposer with opposing sides and
coupling a first semiconductor chip to a first side and coupling a
second semiconductor chip to a second side of the silicon
interposer. A number of electrical connections through the silicon
interposer electrically connect the first semiconductor chip to the
second semiconductor. The method further includes forming a
metal-to-semiconductor junction connected to the first
semiconductor chip. A current is then passed through the
metal-to-semiconductor junction in a direction so as to draw
thermal energy away from the first semiconductor chip.
[0032] In another embodiment of the present invention, a method for
heating an integrated circuit is provided. The method includes
using, or providing, a silicon interposer with opposing sides and
coupling a first semiconductor chip to a first side and coupling a
second semiconductor chip to a second side of the silicon
interposer. A number of electrical connections through the silicon
interposer electrically connect the first semiconductor chip to the
second semiconductor. The method further includes forming a
metal-to-semiconductor junction connected to the first
semiconductor chip. A current is then passed through the
metal-to-semiconductor junction in a direction so as to draw
thermal energy to the first semiconductor chip.
[0033] FIG. 1A is a cross-sectional view illustrating an electronic
packaging assembly 100, or electronic system module 100, according
to the teachings of the present invention. FIG. 1A includes a
silicon interposer 110. The silicon interposer 110 has opposing
surfaces which include a first one 115 of the opposing surfaces, or
first side 115 and a second one 120 of opposing surfaces, or second
side 120. In one exemplary embodiment, the silicon interposer 110
includes rejected silicon wafers which have been recycled from the
front-end of the semiconductor fabrication process. The silicon
interposer 110 may have active and passive devices built on one or
both sides, 115 and 120. Further, the active and passive devices
built on one or both sides, 115 and 120, can also include simple
capacitors using the insulator and metallurgy on one side of the
interposer, and can include devices such as, for example driver
circuits. The electronic packaging assembly 100 includes a number
of flip chips, 125A, 125B, . . . , 125N respectively, located on
the first side 115 of the silicon interposer 110. The electronic
packaging assembly 100 additionally includes a number of flip
chips, 125AA, 125BB, . . . , 125NN respectively, located on the
second side 120 of the silicon interposer 110. In one embodiment,
the a number of flip chips, 125A, 125B, . . . , 125N respectively,
located on the first side 115 includes at least one semiconductor
chip which is a microprocessor chip or other suitable logic chip.
In one embodiment, the number of flip chips, 125AA, 125BB, . . . ,
125NN respectively, located on the second side 120 includes at
least one semiconductor chip which is a memory chip. The memory
chip can include a dynamic random access memory (DRAM)-type chip.
Likewise, the memory chip can include a static random access memory
(SRAM)-type chip or flash electrically erasable program read only
memory (flash EEPROM)-type chip.
[0034] In alternative embodiments, the nature of the flip, or
semiconductor, chips coupled to the first and second sides, 115 and
120 respectively, can be reversed or varied in any desired order.
In one embodiment, capacitors are similarly included amongst the
number of flip-chips, 125A, 125B, . . . , 125N, or, 125AA, 125BB, .
. . 125NN, and coupled to the first or second side, 115 and 120
respectively. Likewise, microprocessors and memory chips may be
coupled to the same side of the silicon interposer. In one
embodiment, a second or even multiple microprocessors, capacitors,
and memory chips are included in the number of flip-chips, 125A,
125B, . . . , 125N, or, 125AA, 125BB, . . . , 125NN, and are
coupled with their circuit side 130 facing the first or second
side, 115 and 120 respectively, of the silicon interposer 110.
[0035] In constructing the silicon interposer 110 it is of course
necessary to complete all the high-temperature process steps prior
to the deposition of the interconnection metallurgy. In one
embodiment, the microprocessors or logic chips are included amongst
the number of flip-chips, 125A, 125B, . . . , 125N, and are mounted
with the circuit side 130 face-down (active circuit facing
downward) to the silicon interposer 110 by a ball-grid array (BGA)
131, micro-bump bonding (MBB) 131, or controlled collapse chip
connections (C-4) 131. In the same embodiment, DRAM chips which are
included amongst the number of flip-chips, 125AA, 125BB, . . . ,
125NN and are mounted on the other side of the silicon interposer
110 with the circuit side 130 facing upward using the same or
similar connection technology. Since chips will be mounted on both
sides of the interposer one must be cognizant of the effects of
high temperature on the solder joints previously made. This problem
may be solved either by using only localized heating to reflow the
solder on the second surface 120 or by using an appropriate solder
hierarchy. In one embodiment, lead 2.5% (by weight) Pb--Sn solder
is used on the C-4 joints of the chips, 125A, 125B, . . . , 125N,
mounted on the first side 115. In the same embodiment then, Pb-11
wt. % Sb is used for the chips, 125AA, 125BB, . . . , 125NN,
mounted on the second side 120, and Pb-62 Wt % Sn is used for card
soldering. In alternative embodiments, other lower-melting point
alloys, for example, Ga-based alloys can also be used.
[0036] FIG. 1A further illustrates that a number of electrical
connections 135 couple the number of semiconductor chips, 125A,
125B, . . . , 125N, mounted on the first side 115 to the number of
semiconductor chips, 125AA, 125BB, . . . , 125NN, mounted on the
second side 120 of the silicon interposer 110. The number of
electrical connections 135 include micro-machined vias which are
formed according to the detailed description provided below in
connection with FIGS. 4A-4G. The detailed description below for the
number of electrical connections 135 is provided according to
techniques taught in co-pending application Ser. No. 08/917,443,
entitled "Integrated Circuitry and Methods of Forming Integrated
Circuitry," filed on Aug. 22, 1997 or according to techniques
taught in application Ser. No. 08/917,449, entitled "Methods of
Forming Coaxial Integrated Circuitry Interconnect Lines, and
Integrated Circuitry," filed on Aug. 22, 1997, which applications
are incorporated herein by reference.
[0037] In one embodiment, as illustrate by FIG. 1A, at least one of
the number of semiconductor chips, 125A, 125B, . . . , 125N, is
further coupled to a metal-to-semiconductor junction 160, or any
other suitable Peltier Junction 160 which will produce a Peltier
effect. In this application, a current passed through a Peltier
Junction 160 is defined to produce a Peltier effect.
[0038] The Peltier effect is essentially the reverse of a
thermocouple effect. When a current is passed through a circuit
formed from two dissimilar metals or from a metal and a
semiconductor, or even certain other alloys and compounds, one
junction gives off heat and is cooled and the other absorbs heat
and becomes warm. The effect is reversible, e.g., if the current is
reversed, thermal energy will be drawn in the opposite direction,
the cool junction becomes warm and the hot junction cools. Larger
temperature differences are produced with metal-to-semiconductor
junctions than with metal-to-metal junctions. A metal-n-type
junction produces a temperature difference in the opposite sense to
that of a metal-p-type junction for the same direction of current
flow. A number of such junctions can be used to form a Peltier
element, an example of which is shown in FIG. 2.
[0039] The amount of thermal energy transferred, for a given
current, depends on the conductors. The thermal energy that is
emitted or absorbed with the passage of current through a junction
of dissimilar conductors is called the Peltier heat. The quotient
of the Peltier heat and the current is called the Peltier
coefficient. Also, a coefficient of performance (COP) is defined in
terms of the ratio of the quantity of absorbed heat to the inputted
power.
[0040] FIG. 1B is a cross-sectional view illustrating in greater
detail a portion of an exemplary embodiment of the present
invention. In FIG. 1B, Peltier element 160 includes a semiconductor
material layer 128 sandwiched between a first metal layer 127 and a
second metal layer 129. The arrangement forms a first
metal-to-semiconductor junction 171 between the first metal layer
127 and the semiconductor material layer 128. A second
metal-to-semiconductor junction 174 is formed between the second
metal layer 129 and the semiconductor material 128. In this
embodiment the semiconductor material can include a range of
semiconductor materials. In one such embodiment, the semiconductor
material layer 128 includes an alloy of Bismuth Telluride
(Bi.sub.2Te.sub.3) that has been suitably doped to provide either
distinct "n" or "p" characteristics. Alternatively an alloy of
Bismuth Telluride (Bi.sub.2Te.sub.3) can be suitably doped and
organized to provide individual blocks of elements having distinct
"n" and "p" characteristics, as illustrated by n-type blocks, 202A,
202B, . . . , 202C, etc. and by p-type blocks, 203A, 203B, . . . ,
203C, etc. in FIG. 2.
[0041] Often, Bi.sub.2Te.sub.3 is used as the doped semiconductor
material for near-room-temperature applications. Lead Telluride
(PbTe) and Silicon Germanium (SiGe) are frequently used as the
doped semiconductor material in higher temperature applications.
Similarly suited doping techniques are employed to create the
individual layers, or blocks, of Lead Telluride (PbTe) and Silicon
Germanium (SiGe) compounds having distinct "n" and "p"
characteristics.
[0042] FIG. 1B illustrates one embodiment in which the silicon
interposer 110 is further connected to an integrated circuit
package 136, or chip package 136. One of ordinary skill in the art
of semiconductor fabrication will understand the manner by which
the silicon interposer 110 may be connected to the chip package
136. An exemplary embodiment for constructing the same is provided
in U.S. Pat. No. 5,598,031, G.L. Groover, et al, "Electrically and
thermally enhanced package using a separate silicon substrate."
Another exemplary embodiment for constructing the same is provided
in U.S. Pat. No. 5,061,987, Hsia, Yukun, "Silicon substrate
multichip assembly." In the embodiment of FIG. 1B, the chip package
136 has first and second electrical leads, 137 and 138
respectively. Further, FIG. 1B illustrates that the electronic
packaging assembly 100 includes electrical coupling 139 between the
first electrical lead 137 and the silicon interposer 110, and hence
the semiconductor chip 125. FIG. 1B, further illustrates an
electrical coupling 133 between the semiconductor chip 125 and the
first metal layer 127. Also electrical coupling 139 is provided
between the second metal layer 129 and a second electrical lead 138
on chip package 136. In one embodiment, the electrical coupling,
139, 133, and 131 respectively, includes wire bonding. In an
alternative embodiment, the electrical coupling, 139, 133, and 131
respectively, includes any suitable coupling such as, for example,
tape automated bonding (TAB).
[0043] FIG. 1A, illustrated an alternative chip package embodiment
for transmitting and receiving signals from the silicon interposer
110. In FIG. 1A, signal connections from the electronic packaging
assembly 100 to other components in an extended electronic system
is provided by energy-efficient optical fiber interconnections. The
Peltier Junction 160 included in FIG. 1A includes the "sandwich
type" configuration illustrated by FIG. 1B, or an alternatively
suited configuration such as, for example, the embodiment
illustrated by FIG. 2. The Peltier Junction 160 is coupled to at
least one of the number of semiconductor chips, 125A, 125B, . . . ,
125N, 125AA, 125BB, . . . , 125NN, found on the silicon interposer
110. In the embodiment of FIG. 1A, the Peltier junction 160 is
shown coupled to chip 125A. The Peltier Junction 160 functions
according to operating techniques taught in this application or
according to equivalents of the same.
[0044] FIG. 1A illustrates an optical receiver 140 adapted to
receiving input signals from a fiber optical network 165. The
optical receiver 140 is further coupled to a sense amplifier 145.
The sense amplifier 145 and optical receiver 140 are located on the
silicon interposer 110. The sense amplifier 145 is further coupled
to at least one of the multiple semiconductor chips, 125A, 125B, .
. . , 125N, mounted on the first side 115 of the silicon interposer
110. Also illustrated in FIG. 1A is an optical emitter 150. The
optical emitter 150 couples signals from at least one of the
multiple semiconductor chips, 125A, 125B, . . . , 125N, mounted on
the first side 115 of the silicon interposer 110 to the fiber
optical network. FIG. 1A provides an illustration of the V-grooves
155 located on the silicon interposer 110. Optical fibers 156 are
mounted in the V-grooves 155 on the silicon interposer 110. In one
embodiment, the optical receiver 140 includes a thyristor detector
140. Further, in one particular embodiment, the thyristor detector
140 includes a silicon thyristor detector 140. In an alternative
embodiment, the thyristor detector 140 includes a gallium arsenide
(GaAs) thyristor detector 140. In one embodiment, the optical
emitter 150 includes a light-emitting diode (LED) 150. The
light-emitting diode (LED) 150 can be, for instance, a gallium
arsenide (GaAs) emitter. In one embodiment, the sense amplifier 145
includes a current sense amplifier 145. In one embodiment, as
illustrated in FIG. 1A, the coupling between the optical emitter
150 and the fiber optical network 165 includes optical fibers 156
mounted in V-grooves 155 on the silicon interposer 110. This
optical coupling can be achieved in any suitable manner and can
include two (2) way channel individual optical fibers 156. One
exemplary embodiment for such optical coupling is provided by the
method described in V. Vusirikala, et al., "Flip-chip optical fiber
attachment to a monolithic optical receiver chip," Proc. SPIE
Emerging Components and Technologies for all Optical Networks,
Philadelphia, Pa. USA, 24 Oct. 1995, pp. 52-58. In one embodiment,
the optical emitter 150 is flip chip bonded to the silicon
interposer and an end 157 in a V-groove 155 is adapted to reflect
light from the optical emitter 150 into the optical fibers 156.
This technique, too can be achieved in any suitable manner such as,
for example, the method described in O. Vendier et al., "A 155 Mbps
digital transmitter using GaAs thin film LEDs bonded to silicon
driver circuits," Dig. IEEE/LEOS Summer Topical Mtg., Keystone
Colo., 5-9 Aug. 1996, pp. 15-16.
[0045] As stated previously the direction of the current flow
through the Peltier junction 160 will determine the direction in
which heat energy is transported. The following provides several
exemplary embodiments of operation with reference to FIG. 1B. In
one operational embodiment of FIG. 1B, the semiconductor material
includes a p-type semiconductor material 128. In this embodiment, a
positive lead of a voltage supply is provided to electrical lead
137 and a negative lead of a voltage supply is provided to
electrical lead 138. Thus, current is passed from positive lead 137
in the direction of the arrow 170 across a metal-p-type
semiconductor junction 171 located between the first metal layer
127 and p-type semiconductor material 128. According to the Peltier
effect, thermal energy is thus drawn in, or follows, the direction
of the current flow through the p-type semiconductor. Thus, in this
operational embodiment of FIG. 1B, heat is drawn away from first
metal layer 127 with a resultant cooling effect at junction 171 and
a heating effect at junction 174. In this embodiment, thermal
energy, or Peltier heat, is drawn away from chip 125A and the chip
125A is cooled.
[0046] Conversely, if the layer 128 remains p-type but the current
flow is reversed, e.g., the polarity of the voltage supply is
reversed, then thermal energy continues to be drawn in, or follow,
the direction of current flow, but the direction is now in the
direction of arrow 172. In this operational embodiment of FIG. 1B,
heat is drawn toward first metal layer 127 with a resultant heating
effect at junction 171 and a cooling effect at junction 174. In
this embodiment, thermal energy, or Peltier heat is drawn toward
chip 125A and chip 125A is heated.
[0047] In another exemplary embodiment of FIG. 1B, semiconductor
layer 128 is an n-type semiconductor material 128. The positive
lead of a voltage supply is provided to electrical lead 137 and a
negative lead of a voltage supply is provided to electrical lead
138. Current is passed from positive lead 137 in the direction of
the arrow 170 across a metal-to n-type semiconductor junction 171
located between the first metal layer 127 and the n-type
semiconductor material 128. Current flow through the metal-to
n-type semiconductor results in thermal energy being transmitted in
the direction of arrow 172, opposite to the direction of current
flow. Thus, in this operational embodiment of FIG. 1B, heat is
drawn in the direction of junction 171 and away from junction 174.
The resultant effect is that junction 171 is heated and junction
174 is cooled. Consequently, thermal energy, or heat, is drawn to
chip 125A and chip 125A is heated.
[0048] Conversely, if the layer 128 remains n-type but the current
flow is reversed, e.g., the polarity of the voltage supply is
reversed, then thermal energy continues to be drawn opposite the
direction of current flow, but the direction is now in the
direction of arrow 170. In this operational embodiment of FIG. 1B,
heat is drawn away from first metal layer 127 with a resultant
cooling effect at junction 171 and a heating effect at junction
174. In this embodiment, thermal energy, or Peltier heat is drawn
away from chip 125A and chip 125A is cooled.
[0049] As is evident from the illustrations presented above, the
choice of semiconductor type material, e.g. n or p-type, and the
choice of current direction can be varied without departing from
the scope of the present invention. And, these above stated
variables can thus be coordinated to achieve a desired objective of
either heating or cooling chip 125A.
[0050] In one embodiment, shown in FIG. 1B, an insulator layer 126
separates the first metal layer 127 from the semiconductor chip
125A. In one embodiment, the adhesive insulator layer 126 includes
any suitable epoxy. In an alternative embodiment, the insulator
layer 126 can include any suitable material, as the same will be
understood upon reading this disclosure by one of ordinary skill in
the art of semiconductor fabrication. In one embodiment, the first
and second metal layers, 127 and 129 respectively, are formed of
copper (Cu). In an alternate embodiment, first and second metal
layers, 127 and 129, are formed from any suitable metal conductor
as will by understood upon reading this disclosure by one of
ordinary skill in the art of semiconductor fabrication.
[0051] FIG. 2 is a cross-sectional view illustrating another
embodiment of a Peltier element 200 according to the teachings of
the present invention. In FIG. 2, the direction in which the
current, indicated by arrows 219, is passed through the n-type,
202A, 202B, . . . , 202C, etc. and the p-type, 203A, 203B, . . . ,
203C, etc. semiconductor blocks determines which direction heat
energy is transferred. The direction in which the heat energy, or
Peltier heat, is transferred determines which surfaces 201A, 201B,
. . . , 201C, etc. or surfaces 204A, 204B, . . . , 204C, etc. are
cooled and heated respectively. In example, with the current
passing in the direction of arrows 219, heat is drawn in the
direction of the current for current passing through a p-type
semiconductor material, 203A, 203B, . . . , 203C, etc. and heat is
drawn opposite to the direction of current for current passing
through an n-type semiconductor material, 202A, 202B, . . . , 202C,
etc. Thus, in the embodiment of FIG. 2, surfaces 201A, 201B, . . .
, 201C, etc. are heated, and surfaces 204A, 204B, . . . , 204C,
etc. are cooled. Conversely, if the current is reversed from the
direction of arrows 219, then surfaces 201A, 201B, . . . , 201C,
etc. are cooled, and surfaces 204A, 204B, . . . , 204C, etc. are
heated.
[0052] In addition to the semiconductor materials presented
earlier, Peltier elements can be formed from a range of other
metal-to-metal, or metal-to-semiconductor combinations. FIG. 2 aids
in illustrating alternative embodiments of a Peltier element
constructed from such other combinations. As will be understood by
one of ordinary skill in the art of semiconductor fabrication from
reading this disclosure, substitution of these other combinations
is included within the scope of the present invention. The
following alternative embodiments provide example of this and all
offer a high coefficient of performance (COP). In one exemplary
embodiment each of the following combinations is adapted to provide
a COP of at least 0.6 or better.
[0053] In FIG. 2 an embodiment of an isolated illustration of a
Peltier element 200 is provided. In one embodiment, Peltier element
200 includes interfaces, or junctions, of metal-to-metal, or
metal-to-semiconductor materials. In the exemplary embodiment, the
Peltier element 200 of FIG. 2 can be suitably fabricated upon a
semiconductor wafer. In one exemplary alternative embodiment, the
n-type layers, or blocks, 202A, 202B, . . . , 202C, etc. and the
p-type layers, or blocks, 203A, 203B, . . . , 203C, etc. include
appropriately doped complex oxide semiconductors. In one
embodiment, the complex oxide semiconductors include strontium (Sr)
and titanium (Ti). In this embodiment the complex oxide
semiconductors possess an oxygen deficiency.
[0054] The following materials are also well suited for inclusion
as the n-type semiconductor layers, or blocks, 202A, 202B, . . . ,
202C, etc. and the p-type semiconductor layers, or blocks, 203A,
203B, . . . , 203C, etc. In one embodiment, the n-type
semiconductor layers, or blocks, 202A, 202B, . . . , 202C, etc. and
the p-type semiconductor layers, or blocks, 203A, 203B, . . . ,
203C, etc. are formed from a superlattice comprising alternating
layers of (PbTeSe).sub.m and (BiSb).sub.n where m and n are the
number of PbTeSe and BiSb monolayers per superlattice period. In
another embodiment, the n-type semiconductor layers, or blocks,
202A, 202B, . . . , 202C, etc. and the p-type semiconductor layers,
or blocks, 203A, 203B, . . . , 203C, etc. include semiconductor
alloys formed between Antimony (Sb) and a transition metal (T) of
Group VIII, including Cobalt, Rhodium, and Iridium (Co, Rh, and
Ir), and wherein the alloy has the general formula Tsb.sub.3. In
this embodiment, the semiconductor alloy includes a
skutterudite-type crystal lattice.
[0055] Similarly well suited to the teachings of the present
invention are Peltier elements 200 fabricated by thin film
technology onto the backside of an semiconductor chip. An
optimization of Bi.sub.2Te.sub.3 films includes forming a Copper
(Cu) and doped Bismuth Telluride (Bi.sub.2Te.sub.3) junction using
vacuum evaporation to form a thin film of p or n-doped Bismuth
Telluride (Bi.sub.2Te.sub.3). An alternate thin film junction is
formed using vacuum evaporation to form a thin film of p or n-doped
Antimony Telluride (Sb.sub.2Te.sub.3). The method for such an
embodiments, is provided, for example, according to the methods
taught by C. Shafai and M.J. Brett, "Optimization of
Bi.sub.2Te.sub.3 thin films for microintegrated Peltier heat
pumps", Journal of Vacuum Science and Technology A, vol.15, no. 5,
p. 2798-801, 1997, and C. Shafai and M.J. Brett, "A
micro-integrated Peltier heat pump for localized on-chip
temperature control", Canadian Journal of Physics, vol. 74, no. 1,
p. S139-42, 1996.
[0056] One of ordinary skill in the art of semiconductor
fabrication will, upon reading this disclosure, understand the
manner in which to construct the same. As explained above in detail
relative to FIGS. 1B and 2, doping and current flow direction
determine the direction in which thermal energy will be transported
in these various alternative embodiments. The doping and current
flow direction are arranged in accordance to the Peltier effect
physical laws to either draw Peltier heat to or away from a chosen
component. The effect being that the selected component is either
cooled or heated as desired.
[0057] FIG. 3 is a block diagram illustrating an electronic system
300 according to an embodiment of the present invention. The
electronic system 300 includes an electronic packaging assembly
305. The electronic packaging system 305 includes the electronic
packaging assembly 305 presented and described in detail above. The
electronic packaging assembly 305, specifically includes a
semiconductor chip which is further coupled to a
metal-to-semiconductor junction. The electronic system 300 includes
a number of external devices 310. The number of external devices
310 include, for example, memory controllers, microprocessors and
input/output bus units. The electronic system 300 includes a system
bus 320. The system bus 320 couples the number of external devices
310 to the electronic packaging assembly 305.
[0058] FIGS. 4A-4G illustrate an embodiment of the various
processing steps for fabricating the number of electrical
connections 135 through the silicon interposer 110, as illustrated
in FIG. 1. FIGS. 4A-4G illustrate an embodiment for forming
salicided connections 135 through the silicon interposer 110. FIG.
4A, is a top view illustrating generally a semiconductor wafer
fragment at 10.
[0059] In FIG. 4B, a cross-sectional view of FIG. 4A, taken along
cut-lines 4B-4B, is provided. The semiconductor wafer fragment at
10 includes a semiconductor conductive substrate. Wafer fragment 10
includes a front surface 14 and a back surface 16 and a thickness
(t) which is defined between the surfaces. An exemplary thickness
is around 30 mils or between around 750 to 800 micrometers (.mu.m).
FIG. 4B illustrates that amounts of the semiconductor conductive
wafer material are removed to form holes or passageways 18, 20, and
22. In one embodiment, such holes are formed to a depth of not less
than half of thickness (t). In one exemplary embodiment, holes 18,
20 and 22 extend perpendicularly through the entirety of wafer
fragment 12 and join with front and back surfaces 14 and 16,
respectively. In the exemplary embodiment, holes 18, 20, and 22
have aspect ratios greater than about 50. In another exemplary
embodiment, the holes 18, 20, and 22 have aspect ratios between
about 75 and 80.
[0060] In a preferred implementation, holes 18, 20, and 22 are
formed or otherwise provided prior to processing of any integrated
circuitry devices over either of surfaces 14, 16. In other words,
the holes are formed prior to patterning any conductive material
which is associated with integrated circuitry devices to be formed
over either of surfaces 14 and 16. The holes 18, 20, and 22 are
formed through suitable etching techniques. Alternatively, such
holes are formed or drilled with a suitable laser. In one exemplary
embodiment, very high aspect ratio holes are formed by placing the
wafer in a semiconductor wafer processor including a dipole-ring
magnetron etching reactor after which, the wafer is exposed to
conditions within the dipole ring magnetron etching reactor which
are sufficient to form holes which extend through the entirety of
the wafer. A suitable dipole ring magnetron (DRM) reactor is
described in an article entitled "Trench Storage Node Technology
for Gigabit DRAM Generations," Technical Digest of International
Electron Devices Meeting, Dec. 8-11, 1996, pages 507-510, published
IEEE, Catalog No. 96CH35961 and authored by Muller et al. Likewise,
a suitable DRM system and exemplary processing conditions are
described in an article entitled "A New High-Density Plasma Etching
System Using a Dipole-Ring Magnet," Jpn. J. Appl. Phys., 34, pt. 1,
no. 11, Nov. 1995, pages 6274-6278, and authored by Sekine et al.
After formation of the holes 18, 20, and 22, the same can be
temporarily filled with any material such as a photoresist to
enable subsequent processing of integrated circuitry devices over
either or both of surfaces 14 and 16.
[0061] As shown in FIG. 4C and in accordance with an exemplary
embodiment, integrated circuitry is formed or otherwise processed
and supported by wafer fragment 10. Integrated circuitry 24 can be
formed over or proximate front surface 14, back surface 16, or both
front and back surfaces 14, 16, respectively.
[0062] In FIG. 4D, wafer fragment 10 is exposed to conditions which
are effective to form respective dielectric layers 28, 30, and 32
within each of the holes 18, 20, and 22, and proximate the
respective interior surfaces 19, 21 and 23 thereof. In one
embodiment, dielectric layers 28, 30, and 32 comprise a
nitride-containing layer which is disposed proximate respective
interior surfaces 19, 21, and 23. An oxide-containing layer is
formed over the nitride-containing layer to provide a dielectric
(NO) layer within the hole. In an exemplary embodiment, a
nitride-containing layer is formed through chemical vapor
deposition (CVD) and the oxide layer by exposing the substrate to
oxidizing conditions. In one exemplary embodiment, dielectric
layers 28, 30 and 32 can constitute reoxidized, low-pressure,
chemical vapor deposition (LPCVD) on nitride film which forms the
illustrated and preferred (NO) dielectric layer. An exemplary
processing implementation includes in situ nitridation in ammonia
an 950.degree. C. LPCVD of nitride at 700.degree. C. takes place
with dichlorosilane and ammonia. Subsequently, reoxidation of the
nitride takes place at a temperature between 900.degree. C. and
950.degree. C. Alternatively, fast thermal processing (FTP) can
implement the above-described three processing steps into a single
processing run. Exemplary processing methods and systems are
described in the Mueller et al. article referenced above.
Alternatively, dielectric layers 28, 30 and 32 can comprise a thin,
silicon dioxide film. A desired and exemplary thickness of such
layers is between 50-100 nanometers (nm).
[0063] In FIG. 4E, electrical interconnect material 34, 36 and 38
is formed within holes 18, 20 and 22 respectively. Such material
fills each hole and is capable of electrically interconnecting
integrated circuitry formed over both front and back surfaces 14
and 16 respectively. In a preferred implementation, interconnect
material 34, 36 and 38 constitute a first material which is formed
within each respective hole and comprises polysilicon which is
formed through CVD. Excess first material can be removed through
conventional steps such as chemical mechanical planarization
(CMP).
[0064] In FIG. 4F, a second layer of electrically conductive
material 40 is formed over the first material 34, 36 and 38. In one
embodiment, such material is formed over both front and back
surfaces 14 and 16 respectively. In another embodiment, second
material 40 constitutes comprising a metal material which is
different from first material 34 and 36 and 38. In an exemplary
embodiment, second material 40 constitutes an aluminum comprising
layer or film. Such material film can be deposited through suitable
sputtering or evaporation techniques. Mechanical mask can be
utilized in order to define with more particularity the area over
which the preferred aluminum layer is deposited. Alternatively,
such a layer can be blanket deposited and subsequently processed as
described below.
[0065] FIG. 4G illustrates the wafer fragment 10 is exposed to
processing conditions which are effective to cause the second
material 40 to replace the first material 34, 36 and 38. In an
exemplary embodiment, the first material 34, 36 and 38 is
completely replaced with the second material 40 and the second
material 40 electrically interconnects at least some of the front
surface integrated circuitry 24 with at least some back surface
integrated circuitry 26. Exemplary processing conditions include
annealing the wafer at a temperature greater than or equal to about
500.degree. C. for a sufficient amount of time. The thickness of
the second material 40 will be determined by the size and
dimensions of the interconnecting holes or passageways. As a
guideline, and for a 0.175 micron diameter and 1.7 micron deep hole
with an aspect ratio of 10, an aluminum thickness of 0.5
micrometers (.mu.m) is sufficient to substitute the preferred
polysilicon. Annealing times and temperatures can be decreased by
forming a thin, e.g., 0.2 micrometer, titanium (Ti) layer over
material 40 prior to annealing. The Ti layer acts as a polysilicon
capture layer which accelerates the replacement of polysilicon with
aluminum. Exemplary processing methods are described in an article
entitled "Novel High-Aspect Ratio Plug for Logic/DRAM LSIs Using
Polysilicon-Aluminum Substrate (PAS)," Technical Digest of
International Electron Devices Meeting, Dec. 8-11, 1996, pages
946-948, published by IEEE, catalog number 96CH35961 and authored
by Horie et al. Excess aluminum in the substitute for polysilicon
can be removed through suitable processing techniques such as CMP.
Alternately considered, a conductive interconnect is provided
within wafer fragment 10 between and electrically connecting at
least a portion of the front-formed integrated circuitry and the
back-formed integrated circuitry. In the illustrated example, the
integrated circuitry is formed in advance of the formation of the
conductive interconnect.
[0066] In an alternate embodiment of the present invention, a
method of forming coaxial integrated circuitry and interconnect
lines is provided in application Ser. No. 08/917,449 entitled,
"Methods of Forming Coaxial Integrated Circuitry Interconnect
Lines, and Integrated Circuitry" filed on Aug. 22, 1997, which
application is incorporated herein by reference.
[0067] FIG. 5 illustrates, in flow diagram form, a methodical
aspect according to the teachings of the present invention. A
silicon interposer is formed at 510. The silicon interposer
includes micro-machined vias formed through the silicon interposer.
A number of flip chips are attached to the silicon interposer at
520. The flip chips couple to the micro-machined vias. A Peltier
element is coupled to at least one of the flip chips at 530.
[0068] FIG. 6 illustrates, in flow diagram form, a methodical
aspect according to the teachings of the present invention. A
silicon interposer is provided at 610. The silicon interposer has
opposing sides. A semiconductor chip is coupled to each of the
opposing sides of the silicon interposer at 620. Next, the
semiconductor chips on each side of the silicon interposer are
coupled to one another by a number of micro-machined vias at 630. A
Peltier element is coupled to at least one of the semiconductors
chips at 640.
[0069] FIG. 7 illustrates, in flow diagram form, a methodical
aspect according to the teachings of the present invention. A
silicon interposer is provided at 710. The silicon interposer has
opposing sides. A semiconductor chip is coupled to each of the
opposing sides of the silicon interposer at 720. Next, the
semiconductor chips on each side of the silicon interposer are
coupled to one another by a number of micro-machined vias at 730.
The micro-machined vias provided electrical connections between the
opposing sides of the silicon interposer. A metal-to-semiconductor
junction is coupled to at least one of the semiconductor chips at
740.
[0070] FIG. 8 illustrates, in flow diagram form, a methodical
aspect according to the teachings of the present invention. A
silicon interposer is provided at 810. The silicon interposer has
opposing sides. A first semiconductor chip is coupled to a first
side of the silicon interposer at 820. Next, a second semiconductor
chip is coupled to a second side of the silicon interposer at 830.
A metal-to-semiconductor junction is formed which couples to the
first semiconductor chip at 840. At 850, a current is passed
through the metal-to-semiconductor junction in a direction such
that a Peltier cooling effect occurs adjacent to the first
semiconductor chip.
[0071] FIG. 9 illustrates, in flow diagram form, a methodical
aspect according to the teachings of the present invention. A
silicon interposer is provided at 910. The silicon interposer has
opposing sides. A first semiconductor chip is coupled to a first
side of the silicon interposer at 920. Next, a second semiconductor
chip is coupled to a second side of the silicon interposer at 930.
A metal-to-semiconductor junction is formed which couples to the
first semiconductor chip at 940. At 950, a current is passed
through the metal-to-semiconductor junction in a direction such
that a Peltier heating effect occurs adjacent to the first
semiconductor chip.
CONCLUSION
[0072] Thus, an improved integrated circuit package for providing
built-in heating or cooling to a semiconductor chip is provided.
The improved integrated circuit package provides increased
operational bandwidth between different circuit devices, e.g. logic
and memory chips. The improved integrated circuit package does not
require changes in current CMOS processing techniques. The
structure includes the use of a silicon interposer. The silicon
interposer can consist of recycled rejected wafers from the
front-end semiconductor processing. Micro-machined vias are formed
through the silicon interposer. The micro-machined vias include
electrical contacts which couple various integrated circuit devices
located on the opposing surfaces of the silicon interposer. The
packaging includes a Peltier element.
[0073] The Peltier element, using semiconductor-based materials,
functions as a small heat pump. By applying a low-voltage d-c
current to the Peltier element thermal energy is transferred with
the effect that one portion of the Peltier element is cooled and
another heated. In one embodiment, the heated portion of the
Peltier element is in contact with a heat sink or the outer cover
of the integrated circuit package and the cooled portion is in
contact with a semiconductor chip. In an alternative embodiment,
the arrangement is reversed. This design has no moving parts, is
small in size and lightweight, and has the ability to cool below or
heat above the ambient temperature surrounding integrated circuit
devices.
[0074] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. It is to be understood that the above
description is intended to be illustrative, and not restrictive.
Combinations of the above embodiments, and other embodiments will
be apparent to those of skill in the art upon reviewing the above
description. The scope of the invention includes any other
applications in which the above structures and fabrication methods
are used. The scope of the invention should be determined with
reference to the appended claims, along with the full scope of
equivalents to which such claims are entitled.
* * * * *